50 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
53 #define VERSAL_OCLK_PHASE {0,  60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
165  * met at 25MHz for Default Speed mode, those controllers work at
166  * 19MHz instead
308 		 * requirements met at 25MHz for Default Speed mode,  in sdhci_arasan_set_clock()
309 		 * those controllers work at 19MHz instead.  in sdhci_arasan_set_clock()
645 		/* For 50MHz clock, 30 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
649 		/* For 100MHz clock, 15 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
654 		/* For 200MHz clock, 8 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
713 		/* For 50MHz clock, 120 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
717 		/* For 100MHz clock, 60 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
718 		tap_max = 60;  in sdhci_zynqmp_sampleclk_set_phase()
722 		/* For 200MHz clock, 30 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
772 		/* For 50MHz clock, 30 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
776 		/* For 100MHz clock, 15 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
781 		/* For 200MHz clock, 8 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
838 		/* For 50MHz clock, 120 Taps are available */  in sdhci_versal_sampleclk_set_phase()
842 		/* For 100MHz clock, 60 Taps are available */  in sdhci_versal_sampleclk_set_phase()
843 		tap_max = 60;  in sdhci_versal_sampleclk_set_phase()
847 		/* For 200MHz clock, 30 Taps are available */  in sdhci_versal_sampleclk_set_phase()
962  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
980 	u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_arasan_update_baseclkfreq()  local
993 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);  in sdhci_arasan_update_baseclkfreq()