xref: /OK3568_Linux_fs/kernel/drivers/video/fbdev/valkyriefb.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * valkyriefb.h: Constants of all sorts for valkyriefb
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Created 8 August 1998 by
6*4882a593Smuzhiyun  *  Martin Costabel <costabel@wanadoo.fr> and Kevin Schoedel
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Vmode-switching changes and vmode 15/17 modifications created 29 August
9*4882a593Smuzhiyun  * 1998 by Barry K. Nathan <barryn@pobox.com>.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * vmode 10 changed by Steven Borley <sjb@salix.demon.co.uk>, 14 mai 2000
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * Ported to 68k Macintosh by David Huggins-Daines <dhd@debian.org>
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * Based directly on:
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  *  controlfb.h: Constants of all sorts for controlfb
18*4882a593Smuzhiyun  *  Copyright (C) 1998 Daniel Jacobowitz <dan@debian.org>
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  *  pmc-valkyrie.h: Console support for PowerMac "control" display adaptor.
21*4882a593Smuzhiyun  *  Copyright (C) 1997 Paul Mackerras.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  *  pmc-valkyrie.c: Console support for PowerMac "control" display adaptor.
24*4882a593Smuzhiyun  *  Copyright (C) 1997 Paul Mackerras.
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  * and indirectly from:
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  *  pmc-control.h: Console support for PowerMac "control" display adaptor.
29*4882a593Smuzhiyun  *  Copyright (C) 1997 Paul Mackerras.
30*4882a593Smuzhiyun  *
31*4882a593Smuzhiyun  *  pmc-control.c: Console support for PowerMac "control" display adaptor.
32*4882a593Smuzhiyun  *  Copyright (C) 1996 Paul Mackerras.
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  *  platinumfb.c: Console support for PowerMac "platinum" display adaptor.
35*4882a593Smuzhiyun  *  Copyright (C) 1998 Jon Howell
36*4882a593Smuzhiyun  */
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #ifdef CONFIG_MAC
39*4882a593Smuzhiyun /* Valkyrie registers are word-aligned on m68k */
40*4882a593Smuzhiyun #define VALKYRIE_REG_PADSIZE	3
41*4882a593Smuzhiyun #else
42*4882a593Smuzhiyun #define VALKYRIE_REG_PADSIZE	7
43*4882a593Smuzhiyun #endif
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun  * Structure of the registers for the Valkyrie colormap registers.
47*4882a593Smuzhiyun  */
48*4882a593Smuzhiyun struct cmap_regs {
49*4882a593Smuzhiyun 	unsigned char addr;
50*4882a593Smuzhiyun 	char pad1[VALKYRIE_REG_PADSIZE];
51*4882a593Smuzhiyun 	unsigned char lut;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun  * Structure of the registers for the "valkyrie" display adaptor.
56*4882a593Smuzhiyun  */
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun struct vpreg {			/* padded register */
59*4882a593Smuzhiyun 	unsigned char r;
60*4882a593Smuzhiyun 	char pad[VALKYRIE_REG_PADSIZE];
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun struct valkyrie_regs {
65*4882a593Smuzhiyun 	struct vpreg mode;
66*4882a593Smuzhiyun 	struct vpreg depth;
67*4882a593Smuzhiyun 	struct vpreg status;
68*4882a593Smuzhiyun 	struct vpreg reg3;
69*4882a593Smuzhiyun 	struct vpreg intr;
70*4882a593Smuzhiyun 	struct vpreg reg5;
71*4882a593Smuzhiyun 	struct vpreg intr_enb;
72*4882a593Smuzhiyun 	struct vpreg msense;
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun  * Register initialization tables for the valkyrie display.
77*4882a593Smuzhiyun  *
78*4882a593Smuzhiyun  * Dot clock rate is
79*4882a593Smuzhiyun  * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
80*4882a593Smuzhiyun  */
81*4882a593Smuzhiyun struct valkyrie_regvals {
82*4882a593Smuzhiyun 	unsigned char mode;
83*4882a593Smuzhiyun 	unsigned char clock_params[3];
84*4882a593Smuzhiyun 	int	pitch[2];		/* bytes/line, indexed by color_mode */
85*4882a593Smuzhiyun 	int	hres;
86*4882a593Smuzhiyun 	int	vres;
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #ifndef CONFIG_MAC
90*4882a593Smuzhiyun /* Register values for 1024x768, 75Hz mode (17) */
91*4882a593Smuzhiyun /* I'm not sure which mode this is (16 or 17), so I'm defining it as 17,
92*4882a593Smuzhiyun  * since the equivalent mode in controlfb (which I adapted this from) is
93*4882a593Smuzhiyun  * also 17. Just because MacOS can't do this on Valkyrie doesn't mean we
94*4882a593Smuzhiyun  * can't! :)
95*4882a593Smuzhiyun  *
96*4882a593Smuzhiyun  * I was going to use 12, 31, 3, which I found by myself, but instead I'm
97*4882a593Smuzhiyun  * using 11, 28, 3 like controlfb, for consistency's sake.
98*4882a593Smuzhiyun  */
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun static struct valkyrie_regvals valkyrie_reg_init_17 = {
101*4882a593Smuzhiyun     15,
102*4882a593Smuzhiyun     { 11, 28, 3 },  /* pixel clock = 79.55MHz for V=74.50Hz */
103*4882a593Smuzhiyun     { 1024, 0 },
104*4882a593Smuzhiyun 	1024, 768
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* Register values for 1024x768, 72Hz mode (15) */
108*4882a593Smuzhiyun /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
109*4882a593Smuzhiyun  * that didn't match MacOS in the same video mode on this chip, and it also
110*4882a593Smuzhiyun  * caused the 15" Apple Studio Display to not work in this mode. While this
111*4882a593Smuzhiyun  * mode still doesn't match MacOS exactly (as far as I can tell), it's a lot
112*4882a593Smuzhiyun  * closer now, and it works with the Apple Studio Display.
113*4882a593Smuzhiyun  *
114*4882a593Smuzhiyun  * Yes, even though MacOS calls it "72Hz", in reality it's about 70Hz.
115*4882a593Smuzhiyun  */
116*4882a593Smuzhiyun static struct valkyrie_regvals valkyrie_reg_init_15 = {
117*4882a593Smuzhiyun     15,
118*4882a593Smuzhiyun     { 12, 29, 3 },  /* pixel clock = 75.52MHz for V=69.71Hz? */
119*4882a593Smuzhiyun 		    /* I interpolated the V=69.71 from the vmode 14 and old 15
120*4882a593Smuzhiyun 		     * numbers. Is this result correct?
121*4882a593Smuzhiyun 		     */
122*4882a593Smuzhiyun     { 1024, 0 },
123*4882a593Smuzhiyun 	1024, 768
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* Register values for 1024x768, 60Hz mode (14) */
127*4882a593Smuzhiyun static struct valkyrie_regvals valkyrie_reg_init_14 = {
128*4882a593Smuzhiyun     14,
129*4882a593Smuzhiyun     { 15, 31, 3 },  /* pixel clock = 64.58MHz for V=59.62Hz */
130*4882a593Smuzhiyun     { 1024, 0 },
131*4882a593Smuzhiyun 	1024, 768
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun #endif /* !defined CONFIG_MAC */
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /* Register values for 832x624, 75Hz mode (13) */
136*4882a593Smuzhiyun static struct valkyrie_regvals valkyrie_reg_init_13 = {
137*4882a593Smuzhiyun     9,
138*4882a593Smuzhiyun     { 23, 42, 3 },  /* pixel clock = 57.07MHz for V=74.27Hz */
139*4882a593Smuzhiyun     { 832, 0 },
140*4882a593Smuzhiyun 	832, 624
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun /* Register values for 800x600, 72Hz mode (11) */
144*4882a593Smuzhiyun static struct valkyrie_regvals valkyrie_reg_init_11 = {
145*4882a593Smuzhiyun     13,
146*4882a593Smuzhiyun     { 17, 27, 3 },  /* pixel clock = 49.63MHz for V=71.66Hz */
147*4882a593Smuzhiyun     { 800, 0 },
148*4882a593Smuzhiyun 	800, 600
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun /* Register values for 800x600, 60Hz mode (10) */
152*4882a593Smuzhiyun static struct valkyrie_regvals valkyrie_reg_init_10 = {
153*4882a593Smuzhiyun     12,
154*4882a593Smuzhiyun     { 25, 32, 3 },  /* pixel clock = 40.0015MHz,
155*4882a593Smuzhiyun                      used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
156*4882a593Smuzhiyun     { 800, 1600 },
157*4882a593Smuzhiyun 	800, 600
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /* Register values for 640x480, 67Hz mode (6) */
161*4882a593Smuzhiyun static struct valkyrie_regvals valkyrie_reg_init_6 = {
162*4882a593Smuzhiyun     6,
163*4882a593Smuzhiyun     { 14, 27, 2 },  /* pixel clock = 30.13MHz for V=66.43Hz */
164*4882a593Smuzhiyun     { 640, 1280 },
165*4882a593Smuzhiyun 	640, 480
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun /* Register values for 640x480, 60Hz mode (5) */
169*4882a593Smuzhiyun static struct valkyrie_regvals valkyrie_reg_init_5 = {
170*4882a593Smuzhiyun     11,
171*4882a593Smuzhiyun     { 23, 37, 2 },  /* pixel clock = 25.14MHz for V=59.85Hz */
172*4882a593Smuzhiyun     { 640, 1280 },
173*4882a593Smuzhiyun 	640, 480
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun static struct valkyrie_regvals *valkyrie_reg_init[VMODE_MAX] = {
177*4882a593Smuzhiyun 	NULL,
178*4882a593Smuzhiyun 	NULL,
179*4882a593Smuzhiyun 	NULL,
180*4882a593Smuzhiyun 	NULL,
181*4882a593Smuzhiyun 	&valkyrie_reg_init_5,
182*4882a593Smuzhiyun 	&valkyrie_reg_init_6,
183*4882a593Smuzhiyun 	NULL,
184*4882a593Smuzhiyun 	NULL,
185*4882a593Smuzhiyun 	NULL,
186*4882a593Smuzhiyun 	&valkyrie_reg_init_10,
187*4882a593Smuzhiyun 	&valkyrie_reg_init_11,
188*4882a593Smuzhiyun 	NULL,
189*4882a593Smuzhiyun 	&valkyrie_reg_init_13,
190*4882a593Smuzhiyun #ifndef CONFIG_MAC
191*4882a593Smuzhiyun 	&valkyrie_reg_init_14,
192*4882a593Smuzhiyun 	&valkyrie_reg_init_15,
193*4882a593Smuzhiyun 	NULL,
194*4882a593Smuzhiyun 	&valkyrie_reg_init_17,
195*4882a593Smuzhiyun #endif
196*4882a593Smuzhiyun };
197