1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2009
4*4882a593Smuzhiyun * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Description:
7*4882a593Smuzhiyun * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
8*4882a593Smuzhiyun * driver to function correctly on these systems.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/fsl_devices.h>
14*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "fsl_usb2_udc.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static struct clk *mxc_ahb_clk;
21*4882a593Smuzhiyun static struct clk *mxc_per_clk;
22*4882a593Smuzhiyun static struct clk *mxc_ipg_clk;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* workaround ENGcm09152 for i.MX35 */
25*4882a593Smuzhiyun #define MX35_USBPHYCTRL_OFFSET 0x600
26*4882a593Smuzhiyun #define USBPHYCTRL_OTGBASE_OFFSET 0x8
27*4882a593Smuzhiyun #define USBPHYCTRL_EVDO (1 << 23)
28*4882a593Smuzhiyun
fsl_udc_clk_init(struct platform_device * pdev)29*4882a593Smuzhiyun int fsl_udc_clk_init(struct platform_device *pdev)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct fsl_usb2_platform_data *pdata;
32*4882a593Smuzhiyun unsigned long freq;
33*4882a593Smuzhiyun int ret;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun pdata = dev_get_platdata(&pdev->dev);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
38*4882a593Smuzhiyun if (IS_ERR(mxc_ipg_clk)) {
39*4882a593Smuzhiyun dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
40*4882a593Smuzhiyun return PTR_ERR(mxc_ipg_clk);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
44*4882a593Smuzhiyun if (IS_ERR(mxc_ahb_clk)) {
45*4882a593Smuzhiyun dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
46*4882a593Smuzhiyun return PTR_ERR(mxc_ahb_clk);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun mxc_per_clk = devm_clk_get(&pdev->dev, "per");
50*4882a593Smuzhiyun if (IS_ERR(mxc_per_clk)) {
51*4882a593Smuzhiyun dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
52*4882a593Smuzhiyun return PTR_ERR(mxc_per_clk);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun clk_prepare_enable(mxc_ipg_clk);
56*4882a593Smuzhiyun clk_prepare_enable(mxc_ahb_clk);
57*4882a593Smuzhiyun clk_prepare_enable(mxc_per_clk);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
60*4882a593Smuzhiyun if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
61*4882a593Smuzhiyun freq = clk_get_rate(mxc_per_clk);
62*4882a593Smuzhiyun if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
63*4882a593Smuzhiyun (freq < 59999000 || freq > 60001000)) {
64*4882a593Smuzhiyun dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
65*4882a593Smuzhiyun ret = -EINVAL;
66*4882a593Smuzhiyun goto eclkrate;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun eclkrate:
73*4882a593Smuzhiyun clk_disable_unprepare(mxc_ipg_clk);
74*4882a593Smuzhiyun clk_disable_unprepare(mxc_ahb_clk);
75*4882a593Smuzhiyun clk_disable_unprepare(mxc_per_clk);
76*4882a593Smuzhiyun mxc_per_clk = NULL;
77*4882a593Smuzhiyun return ret;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
fsl_udc_clk_finalize(struct platform_device * pdev)80*4882a593Smuzhiyun int fsl_udc_clk_finalize(struct platform_device *pdev)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
83*4882a593Smuzhiyun int ret = 0;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* workaround ENGcm09152 for i.MX35 */
86*4882a593Smuzhiyun if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
87*4882a593Smuzhiyun unsigned int v;
88*4882a593Smuzhiyun struct resource *res = platform_get_resource
89*4882a593Smuzhiyun (pdev, IORESOURCE_MEM, 0);
90*4882a593Smuzhiyun void __iomem *phy_regs = ioremap(res->start +
91*4882a593Smuzhiyun MX35_USBPHYCTRL_OFFSET, 512);
92*4882a593Smuzhiyun if (!phy_regs) {
93*4882a593Smuzhiyun dev_err(&pdev->dev, "ioremap for phy address fails\n");
94*4882a593Smuzhiyun ret = -EINVAL;
95*4882a593Smuzhiyun goto ioremap_err;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
99*4882a593Smuzhiyun writel(v | USBPHYCTRL_EVDO,
100*4882a593Smuzhiyun phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun iounmap(phy_regs);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun ioremap_err:
107*4882a593Smuzhiyun /* ULPI transceivers don't need usbpll */
108*4882a593Smuzhiyun if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
109*4882a593Smuzhiyun clk_disable_unprepare(mxc_per_clk);
110*4882a593Smuzhiyun mxc_per_clk = NULL;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return ret;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
fsl_udc_clk_release(void)116*4882a593Smuzhiyun void fsl_udc_clk_release(void)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun if (mxc_per_clk)
119*4882a593Smuzhiyun clk_disable_unprepare(mxc_per_clk);
120*4882a593Smuzhiyun clk_disable_unprepare(mxc_ahb_clk);
121*4882a593Smuzhiyun clk_disable_unprepare(mxc_ipg_clk);
122*4882a593Smuzhiyun }
123