1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _RTW_GENERAL_DEF_H_ 16 #define _RTW_GENERAL_DEF_H_ 17 18 #define SEC_CAP_CHK_BMC BIT0 19 20 #define BIT0 0x00000001 21 #define BIT1 0x00000002 22 #define BIT2 0x00000004 23 #define BIT3 0x00000008 24 #define BIT4 0x00000010 25 #define BIT5 0x00000020 26 #define BIT6 0x00000040 27 #define BIT7 0x00000080 28 #define BIT8 0x00000100 29 #define BIT9 0x00000200 30 #define BIT10 0x00000400 31 #define BIT11 0x00000800 32 #define BIT12 0x00001000 33 #define BIT13 0x00002000 34 #define BIT14 0x00004000 35 #define BIT15 0x00008000 36 #define BIT16 0x00010000 37 #define BIT17 0x00020000 38 #define BIT18 0x00040000 39 #define BIT19 0x00080000 40 #define BIT20 0x00100000 41 #define BIT21 0x00200000 42 #define BIT22 0x00400000 43 #define BIT23 0x00800000 44 #define BIT24 0x01000000 45 #define BIT25 0x02000000 46 #define BIT26 0x04000000 47 #define BIT27 0x08000000 48 #define BIT28 0x10000000 49 #define BIT29 0x20000000 50 #define BIT30 0x40000000 51 #define BIT31 0x80000000 52 53 #define RTW_U32_MAX 0xFFFFFFFF 54 55 enum rtl_ic_id { 56 RTL8852A, 57 RTL8834A, 58 RTL8852B, 59 RTL8852C, 60 MAX_IC_ID 61 }; 62 63 /* BIT definition for combination */ 64 enum rtw_hci_type { 65 RTW_HCI_PCIE = BIT0, 66 RTW_HCI_USB = BIT1, 67 RTW_HCI_SDIO = BIT2, 68 RTW_HCI_GSPI = BIT3, 69 RTW_HCI_MAX, 70 }; 71 72 #define SM_PS_STATIC 0 73 #define SM_PS_DYNAMIC 1 74 #define SM_PS_INVALID 2 75 #define SM_PS_DISABLE 3 76 77 #define MAC_ADDRESS_LENGTH 6 78 #define IPV4_ADDRESS_LENGTH 4 79 #define IPV6_ADDRESS_LENGTH 16 80 81 /* Core shall translate system condition into device state for PHL controller */ 82 enum rtw_dev_state { 83 RTW_DEV_WORKING = BIT0, 84 RTW_DEV_SUSPENDING = BIT1, 85 RTW_DEV_RESUMING = BIT2, 86 RTW_DEV_SURPRISE_REMOVAL = BIT3, 87 RTW_DEV_SHUTTING_DOWN = BIT4, /* set by core */ 88 RTW_DEV_MAX 89 }; 90 91 #define RTW_RATE_MODE_MASK (BIT(7) | BIT(8)) 92 #define RTW_RATE_MODE_SHIFT 7 93 #define RTW_RATE_INDEX_MASK 0x007f 94 95 #define RTW_GET_RATE_MODE(_rtw_data_rate) (u16)((_rtw_data_rate & RTW_RATE_MODE_MASK) >> RTW_RATE_MODE_SHIFT) 96 #define RTW_GET_RATE_INDEX(_rtw_data_rate) (u16)(_rtw_data_rate & RTW_RATE_INDEX_MASK) 97 98 enum rtw_rate_mode { 99 RTW_LEGACY_MODE = 0, 100 RTW_HT_MODE = 1, 101 RTW_VHT_MODE = 2, 102 RTW_HE_MODE = 3 103 }; 104 105 enum rtw_data_rate { 106 RTW_DATA_RATE_CCK1 = 0x0, 107 RTW_DATA_RATE_CCK2 = 0x1, 108 RTW_DATA_RATE_CCK5_5 = 0x2, 109 RTW_DATA_RATE_CCK11 = 0x3, 110 RTW_DATA_RATE_OFDM6 = 0x4, 111 RTW_DATA_RATE_OFDM9 = 0x5, 112 RTW_DATA_RATE_OFDM12 = 0x6, 113 RTW_DATA_RATE_OFDM18 = 0x7, 114 RTW_DATA_RATE_OFDM24 = 0x8, 115 RTW_DATA_RATE_OFDM36 = 0x9, 116 RTW_DATA_RATE_OFDM48 = 0xA, 117 RTW_DATA_RATE_OFDM54 = 0xB, 118 RTW_DATA_RATE_MCS0 = 0x80, 119 RTW_DATA_RATE_MCS1 = 0x81, 120 RTW_DATA_RATE_MCS2 = 0x82, 121 RTW_DATA_RATE_MCS3 = 0x83, 122 RTW_DATA_RATE_MCS4 = 0x84, 123 RTW_DATA_RATE_MCS5 = 0x85, 124 RTW_DATA_RATE_MCS6 = 0x86, 125 RTW_DATA_RATE_MCS7 = 0x87, 126 RTW_DATA_RATE_MCS8 = 0x88, 127 RTW_DATA_RATE_MCS9 = 0x89, 128 RTW_DATA_RATE_MCS10 = 0x8A, 129 RTW_DATA_RATE_MCS11 = 0x8B, 130 RTW_DATA_RATE_MCS12 = 0x8C, 131 RTW_DATA_RATE_MCS13 = 0x8D, 132 RTW_DATA_RATE_MCS14 = 0x8E, 133 RTW_DATA_RATE_MCS15 = 0x8F, 134 RTW_DATA_RATE_MCS16 = 0x90, 135 RTW_DATA_RATE_MCS17 = 0x91, 136 RTW_DATA_RATE_MCS18 = 0x92, 137 RTW_DATA_RATE_MCS19 = 0x93, 138 RTW_DATA_RATE_MCS20 = 0x94, 139 RTW_DATA_RATE_MCS21 = 0x95, 140 RTW_DATA_RATE_MCS22 = 0x96, 141 RTW_DATA_RATE_MCS23 = 0x97, 142 RTW_DATA_RATE_MCS24 = 0x98, 143 RTW_DATA_RATE_MCS25 = 0x99, 144 RTW_DATA_RATE_MCS26 = 0x9A, 145 RTW_DATA_RATE_MCS27 = 0x9B, 146 RTW_DATA_RATE_MCS28 = 0x9C, 147 RTW_DATA_RATE_MCS29 = 0x9D, 148 RTW_DATA_RATE_MCS30 = 0x9E, 149 RTW_DATA_RATE_MCS31 = 0x9F, 150 RTW_DATA_RATE_VHT_NSS1_MCS0 = 0x100, 151 RTW_DATA_RATE_VHT_NSS1_MCS1 = 0x101, 152 RTW_DATA_RATE_VHT_NSS1_MCS2 = 0x102, 153 RTW_DATA_RATE_VHT_NSS1_MCS3 = 0x103, 154 RTW_DATA_RATE_VHT_NSS1_MCS4 = 0x104, 155 RTW_DATA_RATE_VHT_NSS1_MCS5 = 0x105, 156 RTW_DATA_RATE_VHT_NSS1_MCS6 = 0x106, 157 RTW_DATA_RATE_VHT_NSS1_MCS7 = 0x107, 158 RTW_DATA_RATE_VHT_NSS1_MCS8 = 0x108, 159 RTW_DATA_RATE_VHT_NSS1_MCS9 = 0x109, 160 RTW_DATA_RATE_VHT_NSS2_MCS0 = 0x110, 161 RTW_DATA_RATE_VHT_NSS2_MCS1 = 0x111, 162 RTW_DATA_RATE_VHT_NSS2_MCS2 = 0x112, 163 RTW_DATA_RATE_VHT_NSS2_MCS3 = 0x113, 164 RTW_DATA_RATE_VHT_NSS2_MCS4 = 0x114, 165 RTW_DATA_RATE_VHT_NSS2_MCS5 = 0x115, 166 RTW_DATA_RATE_VHT_NSS2_MCS6 = 0x116, 167 RTW_DATA_RATE_VHT_NSS2_MCS7 = 0x117, 168 RTW_DATA_RATE_VHT_NSS2_MCS8 = 0x118, 169 RTW_DATA_RATE_VHT_NSS2_MCS9 = 0x119, 170 RTW_DATA_RATE_VHT_NSS3_MCS0 = 0x120, 171 RTW_DATA_RATE_VHT_NSS3_MCS1 = 0x121, 172 RTW_DATA_RATE_VHT_NSS3_MCS2 = 0x122, 173 RTW_DATA_RATE_VHT_NSS3_MCS3 = 0x123, 174 RTW_DATA_RATE_VHT_NSS3_MCS4 = 0x124, 175 RTW_DATA_RATE_VHT_NSS3_MCS5 = 0x125, 176 RTW_DATA_RATE_VHT_NSS3_MCS6 = 0x126, 177 RTW_DATA_RATE_VHT_NSS3_MCS7 = 0x127, 178 RTW_DATA_RATE_VHT_NSS3_MCS8 = 0x128, 179 RTW_DATA_RATE_VHT_NSS3_MCS9 = 0x129, 180 RTW_DATA_RATE_VHT_NSS4_MCS0 = 0x130, 181 RTW_DATA_RATE_VHT_NSS4_MCS1 = 0x131, 182 RTW_DATA_RATE_VHT_NSS4_MCS2 = 0x132, 183 RTW_DATA_RATE_VHT_NSS4_MCS3 = 0x133, 184 RTW_DATA_RATE_VHT_NSS4_MCS4 = 0x134, 185 RTW_DATA_RATE_VHT_NSS4_MCS5 = 0x135, 186 RTW_DATA_RATE_VHT_NSS4_MCS6 = 0x136, 187 RTW_DATA_RATE_VHT_NSS4_MCS7 = 0x137, 188 RTW_DATA_RATE_VHT_NSS4_MCS8 = 0x138, 189 RTW_DATA_RATE_VHT_NSS4_MCS9 = 0x139, 190 RTW_DATA_RATE_HE_NSS1_MCS0 = 0x180, 191 RTW_DATA_RATE_HE_NSS1_MCS1 = 0x181, 192 RTW_DATA_RATE_HE_NSS1_MCS2 = 0x182, 193 RTW_DATA_RATE_HE_NSS1_MCS3 = 0x183, 194 RTW_DATA_RATE_HE_NSS1_MCS4 = 0x184, 195 RTW_DATA_RATE_HE_NSS1_MCS5 = 0x185, 196 RTW_DATA_RATE_HE_NSS1_MCS6 = 0x186, 197 RTW_DATA_RATE_HE_NSS1_MCS7 = 0x187, 198 RTW_DATA_RATE_HE_NSS1_MCS8 = 0x188, 199 RTW_DATA_RATE_HE_NSS1_MCS9 = 0x189, 200 RTW_DATA_RATE_HE_NSS1_MCS10 = 0x18A, 201 RTW_DATA_RATE_HE_NSS1_MCS11 = 0x18B, 202 RTW_DATA_RATE_HE_NSS2_MCS0 = 0x190, 203 RTW_DATA_RATE_HE_NSS2_MCS1 = 0x191, 204 RTW_DATA_RATE_HE_NSS2_MCS2 = 0x192, 205 RTW_DATA_RATE_HE_NSS2_MCS3 = 0x193, 206 RTW_DATA_RATE_HE_NSS2_MCS4 = 0x194, 207 RTW_DATA_RATE_HE_NSS2_MCS5 = 0x195, 208 RTW_DATA_RATE_HE_NSS2_MCS6 = 0x196, 209 RTW_DATA_RATE_HE_NSS2_MCS7 = 0x197, 210 RTW_DATA_RATE_HE_NSS2_MCS8 = 0x198, 211 RTW_DATA_RATE_HE_NSS2_MCS9 = 0x199, 212 RTW_DATA_RATE_HE_NSS2_MCS10 = 0x19A, 213 RTW_DATA_RATE_HE_NSS2_MCS11 = 0x19B, 214 RTW_DATA_RATE_HE_NSS3_MCS0 = 0x1A0, 215 RTW_DATA_RATE_HE_NSS3_MCS1 = 0x1A1, 216 RTW_DATA_RATE_HE_NSS3_MCS2 = 0x1A2, 217 RTW_DATA_RATE_HE_NSS3_MCS3 = 0x1A3, 218 RTW_DATA_RATE_HE_NSS3_MCS4 = 0x1A4, 219 RTW_DATA_RATE_HE_NSS3_MCS5 = 0x1A5, 220 RTW_DATA_RATE_HE_NSS3_MCS6 = 0x1A6, 221 RTW_DATA_RATE_HE_NSS3_MCS7 = 0x1A7, 222 RTW_DATA_RATE_HE_NSS3_MCS8 = 0x1A8, 223 RTW_DATA_RATE_HE_NSS3_MCS9 = 0x1A9, 224 RTW_DATA_RATE_HE_NSS3_MCS10 = 0x1AA, 225 RTW_DATA_RATE_HE_NSS3_MCS11 = 0x1AB, 226 RTW_DATA_RATE_HE_NSS4_MCS0 = 0x1B0, 227 RTW_DATA_RATE_HE_NSS4_MCS1 = 0x1B1, 228 RTW_DATA_RATE_HE_NSS4_MCS2 = 0x1B2, 229 RTW_DATA_RATE_HE_NSS4_MCS3 = 0x1B3, 230 RTW_DATA_RATE_HE_NSS4_MCS4 = 0x1B4, 231 RTW_DATA_RATE_HE_NSS4_MCS5 = 0x1B5, 232 RTW_DATA_RATE_HE_NSS4_MCS6 = 0x1B6, 233 RTW_DATA_RATE_HE_NSS4_MCS7 = 0x1B7, 234 RTW_DATA_RATE_HE_NSS4_MCS8 = 0x1B8, 235 RTW_DATA_RATE_HE_NSS4_MCS9 = 0x1B9, 236 RTW_DATA_RATE_HE_NSS4_MCS10 = 0x1BA, 237 RTW_DATA_RATE_HE_NSS4_MCS11 = 0x1BB, 238 RTW_DATA_RATE_MAX = 0x1FF 239 }; 240 241 enum rtw_gi_ltf { 242 RTW_GILTF_LGI_4XHE32 = 0, 243 RTW_GILTF_SGI_4XHE08 = 1, 244 RTW_GILTF_2XHE16 = 2, 245 RTW_GILTF_2XHE08 = 3, 246 RTW_GILTF_1XHE16 = 4, 247 RTW_GILTF_1XHE08 = 5, 248 RTW_GILTF_MAX 249 }; 250 251 252 /* 11ax spec define for HE Trigger Frame, only used for HE Trigger Frame! */ 253 enum rtw_gi_ltf_ul_tb { 254 RTW_TB_GILTF_1XHE16 = 0, 255 RTW_TB_GILTF_2XHE16 = 1, 256 RTW_TB_GILTF_4XHE32 = 2, 257 RTW_TB_GILTF_MAX 258 }; 259 260 #define RTW_PHL_MAX_RF_PATH 4 261 enum rf_path { 262 RF_PATH_A = 0, 263 RF_PATH_B = 1, 264 RF_PATH_C = 2, 265 RF_PATH_D = 3, 266 RF_PATH_AB, 267 RF_PATH_AC, 268 RF_PATH_AD, 269 RF_PATH_BC, 270 RF_PATH_BD, 271 RF_PATH_CD, 272 RF_PATH_ABC, 273 RF_PATH_ABD, 274 RF_PATH_ACD, 275 RF_PATH_BCD, 276 RF_PATH_ABCD, 277 }; 278 279 /*HW SPEC & SW/HW CAP*/ 280 #define PROTO_CAP_11B BIT0 281 #define PROTO_CAP_11G BIT1 282 #define PROTO_CAP_11N BIT2 283 #define PROTO_CAP_11AC BIT3 284 #define PROTO_CAP_11AX BIT4 285 #define PROTO_CAP_BIT_NUM 4 286 287 enum wlan_mode { 288 WLAN_MD_INVALID = 0, 289 WLAN_MD_11B = BIT0, 290 WLAN_MD_11A = BIT1, 291 WLAN_MD_11G = BIT2, 292 WLAN_MD_11N = BIT3, 293 WLAN_MD_11AC = BIT4, 294 WLAN_MD_11AX = BIT5, 295 296 /* Type for current wireless mode */ 297 WLAN_MD_11BG = (WLAN_MD_11B | WLAN_MD_11G), 298 WLAN_MD_11GN = (WLAN_MD_11G | WLAN_MD_11N), 299 WLAN_MD_11AN = (WLAN_MD_11A | WLAN_MD_11N), 300 WLAN_MD_11BN = (WLAN_MD_11B | WLAN_MD_11N), 301 WLAN_MD_11BGN = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N), 302 WLAN_MD_11BGAC = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11AC), 303 WLAN_MD_11BGAX = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11AX), 304 WLAN_MD_11GAC = (WLAN_MD_11G | WLAN_MD_11AC), 305 WLAN_MD_11GAX = (WLAN_MD_11G | WLAN_MD_11AX), 306 WLAN_MD_11A_AC = (WLAN_MD_11A | WLAN_MD_11AC), 307 WLAN_MD_11A_AX = (WLAN_MD_11A | WLAN_MD_11AX), 308 309 /* Capability -Type for registry default wireless mode */ 310 WLAN_MD_11AGN = (WLAN_MD_11A | WLAN_MD_11G | WLAN_MD_11N ), 311 WLAN_MD_11ABGN = (WLAN_MD_11A | WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N ), 312 WLAN_MD_11ANAC = (WLAN_MD_11A | WLAN_MD_11N | WLAN_MD_11AC), 313 WLAN_MD_11BGNAC = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC), 314 WLAN_MD_11GNAC = (WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC), 315 WLAN_MD_24G_MIX = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC | WLAN_MD_11AX), 316 WLAN_MD_5G_MIX = (WLAN_MD_11A | WLAN_MD_11N | WLAN_MD_11AC | WLAN_MD_11AX), 317 WLAN_MD_MAX = (WLAN_MD_24G_MIX|WLAN_MD_5G_MIX), 318 }; 319 320 enum band_type { 321 BAND_ON_24G = 0, 322 BAND_ON_5G = 1, 323 BAND_ON_6G = 2, 324 BAND_MAX, 325 }; 326 327 /*HW SPEC & SW/HW CAP*/ 328 #define BAND_CAP_2G BIT(BAND_ON_24G) 329 #define BAND_CAP_5G BIT(BAND_ON_5G) 330 #define BAND_CAP_6G BIT(BAND_ON_6G) 331 #define BAND_CAP_BIT_NUM 3 332 333 enum channel_width { 334 CHANNEL_WIDTH_20 = 0, 335 CHANNEL_WIDTH_40 = 1, 336 CHANNEL_WIDTH_80 = 2, 337 CHANNEL_WIDTH_160 = 3, 338 CHANNEL_WIDTH_80_80 = 4, 339 CHANNEL_WIDTH_5 = 5, 340 CHANNEL_WIDTH_10 = 6, 341 CHANNEL_WIDTH_MAX = 7, 342 }; 343 344 /*HW SPEC & SW/HW CAP*/ 345 #define BW_CAP_20M BIT(CHANNEL_WIDTH_20) 346 #define BW_CAP_40M BIT(CHANNEL_WIDTH_40) 347 #define BW_CAP_80M BIT(CHANNEL_WIDTH_80) 348 #define BW_CAP_160M BIT(CHANNEL_WIDTH_160) 349 #define BW_CAP_80_80M BIT(CHANNEL_WIDTH_80_80) 350 #define BW_CAP_5M BIT(CHANNEL_WIDTH_5) 351 #define BW_CAP_10M BIT(CHANNEL_WIDTH_10) 352 #define BW_CAP_BIT_NUM 7 353 354 355 /* 356 * Represent Extention Channel Offset in HT Capabilities 357 * Secondary Channel Offset 358 * 0 -SCN, 1 -SCA, 2 -RSVD, 3 - SCB 359 * 360 */ 361 enum chan_offset { 362 CHAN_OFFSET_NO_EXT = 0, /*SCN - no secondary channel*/ 363 CHAN_OFFSET_UPPER = 1, /*SCA - secondary channel above*/ 364 CHAN_OFFSET_NO_DEF = 2, /*Reserved*/ 365 CHAN_OFFSET_LOWER = 3, /*SCB - secondary channel below*/ 366 }; 367 368 enum rf_type { 369 RF_1T1R = 0, 370 RF_1T2R = 1, 371 RF_2T2R = 2, 372 RF_2T3R = 3, 373 RF_2T4R = 4, 374 RF_3T3R = 5, 375 RF_3T4R = 6, 376 RF_4T4R = 7, 377 RF_TYPE_MAX, 378 }; 379 380 enum rtw_rf_state { 381 RTW_RF_ON, 382 RTW_RF_OFF, 383 RTW_RF_MAX 384 }; 385 386 enum rtw_usb_speed { 387 RTW_USB_SPEED_LOW = 0, /*U2 (2.0)- 1.0 - 1.5 Mbps - 0.192MBs*/ 388 RTW_USB_SPEED_FULL = 1, /*U2 (2.0)- 1.1 - 12 Mbps - 1.5MBs*/ 389 RTW_USB_SPEED_HIGH = 2, /*U2 (2.0)- 2.1 - 480 Mbps - 60MBs*/ 390 RTW_USB_SPEED_SUPER = 3, /*U3 (3.2 Gen 1)- 3.0 - 5 Gbps - 640MBs*/ 391 RTW_USB_SPEED_SUPER_10G = 4, /*U3 (3.2 Gen 2)- 3.1 - 10 Gbps - 1280MBs*/ 392 RTW_USB_SPEED_SUPER_20G = 5, /*U3 (3.2 Gen 2x2)- 3.2 - 20 Gbps - 2560MBs*/ 393 394 /* keep last */ 395 RTW_USB_SPEED_MAX, 396 RTW_USB_SPEED_UNKNOWN = RTW_USB_SPEED_MAX, 397 }; 398 399 #define USB_SUPER_SPEED_BULK_SIZE 1024 /* usb 3.0 */ 400 #define USB_HIGH_SPEED_BULK_SIZE 512 /* usb 2.0 */ 401 #define USB_FULL_SPEED_BULK_SIZE 64 /* usb 1.1 */ 402 403 #define IV_LENGTH 8 404 405 enum rtw_enc_algo { 406 RTW_ENC_NONE, 407 RTW_ENC_WEP40, 408 RTW_ENC_WEP104, 409 RTW_ENC_TKIP, 410 RTW_ENC_WAPI, 411 RTW_ENC_GCMSMS4, 412 RTW_ENC_CCMP, 413 RTW_ENC_CCMP256, 414 RTW_ENC_GCMP, 415 RTW_ENC_GCMP256, 416 RTW_ENC_BIP_CCMP128, 417 RTW_ENC_MAX 418 }; 419 420 enum rtw_sec_ent_mode { 421 RTW_SEC_ENT_MODE_0, /* No key */ 422 RTW_SEC_ENT_MODE_1, /* WEP */ 423 RTW_SEC_ENT_MODE_2, /* 2 unicast + 3 multicast + 2 BIP keys */ 424 RTW_SEC_ENT_MODE_3, /* 2 unicast + 4 multicast + 1 BIP keys */ 425 }; 426 427 enum rtw_sec_key_type { 428 RTW_SEC_KEY_UNICAST, 429 RTW_SEC_KEY_MULTICAST, 430 RTW_SEC_KEY_BIP, 431 RTW_SEC_KEY_MAX 432 }; 433 434 /** 435 * Figure 27-7 + Table 9-31h from Ax Spec D4.2 436 * B7-B1: 437 * RU26 : 0 1 2 3 4 5 6 7 8 9 10 ... 36 438 * RU52 : 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 439 * RU106 : 53 54 55 56 57 58 59 60 440 * RU242 : 61 62 63 64 441 * RU484 : 65 66 442 * RU996 : 67 443 * RU996x2: 68 444 **/ 445 enum rtw_he_ru_idx { 446 /* 20MHz - 1 */ 447 RTW_HE_RU26_1 = 0, 448 RTW_HE_RU26_2, 449 RTW_HE_RU26_3, 450 RTW_HE_RU26_4, 451 RTW_HE_RU26_5, 452 RTW_HE_RU26_6, 453 RTW_HE_RU26_7, 454 RTW_HE_RU26_8, 455 RTW_HE_RU26_9, 456 /* 20MHz - 2 */ 457 RTW_HE_RU26_10, 458 RTW_HE_RU26_11, 459 RTW_HE_RU26_12, 460 RTW_HE_RU26_13, 461 RTW_HE_RU26_14, 462 RTW_HE_RU26_15, 463 RTW_HE_RU26_16, 464 RTW_HE_RU26_17, 465 RTW_HE_RU26_18, 466 /* Center 26-tone */ 467 RTW_HE_RU26_19, 468 /* 20MHz - 3 */ 469 RTW_HE_RU26_20, 470 RTW_HE_RU26_21, 471 RTW_HE_RU26_22, 472 RTW_HE_RU26_23, 473 RTW_HE_RU26_24, 474 RTW_HE_RU26_25, 475 RTW_HE_RU26_26, 476 RTW_HE_RU26_27, 477 RTW_HE_RU26_28, 478 /* 20MHz - 4 */ 479 RTW_HE_RU26_29, 480 RTW_HE_RU26_30, 481 RTW_HE_RU26_31, 482 RTW_HE_RU26_32, 483 RTW_HE_RU26_33, 484 RTW_HE_RU26_34, 485 RTW_HE_RU26_35, 486 RTW_HE_RU26_36, 487 RTW_HE_RU26_37 = 36, 488 /* 20MHz - 1 */ 489 RTW_HE_RU52_1 = 37, 490 RTW_HE_RU52_2, 491 RTW_HE_RU52_3, 492 RTW_HE_RU52_4, 493 /* 20MHz - 2 */ 494 RTW_HE_RU52_5, 495 RTW_HE_RU52_6, 496 RTW_HE_RU52_7, 497 RTW_HE_RU52_8, 498 /* 20MHz - 3 */ 499 RTW_HE_RU52_9, 500 RTW_HE_RU52_10, 501 RTW_HE_RU52_11, 502 RTW_HE_RU52_12, 503 /* 20MHz - 4 */ 504 RTW_HE_RU52_13, 505 RTW_HE_RU52_14, 506 RTW_HE_RU52_15, 507 RTW_HE_RU52_16 = 52, 508 /* 20MHz - 1 */ 509 RTW_HE_RU106_1 = 53, 510 RTW_HE_RU106_2, 511 /* 20MHz - 2 */ 512 RTW_HE_RU106_3, 513 RTW_HE_RU106_4, 514 /* 20MHz - 3 */ 515 RTW_HE_RU106_5, 516 RTW_HE_RU106_6, 517 /* 20MHz - 4 */ 518 RTW_HE_RU106_7, 519 RTW_HE_RU106_8 = 60, 520 /* 20MHz */ 521 RTW_HE_RU242_1 = 61, 522 RTW_HE_RU242_2, 523 RTW_HE_RU242_3, 524 RTW_HE_RU242_4 = 64, 525 /* 40MHz */ 526 RTW_HE_RU484_1 = 65, 527 RTW_HE_RU484_2 = 66, 528 /* 80MHz */ 529 RTW_HE_RU996_1 = 67, 530 /* 160MHz */ 531 RTW_HE_RU2x996_1 = 68, 532 }; 533 534 enum rtw_protect_mode { 535 RTW_PROTECT_DISABLE = 0, 536 RTW_PROTECT_RTS = 1, 537 RTW_PROTECT_CTS2SELF = 2, 538 RTW_PROTECT_HW_RTS = 3 539 }; 540 541 enum rtw_ac { 542 RTW_AC_BE = 0, 543 RTW_AC_BK = 1, 544 RTW_AC_VI = 2, 545 RTW_AC_VO = 3 546 }; 547 548 enum rtw_edcca_mode { 549 RTW_EDCCA_NORMAL, 550 RTW_EDCCA_ETSI, 551 RTW_EDCCA_JP, 552 RTW_EDCCA_MAX 553 }; 554 555 enum rtw_mac_pwr_st { 556 RTW_MAC_PWR_NONE = 0, 557 RTW_MAC_PWR_OFF = 1, 558 RTW_MAC_PWR_ON = 2, 559 RTW_MAC_PWR_LPS = 3, 560 RTW_MAC_PWR_MAX = 0x4 561 }; 562 563 enum rtw_pcie_bus_func_cap_t { 564 RTW_PCIE_BUS_FUNC_DISABLE = 0, 565 RTW_PCIE_BUS_FUNC_ENABLE = 1, 566 RTW_PCIE_BUS_FUNC_DEFAULT = 2, 567 RTW_PCIE_BUS_FUNC_IGNORE = 3 568 }; 569 570 /* follow mac's definetion, mac_ax_sw_io_mode*/ 571 enum rtw_gpio_mode { 572 RTW_AX_SW_IO_MODE_INPUT, 573 RTW_AX_SW_IO_MODE_OUTPUT_OD, 574 RTW_AX_SW_IO_MODE_OUTPUT_PP, 575 RTW_AX_SW_IO_MODE_MAX 576 }; 577 578 /*MAC_AX_PCIE_L0SDLY_IGNORE = 0xFF, MAC_AX_PCIE_L1DLY_IGNORE = 0xFF, MAC_AX_PCIE_CLKDLY_IGNORE = 0xFF */ 579 #define RTW_PCIE_BUS_ASPM_DLY_IGNORE 0xFF /* Fully controlled by HW */ 580 581 #define RTW_FRAME_TYPE_MGNT 0 582 #define RTW_FRAME_TYPE_CTRL 1 583 #define RTW_FRAME_TYPE_DATA 2 584 #define RTW_FRAME_TYPE_EXT_RSVD 3 585 /* Association Related PKT Type + SubType */ 586 587 #define FRAME_OFFSET_FRAME_CONTROL 0 588 #define FRAME_OFFSET_DURATION 2 589 #define FRAME_OFFSET_ADDRESS1 4 590 #define FRAME_OFFSET_ADDRESS2 10 591 #define FRAME_OFFSET_ADDRESS3 16 592 #define FRAME_OFFSET_SEQUENCE 22 593 #define FRAME_OFFSET_ADDRESS4 24 594 #define PHL_GET_80211_HDR_TYPE(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 2, 6) 595 #define PHL_GET_80211_HDR_MORE_FRAG(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 10, 1) 596 #define PHL_GET_80211_HDR_RETRY(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 11, 1) 597 #define PHL_GET_80211_HDR_FRAG_NUM(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr + 22, 0, 4) 598 #define PHL_GET_80211_HDR_SEQUENCE(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr + 22, 4, 12) 599 #define PHL_GET_80211_HDR_ADDRESS2(_d, _hdr, _val) \ 600 _os_mem_cpy(_d, (u8 *)_val, (u8 *)_hdr + FRAME_OFFSET_ADDRESS2, 6) 601 #define PHL_GET_80211_HDR_ADDRESS3(_d, _hdr, _val) \ 602 _os_mem_cpy(_d, (u8 *)_val, (u8 *)_hdr + FRAME_OFFSET_ADDRESS3, 6) 603 604 #define RTW_FRAME_TYPE_BEACON 32 605 #define RTW_FRAME_TYPE_PROBE_RESP 20 606 #define RTW_FRAME_TYPE_ASOC_REQ 0 607 #define RTW_FRAME_TYPE_ASOC_RESP 4 608 #define RTW_FRAME_TYPE_REASOC_REQ 8 609 #define RTW_FRAME_TYPE_REASOC_RESP 12 610 #define RTW_IS_ASOC_PKT(_TYPE) \ 611 ((_TYPE == RTW_FRAME_TYPE_REASOC_RESP) || \ 612 (_TYPE == RTW_FRAME_TYPE_REASOC_REQ) || \ 613 (_TYPE == RTW_FRAME_TYPE_ASOC_RESP) || \ 614 (_TYPE == RTW_FRAME_TYPE_ASOC_REQ)) ? true : false 615 616 #define RTW_IS_ASOC_REQ_PKT(_TYPE) \ 617 ((_TYPE == RTW_FRAME_TYPE_REASOC_REQ) || \ 618 (_TYPE == RTW_FRAME_TYPE_ASOC_REQ)) ? true : false 619 620 #define RTW_IS_BEACON_OR_PROBE_RESP_PKT(_TYPE) \ 621 ((_TYPE == RTW_FRAME_TYPE_BEACON) || \ 622 (_TYPE == RTW_FRAME_TYPE_PROBE_RESP)) ? true : false 623 624 #define TU 1024 /* Time Unit (TU): 1024 us*/ 625 626 #define RTW_MAX_ETH_PKT_LEN 1536 627 628 #endif /*_RTW_GENERAL_DEF_H_*/ 629