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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi19 hysteresis = <1000>; /* millicelsius */
24 hysteresis = <1000>; /* millicelsius */
29 hysteresis = <1000>; /* millicelsius */
34 hysteresis = <1000>; /* millicelsius */
39 hysteresis = <1000>; /* millicelsius */
44 hysteresis = <1000>; /* millicelsius */
49 hysteresis = <1000>; /* millicelsius */
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dclock.c152 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
161 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
283 * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on), in clock_init()
285 * A7 side: SPLL PFD0 (scs selected, 413Mhz), in clock_init()
286 * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks in clock_init()
287 * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz, in clock_init()
288 * IP BUS (NIC1_BUS) = 58.6Mhz in clock_init()
304 /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */ in clock_init()
334 printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000); in do_mx7_showclocks()
337 printf("PLL_A7_APLL %8d MHz\n", freq / 1000000); in do_mx7_showclocks()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dintel_gt_clock_utils.c10 #define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */
11 #define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
12 #define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
49 gt->clock_frequency / 1000); in intel_gt_init_clock_frequency()
71 return div_u64_roundup(mul_u32_u32(count, 1000 * 1000 * 1000), in intel_gt_clock_interval_to_ns()
83 1000 * 1000 * 1000); in intel_gt_ns_to_clock_interval()
/OK3568_Linux_fs/kernel/drivers/clk/mvebu/
H A Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
55 [0x0] = 666 * 1000 * 1000,
56 [0x2] = 800 * 1000 * 1000,
57 [0x3] = 800 * 1000 * 1000,
58 [0x4] = 1066 * 1000 * 1000,
59 [0x5] = 1066 * 1000 * 1000,
60 [0x6] = 1200 * 1000 * 1000,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c697 pll_settings->reference_freq * 1000, in calculate_ss()
1027 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1028 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1029 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
1030 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
1031 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
1032 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
1033 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
1034 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429
1035 {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c67 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
68 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
69 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
70 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
75 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
76 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
77 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
78 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
79 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
98 table[i].frequency = freqs[i].cpufreq_mhz * 1000; in setup_freqs_table()
[all …]
H A Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
92 #define SLEEP_FREQ (800 * 1000)
103 unsigned long refresh; /* DRAM refresh counter * 1000 */
125 {0, L0, 1000*1000},
126 {0, L1, 800*1000},
127 {0, L2, 400*1000},
128 {0, L3, 200*1000},
129 {0, L4, 100*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
[all …]
H A Dpmac32-cpufreq.c369 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_target()
429 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_resume()
503 * frequency, it claims it to be around 84Mhz on some models while in pmac_cpufreq_init_MacRISC3()
504 * it appears to be approx. 101Mhz on all. Let's hack around here... in pmac_cpufreq_init_MacRISC3()
530 low_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
539 hi_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
587 low_freq = (*value) / 1000; in pmac_cpufreq_init_750FX()
606 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
607 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
608 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
[all …]
H A Dimx6q-cpufreq.c67 freq_hz = new_freq * 1000; in imx6q_set_target()
68 old_freq = clk_get_rate(clks[ARM].clk) / 1000; in imx6q_set_target()
81 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", in imx6q_set_target()
82 old_freq / 1000, volt_old / 1000, in imx6q_set_target()
83 new_freq / 1000, volt / 1000); in imx6q_set_target()
122 * CPU may run at higher than 528MHz, this will lead to in imx6q_set_target()
124 * voltage of 528MHz, so lower the CPU frequency to one in imx6q_set_target()
127 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); in imx6q_set_target()
138 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); in imx6q_set_target()
145 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); in imx6q_set_target()
[all …]
H A Delanfreq.c45 {1000, 0x02, 0x18},
56 {0, 0, 1000},
72 * at the moment. Frequencies from 1 to 33 MHz are generated
73 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
74 * and have the rest of the chip running with 33 MHz.
89 /* Are we in CPU clock multiplied mode (66/99 MHz)? */ in elanfreq_get_cpu_frequency()
97 /* 33 MHz is not 32 MHz... */ in elanfreq_get_cpu_frequency()
101 return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000; in elanfreq_get_cpu_frequency()
117 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency) in elanfreq_target()
124 udelay(1000); /* buffers have cleaned up */ in elanfreq_target()
[all …]
H A Ds3c2416-cpufreq.c98 return clk_get_rate(s3c_freq->armclk) / 1000; in s3c2416_cpufreq_get_speed()
106 if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) { in s3c2416_cpufreq_set_armdiv()
107 ret = clk_set_rate(s3c_freq->armdiv, freq * 1000); in s3c2416_cpufreq_set_armdiv()
131 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_enter_dvs()
191 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_leave_dvs()
193 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_leave_dvs()
196 clk_get_rate(s3c_freq->hclk) / 1000, ret); in s3c2416_cpufreq_leave_dvs()
202 clk_get_rate(s3c_freq->armdiv) / 1000); in s3c2416_cpufreq_leave_dvs()
242 ? clk_get_rate(s3c_freq->hclk) / 1000 in s3c2416_cpufreq_set_target()
298 s3c_freq->regulator_latency = 1 * 1000 * 1000; in s3c2416_cpufreq_cfg_regulator()
[all …]
H A Dspeedstep-centrino.c83 frequency/voltage operating point; frequency in MHz, volts in mV.
85 #define OP(mhz, mv) \ argument
87 .frequency = (mhz) * 1000, \
88 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
98 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
107 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
113 OP(1000, 1004),
123 OP(1000, 1164),
135 OP(1000, 1100),
146 OP(1000, 1292),
[all …]
/OK3568_Linux_fs/u-boot/board/samsung/odroid/
H A Dodroid.c119 /* Set APLL to 1000MHz */ in board_clock_init()
142 * Set dividers for MOUTcore = 1000 MHz in board_clock_init()
143 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) in board_clock_init()
144 * corem0 = armclk / (ratio + 1) = 333 MHz (2) in board_clock_init()
145 * corem1 = armclk / (ratio + 1) = 166 MHz (5) in board_clock_init()
146 * periph = armclk / (ratio + 1) = 1000 MHz (0) in board_clock_init()
147 * atbout = MOUT / (ratio + 1) = 200 MHz (4) in board_clock_init()
148 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) in board_clock_init()
149 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) in board_clock_init()
150 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) in board_clock_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi_common.c18 #define MHZ (1000 * 1000) macro
19 #define FIN_HZ (24 * MHZ)
21 #define DFIN_PLL_MIN_HZ (6 * MHZ)
22 #define DFIN_PLL_MAX_HZ (12 * MHZ)
24 #define DFVCO_MIN_HZ (500 * MHZ)
25 #define DFVCO_MAX_HZ (1000 * MHZ)
110 delay_val = MHZ / dsim->dsim_config->esc_clk; in exynos_mipi_dsi_wr_data()
239 sw_timeout = 1000; in exynos_mipi_dsi_pll_on()
268 * ~ 99.99 MHz 0000 in exynos_mipi_dsi_change_pll()
269 * 100 ~ 119.99 MHz 0001 in exynos_mipi_dsi_change_pll()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
44 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk628/
H A Drk628_combrxphy.c300 usleep_range(40*1000, 41*1000); in rk628_combrxphy_sample_edge_procedure_for_cable()
332 usleep_range(40*1000, 41*1000); in rk628_combrxphy_sample_edge_procedure_for_cable()
412 usleep_range(40*1000, 41*1000); in rk628_combrxphy_sample_edge_procedure()
445 usleep_range(40*1000, 41*1000); in rk628_combrxphy_sample_edge_procedure()
528 * 5'd18:rx3p clock = 297MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
529 * 5'd17:rx3p clock = 162MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
530 * 5'd16:rx3p clock = 148.5MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
531 * 5'd15:rx3p clock = 135MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
532 * 5'd14:rx3p clock = 119MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
533 * 5'd13:rx3p clock = 108MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
[all …]
/OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf52x2/
H A Dcpu.c32 udelay(1000); in do_reset()
45 " CPU CLK %s MHz BUS CLK %s MHz\n", in checkcpu()
84 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); in watchdog_init()
127 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", in checkcpu()
131 " (PIN: 0x%x) rev. %hu, at %s MHz\n", in checkcpu()
177 udelay(1000); in do_reset()
246 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); in watchdog_init()
263 udelay(1000); in do_reset()
275 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", in checkcpu()
315 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); in watchdog_init()
[all …]
/OK3568_Linux_fs/kernel/tools/power/cpupower/utils/
H A Dcpufreq-info.c95 else if (speed > 1000) in print_speed()
96 printf("%u.%03u MHz", ((unsigned int) speed/1000), in print_speed()
97 (unsigned int) (speed%1000)); in print_speed()
108 tmp = speed%1000; in print_speed()
110 speed += 1000; in print_speed()
111 printf("%u MHz", ((unsigned int) speed/1000)); in print_speed()
112 } else if (speed > 1000) { in print_speed()
116 printf("%u.%01u MHz", ((unsigned int) speed/1000), in print_speed()
117 ((unsigned int) (speed%1000)/100)); in print_speed()
133 printf("%u us", ((unsigned int) duration/1000)); in print_duration()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dcpu.h77 #define KHZ (1000)
80 #ifndef MHZ
81 #define MHZ (1000*1000) macro
84 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/OK3568_Linux_fs/kernel/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
402 Specify clos min in MHz with [--min|-n]
403 Specify clos max in MHz with [--max|-m]
412 clos min is not specified, default: 0 MHz
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/calcs/
H A Ddcn_calcs.c75 .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */
76 .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */
77 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
78 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
81 .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */
82 .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */
83 .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */
84 .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */
87 .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */
88 .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/intel_pstate/
H A Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
60 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
80 # MAIN (ALL UNITS IN MHZ)
90 min_freq=$(($_min_freq / 1000))
92 max_freq=$(($_max_freq / 1000))
98 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]

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