1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * elanfreq: cpufreq driver for the AMD ELAN family
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (c) Copyright 2002 Robert Schwebel <r.schwebel@pengutronix.de>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Parts of this code are (c) Sven Geggus <sven@geggus.net>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * All Rights Reserved.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * 2002-02-13: - initial revision for 2.4.18-pre9 by Robert Schwebel
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <linux/cpufreq.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <asm/cpu_device_id.h>
24*4882a593Smuzhiyun #include <asm/msr.h>
25*4882a593Smuzhiyun #include <linux/timex.h>
26*4882a593Smuzhiyun #include <linux/io.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */
29*4882a593Smuzhiyun #define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Module parameter */
32*4882a593Smuzhiyun static int max_freq;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct s_elan_multiplier {
35*4882a593Smuzhiyun int clock; /* frequency in kHz */
36*4882a593Smuzhiyun int val40h; /* PMU Force Mode register */
37*4882a593Smuzhiyun int val80h; /* CPU Clock Speed Register */
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun * It is important that the frequencies
42*4882a593Smuzhiyun * are listed in ascending order here!
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun static struct s_elan_multiplier elan_multiplier[] = {
45*4882a593Smuzhiyun {1000, 0x02, 0x18},
46*4882a593Smuzhiyun {2000, 0x02, 0x10},
47*4882a593Smuzhiyun {4000, 0x02, 0x08},
48*4882a593Smuzhiyun {8000, 0x00, 0x00},
49*4882a593Smuzhiyun {16000, 0x00, 0x02},
50*4882a593Smuzhiyun {33000, 0x00, 0x04},
51*4882a593Smuzhiyun {66000, 0x01, 0x04},
52*4882a593Smuzhiyun {99000, 0x01, 0x05}
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static struct cpufreq_frequency_table elanfreq_table[] = {
56*4882a593Smuzhiyun {0, 0, 1000},
57*4882a593Smuzhiyun {0, 1, 2000},
58*4882a593Smuzhiyun {0, 2, 4000},
59*4882a593Smuzhiyun {0, 3, 8000},
60*4882a593Smuzhiyun {0, 4, 16000},
61*4882a593Smuzhiyun {0, 5, 33000},
62*4882a593Smuzhiyun {0, 6, 66000},
63*4882a593Smuzhiyun {0, 7, 99000},
64*4882a593Smuzhiyun {0, 0, CPUFREQ_TABLE_END},
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /**
69*4882a593Smuzhiyun * elanfreq_get_cpu_frequency: determine current cpu speed
70*4882a593Smuzhiyun *
71*4882a593Smuzhiyun * Finds out at which frequency the CPU of the Elan SOC runs
72*4882a593Smuzhiyun * at the moment. Frequencies from 1 to 33 MHz are generated
73*4882a593Smuzhiyun * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
74*4882a593Smuzhiyun * and have the rest of the chip running with 33 MHz.
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun
elanfreq_get_cpu_frequency(unsigned int cpu)77*4882a593Smuzhiyun static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun u8 clockspeed_reg; /* Clock Speed Register */
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun local_irq_disable();
82*4882a593Smuzhiyun outb_p(0x80, REG_CSCIR);
83*4882a593Smuzhiyun clockspeed_reg = inb_p(REG_CSCDR);
84*4882a593Smuzhiyun local_irq_enable();
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if ((clockspeed_reg & 0xE0) == 0xE0)
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Are we in CPU clock multiplied mode (66/99 MHz)? */
90*4882a593Smuzhiyun if ((clockspeed_reg & 0xE0) == 0xC0) {
91*4882a593Smuzhiyun if ((clockspeed_reg & 0x01) == 0)
92*4882a593Smuzhiyun return 66000;
93*4882a593Smuzhiyun else
94*4882a593Smuzhiyun return 99000;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* 33 MHz is not 32 MHz... */
98*4882a593Smuzhiyun if ((clockspeed_reg & 0xE0) == 0xA0)
99*4882a593Smuzhiyun return 33000;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun
elanfreq_target(struct cpufreq_policy * policy,unsigned int state)105*4882a593Smuzhiyun static int elanfreq_target(struct cpufreq_policy *policy,
106*4882a593Smuzhiyun unsigned int state)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun * Access to the Elan's internal registers is indexed via
110*4882a593Smuzhiyun * 0x22: Chip Setup & Control Register Index Register (CSCI)
111*4882a593Smuzhiyun * 0x23: Chip Setup & Control Register Data Register (CSCD)
112*4882a593Smuzhiyun *
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * 0x40 is the Power Management Unit's Force Mode Register.
117*4882a593Smuzhiyun * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency)
118*4882a593Smuzhiyun */
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun local_irq_disable();
121*4882a593Smuzhiyun outb_p(0x40, REG_CSCIR); /* Disable hyperspeed mode */
122*4882a593Smuzhiyun outb_p(0x00, REG_CSCDR);
123*4882a593Smuzhiyun local_irq_enable(); /* wait till internal pipelines and */
124*4882a593Smuzhiyun udelay(1000); /* buffers have cleaned up */
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun local_irq_disable();
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* now, set the CPU clock speed register (0x80) */
129*4882a593Smuzhiyun outb_p(0x80, REG_CSCIR);
130*4882a593Smuzhiyun outb_p(elan_multiplier[state].val80h, REG_CSCDR);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* now, the hyperspeed bit in PMU Force Mode Register (0x40) */
133*4882a593Smuzhiyun outb_p(0x40, REG_CSCIR);
134*4882a593Smuzhiyun outb_p(elan_multiplier[state].val40h, REG_CSCDR);
135*4882a593Smuzhiyun udelay(10000);
136*4882a593Smuzhiyun local_irq_enable();
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return 0;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun /*
141*4882a593Smuzhiyun * Module init and exit code
142*4882a593Smuzhiyun */
143*4882a593Smuzhiyun
elanfreq_cpu_init(struct cpufreq_policy * policy)144*4882a593Smuzhiyun static int elanfreq_cpu_init(struct cpufreq_policy *policy)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun struct cpuinfo_x86 *c = &cpu_data(0);
147*4882a593Smuzhiyun struct cpufreq_frequency_table *pos;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* capability check */
150*4882a593Smuzhiyun if ((c->x86_vendor != X86_VENDOR_AMD) ||
151*4882a593Smuzhiyun (c->x86 != 4) || (c->x86_model != 10))
152*4882a593Smuzhiyun return -ENODEV;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /* max freq */
155*4882a593Smuzhiyun if (!max_freq)
156*4882a593Smuzhiyun max_freq = elanfreq_get_cpu_frequency(0);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* table init */
159*4882a593Smuzhiyun cpufreq_for_each_entry(pos, elanfreq_table)
160*4882a593Smuzhiyun if (pos->frequency > max_freq)
161*4882a593Smuzhiyun pos->frequency = CPUFREQ_ENTRY_INVALID;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun policy->freq_table = elanfreq_table;
164*4882a593Smuzhiyun return 0;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun #ifndef MODULE
169*4882a593Smuzhiyun /**
170*4882a593Smuzhiyun * elanfreq_setup - elanfreq command line parameter parsing
171*4882a593Smuzhiyun *
172*4882a593Smuzhiyun * elanfreq command line parameter. Use:
173*4882a593Smuzhiyun * elanfreq=66000
174*4882a593Smuzhiyun * to set the maximum CPU frequency to 66 MHz. Note that in
175*4882a593Smuzhiyun * case you do not give this boot parameter, the maximum
176*4882a593Smuzhiyun * frequency will fall back to _current_ CPU frequency which
177*4882a593Smuzhiyun * might be lower. If you build this as a module, use the
178*4882a593Smuzhiyun * max_freq module parameter instead.
179*4882a593Smuzhiyun */
elanfreq_setup(char * str)180*4882a593Smuzhiyun static int __init elanfreq_setup(char *str)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun max_freq = simple_strtoul(str, &str, 0);
183*4882a593Smuzhiyun pr_warn("You're using the deprecated elanfreq command line option. Use elanfreq.max_freq instead, please!\n");
184*4882a593Smuzhiyun return 1;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun __setup("elanfreq=", elanfreq_setup);
187*4882a593Smuzhiyun #endif
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun static struct cpufreq_driver elanfreq_driver = {
191*4882a593Smuzhiyun .get = elanfreq_get_cpu_frequency,
192*4882a593Smuzhiyun .flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
193*4882a593Smuzhiyun .verify = cpufreq_generic_frequency_table_verify,
194*4882a593Smuzhiyun .target_index = elanfreq_target,
195*4882a593Smuzhiyun .init = elanfreq_cpu_init,
196*4882a593Smuzhiyun .name = "elanfreq",
197*4882a593Smuzhiyun .attr = cpufreq_generic_attr,
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static const struct x86_cpu_id elan_id[] = {
201*4882a593Smuzhiyun X86_MATCH_VENDOR_FAM_MODEL(AMD, 4, 10, NULL),
202*4882a593Smuzhiyun {}
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun MODULE_DEVICE_TABLE(x86cpu, elan_id);
205*4882a593Smuzhiyun
elanfreq_init(void)206*4882a593Smuzhiyun static int __init elanfreq_init(void)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun if (!x86_match_cpu(elan_id))
209*4882a593Smuzhiyun return -ENODEV;
210*4882a593Smuzhiyun return cpufreq_register_driver(&elanfreq_driver);
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun
elanfreq_exit(void)214*4882a593Smuzhiyun static void __exit elanfreq_exit(void)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun cpufreq_unregister_driver(&elanfreq_driver);
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun module_param(max_freq, int, 0444);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun MODULE_LICENSE("GPL");
223*4882a593Smuzhiyun MODULE_AUTHOR("Robert Schwebel <r.schwebel@pengutronix.de>, "
224*4882a593Smuzhiyun "Sven Geggus <sven@geggus.net>");
225*4882a593Smuzhiyun MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun module_init(elanfreq_init);
228*4882a593Smuzhiyun module_exit(elanfreq_exit);
229