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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dxenvm-4.2.dts26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
51 reg = <0 0x80000000 0 0x08000000>;
57 #address-cells = <0>;
59 reg = <0 0x2c001000 0 0x1000>,
60 <0 0x2c002000 0 0x100>;
65 interrupts = <1 13 0xf08>,
66 <1 14 0xf08>,
67 <1 11 0xf08>,
[all …]
H A Decx-2000.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
54 memory@0 {
57 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
63 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
67 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
70 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
71 <1 14 0xf08>,
[all …]
H A Dvexpress-v2p-ca15-tc1.dts16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
53 reg = <0 0x80000000 0 0x40000000>;
61 /* Chipselect 2 is physically at 0x18000000 */
65 reg = <0 0x18000000 0 0x00800000>;
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
[all …]
H A Dqcom-apq8084.dtsi21 reg = <0xfa00000 0x200000>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
93 reg = <0x0 0x0>;
188 interrupts = <GIC_PPI 7 0xf04>;
194 #clock-cells = <0>;
200 #clock-cells = <0>;
207 interrupts = <GIC_PPI 2 0xf08>,
208 <GIC_PPI 3 0xf08>,
[all …]
H A Dqcom-ipq4019.dtsi21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
45 #size-cells = <0>;
46 cpu@0 {
53 reg = <0x0>;
55 clock-frequency = <0>;
67 reg = <0x1>;
69 clock-frequency = <0>;
[all …]
H A Dvexpress-v2p-ca15_a7.dts16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
[all …]
H A Dhip04.dtsi22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
27 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0>;
110 reg = <0x100>;
115 reg = <0x101>;
120 reg = <0x102>;
125 reg = <0x103>;
130 reg = <0x200>;
135 reg = <0x201>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer.yaml104 interrupts = <1 13 0xf08>,
105 <1 14 0xf08>,
106 <1 11 0xf08>,
107 <1 10 0xf08>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x2000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a.dtsi35 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0>;
47 clocks = <&clockgen 1 0>;
56 reg = <0x1>;
57 clocks = <&clockgen 1 0>;
66 reg = <0x2>;
67 clocks = <&clockgen 1 0>;
76 reg = <0x3>;
77 clocks = <&clockgen 1 0>;
[all …]
/OK3568_Linux_fs/kernel/include/linux/amba/
H A Dsp810.h18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-highbank/
H A Dsysregs.h16 #define HB_SREG_A9_PWR_REQ 0xf00
17 #define HB_SREG_A9_BOOT_STAT 0xf04
18 #define HB_SREG_A9_BOOT_DATA 0xf08
20 #define HB_PWR_SUSPEND 0
25 #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
29 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_set_core_pwr()
38 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_clear_core_pwr()
42 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); in highbank_clear_core_pwr()
71 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_clear_pwr_request()
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
32 reg = <0x0>;
40 reg = <0x1>;
49 reg = <0x2>;
58 reg = <0x3>;
66 CPU_SLEEP_0: cpu-sleep-0 {
68 arm,psci-suspend-param = <0x40000000>;
110 interrupts = <0 143 4>,
111 <0 144 4>,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/
H A Dphydm_regdefine11ac.h25 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
26 #define ODM_REG_BB_RX_PATH_11AC 0x808
27 #define ODM_REG_BB_TX_PATH_11AC 0x80c
28 #define ODM_REG_BB_ATC_11AC 0x860
29 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
30 #define ODM_REG_DBG_RPT_11AC 0x8fc
32 #define ODM_REG_EDCCA_DOWN_OPT 0x900
33 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
34 #define odm_adc_trigger_jaguar2 0x95C /*ADC sample mode*/
35 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/phydm/
H A Dphydm_regdefine11ac.h30 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
31 #define ODM_REG_BB_RX_PATH_11AC 0x808
32 #define ODM_REG_BB_TX_PATH_11AC 0x80c
33 #define ODM_REG_BB_ATC_11AC 0x860
34 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
35 #define ODM_REG_DBG_RPT_11AC 0x8fc
37 #define ODM_REG_EDCCA_DOWN_OPT 0x900
38 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
39 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
40 #define ODM_REG_NHM_TIMER_11AC 0x990
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/hal/phydm/
H A Dphydm_regdefine11ac.h30 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
31 #define ODM_REG_BB_RX_PATH_11AC 0x808
32 #define ODM_REG_BB_TX_PATH_11AC 0x80c
33 #define ODM_REG_BB_ATC_11AC 0x860
34 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
35 #define ODM_REG_DBG_RPT_11AC 0x8fc
37 #define ODM_REG_EDCCA_DOWN_OPT 0x900
38 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
39 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
40 #define ODM_REG_NHM_TIMER_11AC 0x990
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/phydm/
H A Dphydm_regdefine11ac.h30 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
31 #define ODM_REG_BB_RX_PATH_11AC 0x808
32 #define ODM_REG_BB_TX_PATH_11AC 0x80c
33 #define ODM_REG_BB_ATC_11AC 0x860
34 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
35 #define ODM_REG_DBG_RPT_11AC 0x8fc
37 #define ODM_REG_EDCCA_DOWN_OPT 0x900
38 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
39 #define ODM_ADC_TRIGGER_Jaguar2 0x95C /*ADC sample mode*/
40 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/
H A Dphydm_regdefine11ac.h35 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
36 #define ODM_REG_BB_RX_PATH_11AC 0x808
37 #define ODM_REG_BB_TX_PATH_11AC 0x80c
38 #define ODM_REG_BB_ATC_11AC 0x860
39 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
40 #define ODM_REG_DBG_RPT_11AC 0x8fc
42 #define ODM_REG_EDCCA_DOWN_OPT 0x900
43 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
44 #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
45 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/
H A Dphydm_regdefine11ac.h35 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
36 #define ODM_REG_BB_RX_PATH_11AC 0x808
37 #define ODM_REG_BB_TX_PATH_11AC 0x80c
38 #define ODM_REG_BB_ATC_11AC 0x860
39 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
40 #define ODM_REG_DBG_RPT_11AC 0x8fc
42 #define ODM_REG_EDCCA_DOWN_OPT 0x900
43 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
44 #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
45 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/hal/phydm/
H A Dphydm_regdefine11ac.h35 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
36 #define ODM_REG_BB_RX_PATH_11AC 0x808
37 #define ODM_REG_BB_TX_PATH_11AC 0x80c
38 #define ODM_REG_BB_ATC_11AC 0x860
39 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
40 #define ODM_REG_DBG_RPT_11AC 0x8fc
42 #define ODM_REG_EDCCA_DOWN_OPT 0x900
43 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
44 #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
45 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/hal/phydm/
H A Dphydm_regdefine11ac.h35 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
36 #define ODM_REG_BB_RX_PATH_11AC 0x808
37 #define ODM_REG_BB_TX_PATH_11AC 0x80c
38 #define ODM_REG_BB_ATC_11AC 0x860
39 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
40 #define ODM_REG_DBG_RPT_11AC 0x8fc
42 #define ODM_REG_EDCCA_DOWN_OPT 0x900
43 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
44 #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
45 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/hal/phydm/
H A Dphydm_regdefine11ac.h35 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
36 #define ODM_REG_BB_RX_PATH_11AC 0x808
37 #define ODM_REG_BB_TX_PATH_11AC 0x80c
38 #define ODM_REG_BB_ATC_11AC 0x860
39 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
40 #define ODM_REG_DBG_RPT_11AC 0x8fc
42 #define ODM_REG_EDCCA_DOWN_OPT 0x900
43 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
44 #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
45 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/hal/phydm/
H A Dphydm_regdefine11ac.h35 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
36 #define ODM_REG_BB_RX_PATH_11AC 0x808
37 #define ODM_REG_BB_TX_PATH_11AC 0x80c
38 #define ODM_REG_BB_ATC_11AC 0x860
39 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
40 #define ODM_REG_DBG_RPT_11AC 0x8fc
42 #define ODM_REG_EDCCA_DOWN_OPT 0x900
43 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
44 #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
45 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/hal/phydm/
H A Dphydm_regdefine11ac.h35 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
36 #define ODM_REG_BB_RX_PATH_11AC 0x808
37 #define ODM_REG_BB_TX_PATH_11AC 0x80c
38 #define ODM_REG_BB_ATC_11AC 0x860
39 #define ODM_REG_EDCCA_POWER_CAL 0x8dc
40 #define ODM_REG_DBG_RPT_11AC 0x8fc
42 #define ODM_REG_EDCCA_DOWN_OPT 0x900
43 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
44 #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
45 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
[all …]

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