1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Xen Virtual Machine for unprivileged guests 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) 6*4882a593Smuzhiyun * Cortex-A15 MPCore (V2P-CA15) 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/dts-v1/; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "XENVM-4.2"; 14*4882a593Smuzhiyun compatible = "xen,xenvm-4.2", "xen,xenvm"; 15*4882a593Smuzhiyun interrupt-parent = <&gic>; 16*4882a593Smuzhiyun #address-cells = <2>; 17*4882a593Smuzhiyun #size-cells = <2>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun chosen { 20*4882a593Smuzhiyun /* this field is going to be adjusted by the hypervisor */ 21*4882a593Smuzhiyun bootargs = "console=hvc0 root=/dev/xvda"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun cpus { 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun cpu@0 { 29*4882a593Smuzhiyun device_type = "cpu"; 30*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 31*4882a593Smuzhiyun reg = <0>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun cpu@1 { 35*4882a593Smuzhiyun device_type = "cpu"; 36*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 37*4882a593Smuzhiyun reg = <1>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun psci { 42*4882a593Smuzhiyun compatible = "arm,psci"; 43*4882a593Smuzhiyun method = "hvc"; 44*4882a593Smuzhiyun cpu_off = <1>; 45*4882a593Smuzhiyun cpu_on = <2>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun memory@80000000 { 49*4882a593Smuzhiyun device_type = "memory"; 50*4882a593Smuzhiyun /* this field is going to be adjusted by the hypervisor */ 51*4882a593Smuzhiyun reg = <0 0x80000000 0 0x08000000>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun gic: interrupt-controller@2c001000 { 55*4882a593Smuzhiyun compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 56*4882a593Smuzhiyun #interrupt-cells = <3>; 57*4882a593Smuzhiyun #address-cells = <0>; 58*4882a593Smuzhiyun interrupt-controller; 59*4882a593Smuzhiyun reg = <0 0x2c001000 0 0x1000>, 60*4882a593Smuzhiyun <0 0x2c002000 0 0x100>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun timer { 64*4882a593Smuzhiyun compatible = "arm,armv7-timer"; 65*4882a593Smuzhiyun interrupts = <1 13 0xf08>, 66*4882a593Smuzhiyun <1 14 0xf08>, 67*4882a593Smuzhiyun <1 11 0xf08>, 68*4882a593Smuzhiyun <1 10 0xf08>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun hypervisor { 72*4882a593Smuzhiyun compatible = "xen,xen-4.2", "xen,xen"; 73*4882a593Smuzhiyun /* this field is going to be adjusted by the hypervisor */ 74*4882a593Smuzhiyun reg = <0 0xb0000000 0 0x20000>; 75*4882a593Smuzhiyun /* this field is going to be adjusted by the hypervisor */ 76*4882a593Smuzhiyun interrupts = <1 15 0xf08>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun motherboard { 80*4882a593Smuzhiyun arm,v2m-memory-map = "rs1"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83