1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * The full GNU General Public License is included in this distribution in the 15*4882a593Smuzhiyun * file called LICENSE. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * Contact Information: 18*4882a593Smuzhiyun * wlanfae <wlanfae@realtek.com> 19*4882a593Smuzhiyun * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20*4882a593Smuzhiyun * Hsinchu 300, Taiwan. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Larry Finger <Larry.Finger@lwfinger.net> 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun *****************************************************************************/ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifndef __ODM_REGDEFINE11AC_H__ 27*4882a593Smuzhiyun #define __ODM_REGDEFINE11AC_H__ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* @2 RF REG LIST */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* @2 BB REG LIST */ 34*4882a593Smuzhiyun /* PAGE 8 */ 35*4882a593Smuzhiyun #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 36*4882a593Smuzhiyun #define ODM_REG_BB_RX_PATH_11AC 0x808 37*4882a593Smuzhiyun #define ODM_REG_BB_TX_PATH_11AC 0x80c 38*4882a593Smuzhiyun #define ODM_REG_BB_ATC_11AC 0x860 39*4882a593Smuzhiyun #define ODM_REG_EDCCA_POWER_CAL 0x8dc 40*4882a593Smuzhiyun #define ODM_REG_DBG_RPT_11AC 0x8fc 41*4882a593Smuzhiyun /* PAGE 9 */ 42*4882a593Smuzhiyun #define ODM_REG_EDCCA_DOWN_OPT 0x900 43*4882a593Smuzhiyun #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 44*4882a593Smuzhiyun #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/ 45*4882a593Smuzhiyun #define ODM_REG_OFDM_FA_RST_11AC 0x9A4 46*4882a593Smuzhiyun #define ODM_REG_CCX_PERIOD_11AC 0x990 47*4882a593Smuzhiyun #define ODM_REG_NHM_TH9_TH10_11AC 0x994 48*4882a593Smuzhiyun #define ODM_REG_CLM_11AC 0x994 49*4882a593Smuzhiyun #define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 50*4882a593Smuzhiyun #define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c 51*4882a593Smuzhiyun #define ODM_REG_NHM_TH8_11AC 0x9a0 52*4882a593Smuzhiyun #define ODM_REG_NHM_9E8_11AC 0x9e8 53*4882a593Smuzhiyun #define ODM_REG_CSI_CONTENT_VALUE 0x9b4 54*4882a593Smuzhiyun /* PAGE A */ 55*4882a593Smuzhiyun #define ODM_REG_CCK_CCA_11AC 0xA0A 56*4882a593Smuzhiyun #define ODM_REG_CCK_FA_RST_11AC 0xA2C 57*4882a593Smuzhiyun #define ODM_REG_CCK_FA_11AC 0xA5C 58*4882a593Smuzhiyun /* PAGE B */ 59*4882a593Smuzhiyun #define ODM_REG_RST_RPT_11AC 0xB58 60*4882a593Smuzhiyun /* PAGE C */ 61*4882a593Smuzhiyun #define ODM_REG_TRMUX_11AC 0xC08 62*4882a593Smuzhiyun #define ODM_REG_IGI_A_11AC 0xC50 63*4882a593Smuzhiyun /* PAGE E */ 64*4882a593Smuzhiyun #define ODM_REG_IGI_B_11AC 0xE50 65*4882a593Smuzhiyun #define ODM_REG_ANT_11AC_B 0xE08 66*4882a593Smuzhiyun /* PAGE F */ 67*4882a593Smuzhiyun #define ODM_REG_CCK_CRC32_CNT_11AC 0xF04 68*4882a593Smuzhiyun #define ODM_REG_CCK_CCA_CNT_11AC 0xF08 69*4882a593Smuzhiyun #define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c 70*4882a593Smuzhiyun #define ODM_REG_HT_CRC32_CNT_11AC 0xF10 71*4882a593Smuzhiyun #define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 72*4882a593Smuzhiyun #define ODM_REG_OFDM_FA_11AC 0xF48 73*4882a593Smuzhiyun #define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC 74*4882a593Smuzhiyun #define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 75*4882a593Smuzhiyun #define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC 76*4882a593Smuzhiyun #define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0 77*4882a593Smuzhiyun #define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4 78*4882a593Smuzhiyun #define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8 79*4882a593Smuzhiyun #define ODM_REG_RPT_11AC 0xfa0 80*4882a593Smuzhiyun #define ODM_REG_CLM_RESULT_11AC 0xfa4 81*4882a593Smuzhiyun #define ODM_REG_NHM_CNT_11AC 0xfa8 82*4882a593Smuzhiyun #define ODM_REG_NHM_DUR_READY_11AC 0xfb4 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac 85*4882a593Smuzhiyun #define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 86*4882a593Smuzhiyun /* PAGE 18 */ 87*4882a593Smuzhiyun #define ODM_REG_IGI_C_11AC 0x1850 88*4882a593Smuzhiyun /* PAGE 1A */ 89*4882a593Smuzhiyun #define ODM_REG_IGI_D_11AC 0x1A50 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* PAGE 1D */ 92*4882a593Smuzhiyun #define ODM_REG_IGI_11AC3 0x1D70 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* @2 MAC REG LIST */ 95*4882a593Smuzhiyun #define ODM_REG_RESP_TX_11AC 0x6D8 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* @DIG Related */ 100*4882a593Smuzhiyun #define ODM_BIT_IGI_11AC 0x0000007F 101*4882a593Smuzhiyun #define ODM_BIT_IGI_B_11AC3 0x00007F00 102*4882a593Smuzhiyun #define ODM_BIT_IGI_C_11AC3 0x007F0000 103*4882a593Smuzhiyun #define ODM_BIT_IGI_D_11AC3 0x7F000000 104*4882a593Smuzhiyun #define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16) 105*4882a593Smuzhiyun #define ODM_BIT_BB_RX_PATH_11AC 0xF 106*4882a593Smuzhiyun #define ODM_BIT_BB_TX_PATH_11AC 0xF 107*4882a593Smuzhiyun #define ODM_BIT_BB_ATC_11AC BIT(14) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #endif 110