1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2011 Calxeda, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #ifndef _MACH_HIGHBANK__SYSREGS_H_
6*4882a593Smuzhiyun #define _MACH_HIGHBANK__SYSREGS_H_
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/smp.h>
10*4882a593Smuzhiyun #include <asm/smp_plat.h>
11*4882a593Smuzhiyun #include <asm/smp_scu.h>
12*4882a593Smuzhiyun #include "core.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun extern void __iomem *sregs_base;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define HB_SREG_A9_PWR_REQ 0xf00
17*4882a593Smuzhiyun #define HB_SREG_A9_BOOT_STAT 0xf04
18*4882a593Smuzhiyun #define HB_SREG_A9_BOOT_DATA 0xf08
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define HB_PWR_SUSPEND 0
21*4882a593Smuzhiyun #define HB_PWR_SOFT_RESET 1
22*4882a593Smuzhiyun #define HB_PWR_HARD_RESET 2
23*4882a593Smuzhiyun #define HB_PWR_SHUTDOWN 3
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
26*4882a593Smuzhiyun
highbank_set_core_pwr(void)27*4882a593Smuzhiyun static inline void highbank_set_core_pwr(void)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
30*4882a593Smuzhiyun if (scu_base_addr)
31*4882a593Smuzhiyun scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
32*4882a593Smuzhiyun else
33*4882a593Smuzhiyun writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
highbank_clear_core_pwr(void)36*4882a593Smuzhiyun static inline void highbank_clear_core_pwr(void)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
39*4882a593Smuzhiyun if (scu_base_addr)
40*4882a593Smuzhiyun scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
41*4882a593Smuzhiyun else
42*4882a593Smuzhiyun writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
highbank_set_pwr_suspend(void)45*4882a593Smuzhiyun static inline void highbank_set_pwr_suspend(void)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
48*4882a593Smuzhiyun highbank_set_core_pwr();
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
highbank_set_pwr_shutdown(void)51*4882a593Smuzhiyun static inline void highbank_set_pwr_shutdown(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
54*4882a593Smuzhiyun highbank_set_core_pwr();
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
highbank_set_pwr_soft_reset(void)57*4882a593Smuzhiyun static inline void highbank_set_pwr_soft_reset(void)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
60*4882a593Smuzhiyun highbank_set_core_pwr();
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
highbank_set_pwr_hard_reset(void)63*4882a593Smuzhiyun static inline void highbank_set_pwr_hard_reset(void)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
66*4882a593Smuzhiyun highbank_set_core_pwr();
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
highbank_clear_pwr_request(void)69*4882a593Smuzhiyun static inline void highbank_clear_pwr_request(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
72*4882a593Smuzhiyun highbank_clear_core_pwr();
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #endif
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