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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt86 reg = <0xa 0xf00>;
93 reg = <0xb 0xf00>;
101 reg = <0xc 0xf00>;
108 dev@0 {
109 reg = <0x0 0xf00>;
117 reg = <0x1 0xf00>;
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
127 reg = <0x2 0xf00>;
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
/OK3568_Linux_fs/kernel/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2701.c39 /* 0E4E8SR 4/8/12/16 */
41 /* 0E2E4SR 2/4/6/8 */
44 MTK_DRV_GRP(2, 16, 0, 2, 2)
48 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
54 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
/OK3568_Linux_fs/kernel/drivers/regulator/
H A Dmt6358-regulator.c16 #define MT6358_BUCK_MODE_AUTO 0
57 .enable_mask = BIT(0), \
61 .qi = BIT(0), \
112 .enable_mask = BIT(0), \
118 .qi = BIT(0), \
141 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
145 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
149 REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
153 REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
204 0, 12,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/moxa/
H A Dmoxart_ether.h18 #define TX_REG_OFFSET_DESC0 0
23 #define RX_REG_OFFSET_DESC0 0
28 #define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
29 #define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
30 #define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
31 #define TX_DESC1_BUF_SIZE_MASK 0x7ff
32 #define TX_DESC1_LTS 0x8000000 /* last TX packet */
33 #define TX_DESC1_FTS 0x10000000 /* first TX packet */
34 #define TX_DESC1_FIFO_COMPLETE 0x20000000
35 #define TX_DESC1_INTR_COMPLETE 0x40000000
[all …]
/OK3568_Linux_fs/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S24 mov r5, #0
29 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
30 orr r0, r0, #0x0
35 ldr r1, =0x9
39 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
40 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
41 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
44 mvn r3, #0x0
45 str r3, [r0, #0x14] @INTENCLEAR
46 str r3, [r1, #0x14] @INTENCLEAR
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/ddbridge/
H A Dddbridge-hw.c25 .base = 0x200,
26 .num = 0x08,
27 .size = 0x10,
31 .base = 0x280,
32 .num = 0x08,
33 .size = 0x10,
37 .base = 0x300,
38 .num = 0x08,
39 .size = 0x10,
43 .base = 0x2000,
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_sec_mon.h31 u8 reserved0[0x04];
32 u32 hp_com; /* 0x04 SEC_MON_HP Command Register */
33 u8 reserved2[0x0c];
34 u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
37 #define HPCOMR_SW_SV 0x100 /* Security Violation bit */
38 #define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
39 #define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
40 #define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
41 #define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
42 #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mm/
H A Dtlb-v4wbi.S34 mov r3, #0
35 mcr p15, 0, r3, c7, c10, 4 @ drain WB
37 bic r0, r0, #0x0ff
38 bic r0, r0, #0xf00
40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
48 mov r3, #0
49 mcr p15, 0, r3, c7, c10, 4 @ drain WB
50 bic r0, r0, #0x0ff
51 bic r0, r0, #0xf00
[all …]
H A Dtlb-fa.S39 mov r3, #0
40 mcr p15, 0, r3, c7, c10, 4 @ drain WB
41 bic r0, r0, #0x0ff
42 bic r0, r0, #0xf00
43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
47 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
52 mov r3, #0
53 mcr p15, 0, r3, c7, c10, 4 @ drain WB
54 bic r0, r0, #0x0ff
55 bic r0, r0, #0xf00
[all …]
H A Dtlb-v4wb.S36 mcr p15, 0, r3, c7, c10, 4 @ drain WB
38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
39 bic r0, r0, #0x0ff
40 bic r0, r0, #0xf00
41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
57 mov r3, #0
58 mcr p15, 0, r3, c7, c10, 4 @ drain WB
59 bic r0, r0, #0x0ff
60 bic r0, r0, #0xf00
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/
H A Daidmp.h35 #define MFGID_ARM 0x43b
36 #define MFGID_BRCM 0x4bf
37 #define MFGID_MIPS 0x4a7
40 #define CC_SIM 0
43 #define CC_VERIF 0xb
44 #define CC_OPTIMO 0xd
45 #define CC_GEN 0xe
46 #define CC_PRIMECELL 0xf
49 #define ER_EROMENTRY 0x000
50 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/
H A Dchosen.txt21 reg = <0xf00 0x10>;
41 reg = <0xf00 0x10>;
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/
H A Daidmp.h28 #define MFGID_ARM 0x43b
29 #define MFGID_BRCM 0x4bf
30 #define MFGID_MIPS 0x4a7
33 #define CC_SIM 0
36 #define CC_VERIF 0xb
37 #define CC_OPTIMO 0xd
38 #define CC_GEN 0xe
39 #define CC_PRIMECELL 0xf
42 #define ER_EROMENTRY 0x000
43 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/
H A Daidmp.h28 #define MFGID_ARM 0x43b
29 #define MFGID_BRCM 0x4bf
30 #define MFGID_MIPS 0x4a7
33 #define CC_SIM 0
36 #define CC_VERIF 0xb
37 #define CC_OPTIMO 0xd
38 #define CC_GEN 0xe
39 #define CC_PRIMECELL 0xf
42 #define ER_EROMENTRY 0x000
43 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/
H A Daidmp.h36 #define MFGID_ARM 0x43b
37 #define MFGID_BRCM 0x4bf
38 #define MFGID_MIPS 0x4a7
41 #define CC_SIM 0
44 #define CC_VERIF 0xb
45 #define CC_OPTIMO 0xd
46 #define CC_GEN 0xe
47 #define CC_PRIMECELL 0xf
50 #define ER_EROMENTRY 0x000
51 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/
H A Daidmp.h36 #define MFGID_ARM 0x43b
37 #define MFGID_BRCM 0x4bf
38 #define MFGID_MIPS 0x4a7
41 #define CC_SIM 0
44 #define CC_VERIF 0xb
45 #define CC_OPTIMO 0xd
46 #define CC_GEN 0xe
47 #define CC_PRIMECELL 0xf
50 #define ER_EROMENTRY 0x000
51 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/
H A Daidmp.h36 #define MFGID_ARM 0x43b
37 #define MFGID_BRCM 0x4bf
38 #define MFGID_MIPS 0x4a7
41 #define CC_SIM 0
44 #define CC_VERIF 0xb
45 #define CC_OPTIMO 0xd
46 #define CC_GEN 0xe
47 #define CC_PRIMECELL 0xf
50 #define ER_EROMENTRY 0x000
51 #define ER_REMAPCONTROL 0xe00
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]

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