1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * linux/arch/arm/mm/tlb-fa.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2005 Faraday Corp. 6*4882a593Smuzhiyun * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on tlb-v4wbi.S: 9*4882a593Smuzhiyun * Copyright (C) 1997-2002 Russell King 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * ARM architecture version 4, Faraday variation. 12*4882a593Smuzhiyun * This assume an unified TLBs, with a write buffer, and branch target buffer (BTB) 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Processors: FA520 FA526 FA626 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun#include <linux/linkage.h> 17*4882a593Smuzhiyun#include <linux/init.h> 18*4882a593Smuzhiyun#include <asm/assembler.h> 19*4882a593Smuzhiyun#include <asm/asm-offsets.h> 20*4882a593Smuzhiyun#include <asm/tlbflush.h> 21*4882a593Smuzhiyun#include "proc-macros.S" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun/* 25*4882a593Smuzhiyun * flush_user_tlb_range(start, end, mm) 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * Invalidate a range of TLB entries in the specified address space. 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * - start - range start address 30*4882a593Smuzhiyun * - end - range end address 31*4882a593Smuzhiyun * - mm - mm_struct describing address space 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun .align 4 34*4882a593SmuzhiyunENTRY(fa_flush_user_tlb_range) 35*4882a593Smuzhiyun vma_vm_mm ip, r2 36*4882a593Smuzhiyun act_mm r3 @ get current->active_mm 37*4882a593Smuzhiyun eors r3, ip, r3 @ == mm ? 38*4882a593Smuzhiyun retne lr @ no, we dont do anything 39*4882a593Smuzhiyun mov r3, #0 40*4882a593Smuzhiyun mcr p15, 0, r3, c7, c10, 4 @ drain WB 41*4882a593Smuzhiyun bic r0, r0, #0x0ff 42*4882a593Smuzhiyun bic r0, r0, #0xf00 43*4882a593Smuzhiyun1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 44*4882a593Smuzhiyun add r0, r0, #PAGE_SZ 45*4882a593Smuzhiyun cmp r0, r1 46*4882a593Smuzhiyun blo 1b 47*4882a593Smuzhiyun mcr p15, 0, r3, c7, c10, 4 @ data write barrier 48*4882a593Smuzhiyun ret lr 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunENTRY(fa_flush_kern_tlb_range) 52*4882a593Smuzhiyun mov r3, #0 53*4882a593Smuzhiyun mcr p15, 0, r3, c7, c10, 4 @ drain WB 54*4882a593Smuzhiyun bic r0, r0, #0x0ff 55*4882a593Smuzhiyun bic r0, r0, #0xf00 56*4882a593Smuzhiyun1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 57*4882a593Smuzhiyun add r0, r0, #PAGE_SZ 58*4882a593Smuzhiyun cmp r0, r1 59*4882a593Smuzhiyun blo 1b 60*4882a593Smuzhiyun mcr p15, 0, r3, c7, c10, 4 @ data write barrier 61*4882a593Smuzhiyun mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb) 62*4882a593Smuzhiyun ret lr 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun __INITDATA 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */ 67*4882a593Smuzhiyun define_tlb_functions fa, fa_tlb_flags 68