1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2009 Samsung Electronics 3*4882a593Smuzhiyun * Kyungmin Park <kyungmin.park@samsung.com> 4*4882a593Smuzhiyun * Minkyu Kang <mk7.kang@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <config.h> 10*4882a593Smuzhiyun#include <asm/arch/cpu.h> 11*4882a593Smuzhiyun#include <asm/arch/power.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/* 14*4882a593Smuzhiyun * Register usages: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * r5 has zero always 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun .globl lowlevel_init 20*4882a593Smuzhiyunlowlevel_init: 21*4882a593Smuzhiyun mov r9, lr 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* r5 has always zero */ 24*4882a593Smuzhiyun mov r5, #0 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun ldr r8, =S5PC100_GPIO_BASE 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Disable Watchdog */ 29*4882a593Smuzhiyun ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000 30*4882a593Smuzhiyun orr r0, r0, #0x0 31*4882a593Smuzhiyun str r5, [r0] 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* setting SRAM */ 34*4882a593Smuzhiyun ldr r0, =S5PC100_SROMC_BASE 35*4882a593Smuzhiyun ldr r1, =0x9 36*4882a593Smuzhiyun str r1, [r0] 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* S5PC100 has 3 groups of interrupt sources */ 39*4882a593Smuzhiyun ldr r0, =S5PC100_VIC0_BASE @0xE4000000 40*4882a593Smuzhiyun ldr r1, =S5PC100_VIC1_BASE @0xE4000000 41*4882a593Smuzhiyun ldr r2, =S5PC100_VIC2_BASE @0xE4000000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Disable all interrupts (VIC0, VIC1 and VIC2) */ 44*4882a593Smuzhiyun mvn r3, #0x0 45*4882a593Smuzhiyun str r3, [r0, #0x14] @INTENCLEAR 46*4882a593Smuzhiyun str r3, [r1, #0x14] @INTENCLEAR 47*4882a593Smuzhiyun str r3, [r2, #0x14] @INTENCLEAR 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Set all interrupts as IRQ */ 50*4882a593Smuzhiyun str r5, [r0, #0xc] @INTSELECT 51*4882a593Smuzhiyun str r5, [r1, #0xc] @INTSELECT 52*4882a593Smuzhiyun str r5, [r2, #0xc] @INTSELECT 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Pending Interrupt Clear */ 55*4882a593Smuzhiyun str r5, [r0, #0xf00] @INTADDRESS 56*4882a593Smuzhiyun str r5, [r1, #0xf00] @INTADDRESS 57*4882a593Smuzhiyun str r5, [r2, #0xf00] @INTADDRESS 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* for UART */ 60*4882a593Smuzhiyun bl uart_asm_init 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* for TZPC */ 63*4882a593Smuzhiyun bl tzpc_asm_init 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun1: 66*4882a593Smuzhiyun mov lr, r9 67*4882a593Smuzhiyun mov pc, lr 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun/* 70*4882a593Smuzhiyun * system_clock_init: Initialize core clock and bus clock. 71*4882a593Smuzhiyun * void system_clock_init(void) 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyunsystem_clock_init: 74*4882a593Smuzhiyun ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Set Clock divider */ 77*4882a593Smuzhiyun ldr r1, =0x00011110 78*4882a593Smuzhiyun str r1, [r8, #0x304] 79*4882a593Smuzhiyun ldr r1, =0x1 80*4882a593Smuzhiyun str r1, [r8, #0x308] 81*4882a593Smuzhiyun ldr r1, =0x00011301 82*4882a593Smuzhiyun str r1, [r8, #0x300] 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Set Lock Time */ 85*4882a593Smuzhiyun ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 86*4882a593Smuzhiyun str r1, [r8, #0x000] @ APLL_LOCK 87*4882a593Smuzhiyun str r1, [r8, #0x004] @ MPLL_LOCK 88*4882a593Smuzhiyun str r1, [r8, #0x008] @ EPLL_LOCK 89*4882a593Smuzhiyun str r1, [r8, #0x00C] @ HPLL_LOCK 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* APLL_CON */ 92*4882a593Smuzhiyun ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz) 93*4882a593Smuzhiyun str r1, [r8, #0x100] 94*4882a593Smuzhiyun /* MPLL_CON */ 95*4882a593Smuzhiyun ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) 96*4882a593Smuzhiyun str r1, [r8, #0x104] 97*4882a593Smuzhiyun /* EPLL_CON */ 98*4882a593Smuzhiyun ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) 99*4882a593Smuzhiyun str r1, [r8, #0x108] 100*4882a593Smuzhiyun /* HPLL_CON */ 101*4882a593Smuzhiyun ldr r1, =0x80600603 102*4882a593Smuzhiyun str r1, [r8, #0x10C] 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Set Source Clock */ 105*4882a593Smuzhiyun ldr r1, =0x1111 @ A, M, E, HPLL Muxing 106*4882a593Smuzhiyun str r1, [r8, #0x200] @ CLK_SRC0 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing 109*4882a593Smuzhiyun str r1, [r8, #0x204] @ CLK_SRC1 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun ldr r1, =0x9000 @ ARMCLK/4 112*4882a593Smuzhiyun str r1, [r8, #0x400] @ CLK_OUT 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* wait at least 200us to stablize all clock */ 115*4882a593Smuzhiyun mov r2, #0x10000 116*4882a593Smuzhiyun1: subs r2, r2, #1 117*4882a593Smuzhiyun bne 1b 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun mov pc, lr 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun/* 122*4882a593Smuzhiyun * uart_asm_init: Initialize UART's pins 123*4882a593Smuzhiyun */ 124*4882a593Smuzhiyunuart_asm_init: 125*4882a593Smuzhiyun mov r0, r8 126*4882a593Smuzhiyun ldr r1, =0x22222222 127*4882a593Smuzhiyun str r1, [r0, #0x0] @ GPA0_CON 128*4882a593Smuzhiyun ldr r1, =0x00022222 129*4882a593Smuzhiyun str r1, [r0, #0x20] @ GPA1_CON 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun mov pc, lr 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun/* 134*4882a593Smuzhiyun * tzpc_asm_init: Initialize TZPC 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyuntzpc_asm_init: 137*4882a593Smuzhiyun ldr r0, =0xE3800000 138*4882a593Smuzhiyun mov r1, #0x0 139*4882a593Smuzhiyun str r1, [r0] 140*4882a593Smuzhiyun mov r1, #0xff 141*4882a593Smuzhiyun str r1, [r0, #0x804] 142*4882a593Smuzhiyun str r1, [r0, #0x810] 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun ldr r0, =0xE2800000 145*4882a593Smuzhiyun str r1, [r0, #0x804] 146*4882a593Smuzhiyun str r1, [r0, #0x810] 147*4882a593Smuzhiyun str r1, [r0, #0x81C] 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun ldr r0, =0xE2900000 150*4882a593Smuzhiyun str r1, [r0, #0x804] 151*4882a593Smuzhiyun str r1, [r0, #0x810] 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun mov pc, lr 154