1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Common internal memory map for some Freescale SoCs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __FSL_SEC_MON_H 9*4882a593Smuzhiyun #define __FSL_SEC_MON_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_SEC_MON_LE 15*4882a593Smuzhiyun #define sec_mon_in32(a) in_le32(a) 16*4882a593Smuzhiyun #define sec_mon_out32(a, v) out_le32(a, v) 17*4882a593Smuzhiyun #define sec_mon_in16(a) in_le16(a) 18*4882a593Smuzhiyun #define sec_mon_clrbits32 clrbits_le32 19*4882a593Smuzhiyun #define sec_mon_setbits32 setbits_le32 20*4882a593Smuzhiyun #elif defined(CONFIG_SYS_FSL_SEC_MON_BE) 21*4882a593Smuzhiyun #define sec_mon_in32(a) in_be32(a) 22*4882a593Smuzhiyun #define sec_mon_out32(a, v) out_be32(a, v) 23*4882a593Smuzhiyun #define sec_mon_in16(a) in_be16(a) 24*4882a593Smuzhiyun #define sec_mon_clrbits32 clrbits_be32 25*4882a593Smuzhiyun #define sec_mon_setbits32 setbits_be32 26*4882a593Smuzhiyun #else 27*4882a593Smuzhiyun #error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct ccsr_sec_mon_regs { 31*4882a593Smuzhiyun u8 reserved0[0x04]; 32*4882a593Smuzhiyun u32 hp_com; /* 0x04 SEC_MON_HP Command Register */ 33*4882a593Smuzhiyun u8 reserved2[0x0c]; 34*4882a593Smuzhiyun u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */ 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define HPCOMR_SW_SV 0x100 /* Security Violation bit */ 38*4882a593Smuzhiyun #define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ 39*4882a593Smuzhiyun #define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ 40*4882a593Smuzhiyun #define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ 41*4882a593Smuzhiyun #define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ 42*4882a593Smuzhiyun #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */ 43*4882a593Smuzhiyun #define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */ 44*4882a593Smuzhiyun #define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */ 45*4882a593Smuzhiyun #define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */ 46*4882a593Smuzhiyun #define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */ 47*4882a593Smuzhiyun #define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * SEC_MON read. This specifies the possible reads 51*4882a593Smuzhiyun * from the SEC_MON 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun enum { 54*4882a593Smuzhiyun SEC_MON_SSM_ST, 55*4882a593Smuzhiyun SEC_MON_SW_FSV, 56*4882a593Smuzhiyun SEC_MON_SW_SV, 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Transition SEC_MON state */ 60*4882a593Smuzhiyun int set_sec_mon_state(u32 state); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* __FSL_SEC_MON_H */ 63