1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2019 MediaTek Inc.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/mfd/mt6358/registers.h>
6*4882a593Smuzhiyun #include <linux/mfd/mt6397/core.h>
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/regmap.h>
11*4882a593Smuzhiyun #include <linux/regulator/driver.h>
12*4882a593Smuzhiyun #include <linux/regulator/machine.h>
13*4882a593Smuzhiyun #include <linux/regulator/mt6358-regulator.h>
14*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define MT6358_BUCK_MODE_AUTO 0
17*4882a593Smuzhiyun #define MT6358_BUCK_MODE_FORCE_PWM 1
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * MT6358 regulators' information
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * @desc: standard fields of regulator description.
23*4882a593Smuzhiyun * @qi: Mask for query enable signal status of regulators
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun struct mt6358_regulator_info {
26*4882a593Smuzhiyun struct regulator_desc desc;
27*4882a593Smuzhiyun u32 status_reg;
28*4882a593Smuzhiyun u32 qi;
29*4882a593Smuzhiyun const u32 *index_table;
30*4882a593Smuzhiyun unsigned int n_table;
31*4882a593Smuzhiyun u32 vsel_shift;
32*4882a593Smuzhiyun u32 da_vsel_reg;
33*4882a593Smuzhiyun u32 da_vsel_mask;
34*4882a593Smuzhiyun u32 da_vsel_shift;
35*4882a593Smuzhiyun u32 modeset_reg;
36*4882a593Smuzhiyun u32 modeset_mask;
37*4882a593Smuzhiyun u32 modeset_shift;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define MT6358_BUCK(match, vreg, min, max, step, \
41*4882a593Smuzhiyun volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \
42*4882a593Smuzhiyun _da_vsel_shift, _modeset_reg, _modeset_shift) \
43*4882a593Smuzhiyun [MT6358_ID_##vreg] = { \
44*4882a593Smuzhiyun .desc = { \
45*4882a593Smuzhiyun .name = #vreg, \
46*4882a593Smuzhiyun .of_match = of_match_ptr(match), \
47*4882a593Smuzhiyun .ops = &mt6358_volt_range_ops, \
48*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
49*4882a593Smuzhiyun .id = MT6358_ID_##vreg, \
50*4882a593Smuzhiyun .owner = THIS_MODULE, \
51*4882a593Smuzhiyun .n_voltages = ((max) - (min)) / (step) + 1, \
52*4882a593Smuzhiyun .linear_ranges = volt_ranges, \
53*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
54*4882a593Smuzhiyun .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
55*4882a593Smuzhiyun .vsel_mask = vosel_mask, \
56*4882a593Smuzhiyun .enable_reg = MT6358_BUCK_##vreg##_CON0, \
57*4882a593Smuzhiyun .enable_mask = BIT(0), \
58*4882a593Smuzhiyun .of_map_mode = mt6358_map_mode, \
59*4882a593Smuzhiyun }, \
60*4882a593Smuzhiyun .status_reg = MT6358_BUCK_##vreg##_DBG1, \
61*4882a593Smuzhiyun .qi = BIT(0), \
62*4882a593Smuzhiyun .da_vsel_reg = _da_vsel_reg, \
63*4882a593Smuzhiyun .da_vsel_mask = _da_vsel_mask, \
64*4882a593Smuzhiyun .da_vsel_shift = _da_vsel_shift, \
65*4882a593Smuzhiyun .modeset_reg = _modeset_reg, \
66*4882a593Smuzhiyun .modeset_mask = BIT(_modeset_shift), \
67*4882a593Smuzhiyun .modeset_shift = _modeset_shift \
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define MT6358_LDO(match, vreg, ldo_volt_table, \
71*4882a593Smuzhiyun ldo_index_table, enreg, enbit, vosel, \
72*4882a593Smuzhiyun vosel_mask, vosel_shift) \
73*4882a593Smuzhiyun [MT6358_ID_##vreg] = { \
74*4882a593Smuzhiyun .desc = { \
75*4882a593Smuzhiyun .name = #vreg, \
76*4882a593Smuzhiyun .of_match = of_match_ptr(match), \
77*4882a593Smuzhiyun .ops = &mt6358_volt_table_ops, \
78*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
79*4882a593Smuzhiyun .id = MT6358_ID_##vreg, \
80*4882a593Smuzhiyun .owner = THIS_MODULE, \
81*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(ldo_volt_table), \
82*4882a593Smuzhiyun .volt_table = ldo_volt_table, \
83*4882a593Smuzhiyun .vsel_reg = vosel, \
84*4882a593Smuzhiyun .vsel_mask = vosel_mask, \
85*4882a593Smuzhiyun .enable_reg = enreg, \
86*4882a593Smuzhiyun .enable_mask = BIT(enbit), \
87*4882a593Smuzhiyun }, \
88*4882a593Smuzhiyun .status_reg = MT6358_LDO_##vreg##_CON1, \
89*4882a593Smuzhiyun .qi = BIT(15), \
90*4882a593Smuzhiyun .index_table = ldo_index_table, \
91*4882a593Smuzhiyun .n_table = ARRAY_SIZE(ldo_index_table), \
92*4882a593Smuzhiyun .vsel_shift = vosel_shift, \
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #define MT6358_LDO1(match, vreg, min, max, step, \
96*4882a593Smuzhiyun volt_ranges, _da_vsel_reg, _da_vsel_mask, \
97*4882a593Smuzhiyun _da_vsel_shift, vosel, vosel_mask) \
98*4882a593Smuzhiyun [MT6358_ID_##vreg] = { \
99*4882a593Smuzhiyun .desc = { \
100*4882a593Smuzhiyun .name = #vreg, \
101*4882a593Smuzhiyun .of_match = of_match_ptr(match), \
102*4882a593Smuzhiyun .ops = &mt6358_volt_range_ops, \
103*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
104*4882a593Smuzhiyun .id = MT6358_ID_##vreg, \
105*4882a593Smuzhiyun .owner = THIS_MODULE, \
106*4882a593Smuzhiyun .n_voltages = ((max) - (min)) / (step) + 1, \
107*4882a593Smuzhiyun .linear_ranges = volt_ranges, \
108*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
109*4882a593Smuzhiyun .vsel_reg = vosel, \
110*4882a593Smuzhiyun .vsel_mask = vosel_mask, \
111*4882a593Smuzhiyun .enable_reg = MT6358_LDO_##vreg##_CON0, \
112*4882a593Smuzhiyun .enable_mask = BIT(0), \
113*4882a593Smuzhiyun }, \
114*4882a593Smuzhiyun .da_vsel_reg = _da_vsel_reg, \
115*4882a593Smuzhiyun .da_vsel_mask = _da_vsel_mask, \
116*4882a593Smuzhiyun .da_vsel_shift = _da_vsel_shift, \
117*4882a593Smuzhiyun .status_reg = MT6358_LDO_##vreg##_DBG1, \
118*4882a593Smuzhiyun .qi = BIT(0), \
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define MT6358_REG_FIXED(match, vreg, \
122*4882a593Smuzhiyun enreg, enbit, volt) \
123*4882a593Smuzhiyun [MT6358_ID_##vreg] = { \
124*4882a593Smuzhiyun .desc = { \
125*4882a593Smuzhiyun .name = #vreg, \
126*4882a593Smuzhiyun .of_match = of_match_ptr(match), \
127*4882a593Smuzhiyun .ops = &mt6358_volt_fixed_ops, \
128*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
129*4882a593Smuzhiyun .id = MT6358_ID_##vreg, \
130*4882a593Smuzhiyun .owner = THIS_MODULE, \
131*4882a593Smuzhiyun .n_voltages = 1, \
132*4882a593Smuzhiyun .enable_reg = enreg, \
133*4882a593Smuzhiyun .enable_mask = BIT(enbit), \
134*4882a593Smuzhiyun .min_uV = volt, \
135*4882a593Smuzhiyun }, \
136*4882a593Smuzhiyun .status_reg = MT6358_LDO_##vreg##_CON1, \
137*4882a593Smuzhiyun .qi = BIT(15), \
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun static const struct linear_range buck_volt_range1[] = {
141*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun static const struct linear_range buck_volt_range2[] = {
145*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun static const struct linear_range buck_volt_range3[] = {
149*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static const struct linear_range buck_volt_range4[] = {
153*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun static const u32 vdram2_voltages[] = {
157*4882a593Smuzhiyun 600000, 1800000,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun static const u32 vsim_voltages[] = {
161*4882a593Smuzhiyun 1700000, 1800000, 2700000, 3000000, 3100000,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static const u32 vibr_voltages[] = {
165*4882a593Smuzhiyun 1200000, 1300000, 1500000, 1800000,
166*4882a593Smuzhiyun 2000000, 2800000, 3000000, 3300000,
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static const u32 vusb_voltages[] = {
170*4882a593Smuzhiyun 3000000, 3100000,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun static const u32 vcamd_voltages[] = {
174*4882a593Smuzhiyun 900000, 1000000, 1100000, 1200000,
175*4882a593Smuzhiyun 1300000, 1500000, 1800000,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun static const u32 vefuse_voltages[] = {
179*4882a593Smuzhiyun 1700000, 1800000, 1900000,
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun static const u32 vmch_vemc_voltages[] = {
183*4882a593Smuzhiyun 2900000, 3000000, 3300000,
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static const u32 vcama_voltages[] = {
187*4882a593Smuzhiyun 1800000, 2500000, 2700000,
188*4882a593Smuzhiyun 2800000, 2900000, 3000000,
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun static const u32 vcn33_bt_wifi_voltages[] = {
192*4882a593Smuzhiyun 3300000, 3400000, 3500000,
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static const u32 vmc_voltages[] = {
196*4882a593Smuzhiyun 1800000, 2900000, 3000000, 3300000,
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun static const u32 vldo28_voltages[] = {
200*4882a593Smuzhiyun 2800000, 3000000,
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static const u32 vdram2_idx[] = {
204*4882a593Smuzhiyun 0, 12,
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static const u32 vsim_idx[] = {
208*4882a593Smuzhiyun 3, 4, 8, 11, 12,
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static const u32 vibr_idx[] = {
212*4882a593Smuzhiyun 0, 1, 2, 4, 5, 9, 11, 13,
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun static const u32 vusb_idx[] = {
216*4882a593Smuzhiyun 3, 4,
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun static const u32 vcamd_idx[] = {
220*4882a593Smuzhiyun 3, 4, 5, 6, 7, 9, 12,
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun static const u32 vefuse_idx[] = {
224*4882a593Smuzhiyun 11, 12, 13,
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun static const u32 vmch_vemc_idx[] = {
228*4882a593Smuzhiyun 2, 3, 5,
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static const u32 vcama_idx[] = {
232*4882a593Smuzhiyun 0, 7, 9, 10, 11, 12,
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun static const u32 vcn33_bt_wifi_idx[] = {
236*4882a593Smuzhiyun 1, 2, 3,
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static const u32 vmc_idx[] = {
240*4882a593Smuzhiyun 4, 10, 11, 13,
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun static const u32 vldo28_idx[] = {
244*4882a593Smuzhiyun 1, 3,
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
mt6358_map_mode(unsigned int mode)247*4882a593Smuzhiyun static unsigned int mt6358_map_mode(unsigned int mode)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun return mode == MT6358_BUCK_MODE_AUTO ?
250*4882a593Smuzhiyun REGULATOR_MODE_NORMAL : REGULATOR_MODE_FAST;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
mt6358_set_voltage_sel(struct regulator_dev * rdev,unsigned int selector)253*4882a593Smuzhiyun static int mt6358_set_voltage_sel(struct regulator_dev *rdev,
254*4882a593Smuzhiyun unsigned int selector)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun int idx, ret;
257*4882a593Smuzhiyun const u32 *pvol;
258*4882a593Smuzhiyun struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun pvol = info->index_table;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun idx = pvol[selector];
263*4882a593Smuzhiyun ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg,
264*4882a593Smuzhiyun info->desc.vsel_mask,
265*4882a593Smuzhiyun idx << info->vsel_shift);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return ret;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
mt6358_get_voltage_sel(struct regulator_dev * rdev)270*4882a593Smuzhiyun static int mt6358_get_voltage_sel(struct regulator_dev *rdev)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun int idx, ret;
273*4882a593Smuzhiyun u32 selector;
274*4882a593Smuzhiyun struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
275*4882a593Smuzhiyun const u32 *pvol;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector);
278*4882a593Smuzhiyun if (ret != 0) {
279*4882a593Smuzhiyun dev_info(&rdev->dev,
280*4882a593Smuzhiyun "Failed to get mt6358 %s vsel reg: %d\n",
281*4882a593Smuzhiyun info->desc.name, ret);
282*4882a593Smuzhiyun return ret;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun selector = (selector & info->desc.vsel_mask) >> info->vsel_shift;
286*4882a593Smuzhiyun pvol = info->index_table;
287*4882a593Smuzhiyun for (idx = 0; idx < info->desc.n_voltages; idx++) {
288*4882a593Smuzhiyun if (pvol[idx] == selector)
289*4882a593Smuzhiyun return idx;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun return -EINVAL;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
mt6358_get_buck_voltage_sel(struct regulator_dev * rdev)295*4882a593Smuzhiyun static int mt6358_get_buck_voltage_sel(struct regulator_dev *rdev)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun int ret, regval;
298*4882a593Smuzhiyun struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val);
301*4882a593Smuzhiyun if (ret != 0) {
302*4882a593Smuzhiyun dev_err(&rdev->dev,
303*4882a593Smuzhiyun "Failed to get mt6358 Buck %s vsel reg: %d\n",
304*4882a593Smuzhiyun info->desc.name, ret);
305*4882a593Smuzhiyun return ret;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun ret = (regval >> info->da_vsel_shift) & info->da_vsel_mask;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun return ret;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
mt6358_get_status(struct regulator_dev * rdev)313*4882a593Smuzhiyun static int mt6358_get_status(struct regulator_dev *rdev)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun int ret;
316*4882a593Smuzhiyun u32 regval;
317*4882a593Smuzhiyun struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, info->status_reg, ®val);
320*4882a593Smuzhiyun if (ret != 0) {
321*4882a593Smuzhiyun dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret);
322*4882a593Smuzhiyun return ret;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
mt6358_regulator_set_mode(struct regulator_dev * rdev,unsigned int mode)328*4882a593Smuzhiyun static int mt6358_regulator_set_mode(struct regulator_dev *rdev,
329*4882a593Smuzhiyun unsigned int mode)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
332*4882a593Smuzhiyun int val;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun switch (mode) {
335*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
336*4882a593Smuzhiyun val = MT6358_BUCK_MODE_FORCE_PWM;
337*4882a593Smuzhiyun break;
338*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
339*4882a593Smuzhiyun val = MT6358_BUCK_MODE_AUTO;
340*4882a593Smuzhiyun break;
341*4882a593Smuzhiyun default:
342*4882a593Smuzhiyun return -EINVAL;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x, %#x\n",
346*4882a593Smuzhiyun info->modeset_reg, info->modeset_mask,
347*4882a593Smuzhiyun info->modeset_shift, val);
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun val <<= info->modeset_shift;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, info->modeset_reg,
352*4882a593Smuzhiyun info->modeset_mask, val);
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
mt6358_regulator_get_mode(struct regulator_dev * rdev)355*4882a593Smuzhiyun static unsigned int mt6358_regulator_get_mode(struct regulator_dev *rdev)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
358*4882a593Smuzhiyun int ret, regval;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, info->modeset_reg, ®val);
361*4882a593Smuzhiyun if (ret != 0) {
362*4882a593Smuzhiyun dev_err(&rdev->dev,
363*4882a593Smuzhiyun "Failed to get mt6358 buck mode: %d\n", ret);
364*4882a593Smuzhiyun return ret;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun switch ((regval & info->modeset_mask) >> info->modeset_shift) {
368*4882a593Smuzhiyun case MT6358_BUCK_MODE_AUTO:
369*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
370*4882a593Smuzhiyun case MT6358_BUCK_MODE_FORCE_PWM:
371*4882a593Smuzhiyun return REGULATOR_MODE_FAST;
372*4882a593Smuzhiyun default:
373*4882a593Smuzhiyun return -EINVAL;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun static const struct regulator_ops mt6358_volt_range_ops = {
378*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
379*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
380*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
381*4882a593Smuzhiyun .get_voltage_sel = mt6358_get_buck_voltage_sel,
382*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
383*4882a593Smuzhiyun .enable = regulator_enable_regmap,
384*4882a593Smuzhiyun .disable = regulator_disable_regmap,
385*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
386*4882a593Smuzhiyun .get_status = mt6358_get_status,
387*4882a593Smuzhiyun .set_mode = mt6358_regulator_set_mode,
388*4882a593Smuzhiyun .get_mode = mt6358_regulator_get_mode,
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun static const struct regulator_ops mt6358_volt_table_ops = {
392*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_table,
393*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_iterate,
394*4882a593Smuzhiyun .set_voltage_sel = mt6358_set_voltage_sel,
395*4882a593Smuzhiyun .get_voltage_sel = mt6358_get_voltage_sel,
396*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
397*4882a593Smuzhiyun .enable = regulator_enable_regmap,
398*4882a593Smuzhiyun .disable = regulator_disable_regmap,
399*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
400*4882a593Smuzhiyun .get_status = mt6358_get_status,
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun static const struct regulator_ops mt6358_volt_fixed_ops = {
404*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
405*4882a593Smuzhiyun .enable = regulator_enable_regmap,
406*4882a593Smuzhiyun .disable = regulator_disable_regmap,
407*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
408*4882a593Smuzhiyun .get_status = mt6358_get_status,
409*4882a593Smuzhiyun };
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun /* The array is indexed by id(MT6358_ID_XXX) */
412*4882a593Smuzhiyun static struct mt6358_regulator_info mt6358_regulators[] = {
413*4882a593Smuzhiyun MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
414*4882a593Smuzhiyun buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
415*4882a593Smuzhiyun 0, MT6358_VDRAM1_ANA_CON0, 8),
416*4882a593Smuzhiyun MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
417*4882a593Smuzhiyun buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
418*4882a593Smuzhiyun 0, MT6358_VCORE_VGPU_ANA_CON0, 1),
419*4882a593Smuzhiyun MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
420*4882a593Smuzhiyun buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, 0,
421*4882a593Smuzhiyun MT6358_VPA_ANA_CON0, 3),
422*4882a593Smuzhiyun MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
423*4882a593Smuzhiyun buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
424*4882a593Smuzhiyun 0, MT6358_VPROC_ANA_CON0, 1),
425*4882a593Smuzhiyun MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
426*4882a593Smuzhiyun buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
427*4882a593Smuzhiyun 0, MT6358_VPROC_ANA_CON0, 2),
428*4882a593Smuzhiyun MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
429*4882a593Smuzhiyun buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, 0,
430*4882a593Smuzhiyun MT6358_VCORE_VGPU_ANA_CON0, 2),
431*4882a593Smuzhiyun MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
432*4882a593Smuzhiyun buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, 0,
433*4882a593Smuzhiyun MT6358_VS2_ANA_CON0, 8),
434*4882a593Smuzhiyun MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
435*4882a593Smuzhiyun buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
436*4882a593Smuzhiyun 0, MT6358_VMODEM_ANA_CON0, 8),
437*4882a593Smuzhiyun MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
438*4882a593Smuzhiyun buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, 0,
439*4882a593Smuzhiyun MT6358_VS1_ANA_CON0, 8),
440*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vrf12", VRF12,
441*4882a593Smuzhiyun MT6358_LDO_VRF12_CON0, 0, 1200000),
442*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vio18", VIO18,
443*4882a593Smuzhiyun MT6358_LDO_VIO18_CON0, 0, 1800000),
444*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vcamio", VCAMIO,
445*4882a593Smuzhiyun MT6358_LDO_VCAMIO_CON0, 0, 1800000),
446*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
447*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
448*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
449*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
450*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vaux18", VAUX18,
451*4882a593Smuzhiyun MT6358_LDO_VAUX18_CON0, 0, 1800000),
452*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vbif28", VBIF28,
453*4882a593Smuzhiyun MT6358_LDO_VBIF28_CON0, 0, 2800000),
454*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
455*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
456*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
457*4882a593Smuzhiyun MT6358_REG_FIXED("ldo_vaud28", VAUD28,
458*4882a593Smuzhiyun MT6358_LDO_VAUD28_CON0, 0, 2800000),
459*4882a593Smuzhiyun MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
460*4882a593Smuzhiyun MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf, 0),
461*4882a593Smuzhiyun MT6358_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx,
462*4882a593Smuzhiyun MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00, 8),
463*4882a593Smuzhiyun MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
464*4882a593Smuzhiyun MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00, 8),
465*4882a593Smuzhiyun MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
466*4882a593Smuzhiyun MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700, 8),
467*4882a593Smuzhiyun MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx,
468*4882a593Smuzhiyun MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00, 8),
469*4882a593Smuzhiyun MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
470*4882a593Smuzhiyun MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00, 8),
471*4882a593Smuzhiyun MT6358_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx,
472*4882a593Smuzhiyun MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700, 8),
473*4882a593Smuzhiyun MT6358_LDO("ldo_vcama1", VCAMA1, vcama_voltages, vcama_idx,
474*4882a593Smuzhiyun MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00, 8),
475*4882a593Smuzhiyun MT6358_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx,
476*4882a593Smuzhiyun MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700, 8),
477*4882a593Smuzhiyun MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
478*4882a593Smuzhiyun vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
479*4882a593Smuzhiyun 0, MT6358_VCN33_ANA_CON0, 0x300, 8),
480*4882a593Smuzhiyun MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
481*4882a593Smuzhiyun vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
482*4882a593Smuzhiyun 0, MT6358_VCN33_ANA_CON0, 0x300, 8),
483*4882a593Smuzhiyun MT6358_LDO("ldo_vcama2", VCAMA2, vcama_voltages, vcama_idx,
484*4882a593Smuzhiyun MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00, 8),
485*4882a593Smuzhiyun MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
486*4882a593Smuzhiyun MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00, 8),
487*4882a593Smuzhiyun MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx,
488*4882a593Smuzhiyun MT6358_LDO_VLDO28_CON0_0, 0,
489*4882a593Smuzhiyun MT6358_VLDO28_ANA_CON0, 0x300, 8),
490*4882a593Smuzhiyun MT6358_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx,
491*4882a593Smuzhiyun MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00, 8),
492*4882a593Smuzhiyun MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
493*4882a593Smuzhiyun buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f, 8,
494*4882a593Smuzhiyun MT6358_LDO_VSRAM_CON0, 0x7f),
495*4882a593Smuzhiyun MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
496*4882a593Smuzhiyun buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f, 8,
497*4882a593Smuzhiyun MT6358_LDO_VSRAM_CON2, 0x7f),
498*4882a593Smuzhiyun MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
499*4882a593Smuzhiyun buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f, 8,
500*4882a593Smuzhiyun MT6358_LDO_VSRAM_CON3, 0x7f),
501*4882a593Smuzhiyun MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
502*4882a593Smuzhiyun buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f, 8,
503*4882a593Smuzhiyun MT6358_LDO_VSRAM_CON1, 0x7f),
504*4882a593Smuzhiyun };
505*4882a593Smuzhiyun
mt6358_regulator_probe(struct platform_device * pdev)506*4882a593Smuzhiyun static int mt6358_regulator_probe(struct platform_device *pdev)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
509*4882a593Smuzhiyun struct regulator_config config = {};
510*4882a593Smuzhiyun struct regulator_dev *rdev;
511*4882a593Smuzhiyun int i;
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun for (i = 0; i < MT6358_MAX_REGULATOR; i++) {
514*4882a593Smuzhiyun config.dev = &pdev->dev;
515*4882a593Smuzhiyun config.driver_data = &mt6358_regulators[i];
516*4882a593Smuzhiyun config.regmap = mt6397->regmap;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev,
519*4882a593Smuzhiyun &mt6358_regulators[i].desc,
520*4882a593Smuzhiyun &config);
521*4882a593Smuzhiyun if (IS_ERR(rdev)) {
522*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to register %s\n",
523*4882a593Smuzhiyun mt6358_regulators[i].desc.name);
524*4882a593Smuzhiyun return PTR_ERR(rdev);
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun return 0;
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun static const struct platform_device_id mt6358_platform_ids[] = {
532*4882a593Smuzhiyun {"mt6358-regulator", 0},
533*4882a593Smuzhiyun { /* sentinel */ },
534*4882a593Smuzhiyun };
535*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, mt6358_platform_ids);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun static struct platform_driver mt6358_regulator_driver = {
538*4882a593Smuzhiyun .driver = {
539*4882a593Smuzhiyun .name = "mt6358-regulator",
540*4882a593Smuzhiyun },
541*4882a593Smuzhiyun .probe = mt6358_regulator_probe,
542*4882a593Smuzhiyun .id_table = mt6358_platform_ids,
543*4882a593Smuzhiyun };
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun module_platform_driver(mt6358_regulator_driver);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
548*4882a593Smuzhiyun MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6358 PMIC");
549*4882a593Smuzhiyun MODULE_LICENSE("GPL");
550