1 /* 2 * Broadcom AMBA Interconnect definitions. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: aidmp.h 617751 2016-02-08 09:04:22Z $ 30 */ 31 32 #ifndef _AIDMP_H 33 #define _AIDMP_H 34 35 /* Manufacturer Ids */ 36 #define MFGID_ARM 0x43b 37 #define MFGID_BRCM 0x4bf 38 #define MFGID_MIPS 0x4a7 39 40 /* Component Classes */ 41 #define CC_SIM 0 42 #define CC_EROM 1 43 #define CC_CORESIGHT 9 44 #define CC_VERIF 0xb 45 #define CC_OPTIMO 0xd 46 #define CC_GEN 0xe 47 #define CC_PRIMECELL 0xf 48 49 /* Enumeration ROM registers */ 50 #define ER_EROMENTRY 0x000 51 #define ER_REMAPCONTROL 0xe00 52 #define ER_REMAPSELECT 0xe04 53 #define ER_MASTERSELECT 0xe10 54 #define ER_ITCR 0xf00 55 #define ER_ITIP 0xf04 56 57 /* Erom entries */ 58 #define ER_TAG 0xe 59 #define ER_TAG1 0x6 60 #define ER_VALID 1 61 #define ER_CI 0 62 #define ER_MP 2 63 #define ER_ADD 4 64 #define ER_END 0xe 65 #define ER_BAD 0xffffffff 66 #define ER_SZ_MAX 4096 /* 4KB */ 67 68 /* EROM CompIdentA */ 69 #define CIA_MFG_MASK 0xfff00000 70 #define CIA_MFG_SHIFT 20 71 #define CIA_CID_MASK 0x000fff00 72 #define CIA_CID_SHIFT 8 73 #define CIA_CCL_MASK 0x000000f0 74 #define CIA_CCL_SHIFT 4 75 76 /* EROM CompIdentB */ 77 #define CIB_REV_MASK 0xff000000 78 #define CIB_REV_SHIFT 24 79 #define CIB_NSW_MASK 0x00f80000 80 #define CIB_NSW_SHIFT 19 81 #define CIB_NMW_MASK 0x0007c000 82 #define CIB_NMW_SHIFT 14 83 #define CIB_NSP_MASK 0x00003e00 84 #define CIB_NSP_SHIFT 9 85 #define CIB_NMP_MASK 0x000001f0 86 #define CIB_NMP_SHIFT 4 87 88 /* EROM MasterPortDesc */ 89 #define MPD_MUI_MASK 0x0000ff00 90 #define MPD_MUI_SHIFT 8 91 #define MPD_MP_MASK 0x000000f0 92 #define MPD_MP_SHIFT 4 93 94 /* EROM AddrDesc */ 95 #define AD_ADDR_MASK 0xfffff000 96 #define AD_SP_MASK 0x00000f00 97 #define AD_SP_SHIFT 8 98 #define AD_ST_MASK 0x000000c0 99 #define AD_ST_SHIFT 6 100 #define AD_ST_SLAVE 0x00000000 101 #define AD_ST_BRIDGE 0x00000040 102 #define AD_ST_SWRAP 0x00000080 103 #define AD_ST_MWRAP 0x000000c0 104 #define AD_SZ_MASK 0x00000030 105 #define AD_SZ_SHIFT 4 106 #define AD_SZ_4K 0x00000000 107 #define AD_SZ_8K 0x00000010 108 #define AD_SZ_16K 0x00000020 109 #define AD_SZ_SZD 0x00000030 110 #define AD_AG32 0x00000008 111 #define AD_ADDR_ALIGN 0x00000fff 112 #define AD_SZ_BASE 0x00001000 /* 4KB */ 113 114 /* EROM SizeDesc */ 115 #define SD_SZ_MASK 0xfffff000 116 #define SD_SG32 0x00000008 117 #define SD_SZ_ALIGN 0x00000fff 118 119 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 120 121 typedef volatile struct _aidmp { 122 uint32 oobselina30; /* 0x000 */ 123 uint32 oobselina74; /* 0x004 */ 124 uint32 PAD[6]; 125 uint32 oobselinb30; /* 0x020 */ 126 uint32 oobselinb74; /* 0x024 */ 127 uint32 PAD[6]; 128 uint32 oobselinc30; /* 0x040 */ 129 uint32 oobselinc74; /* 0x044 */ 130 uint32 PAD[6]; 131 uint32 oobselind30; /* 0x060 */ 132 uint32 oobselind74; /* 0x064 */ 133 uint32 PAD[38]; 134 uint32 oobselouta30; /* 0x100 */ 135 uint32 oobselouta74; /* 0x104 */ 136 uint32 PAD[6]; 137 uint32 oobseloutb30; /* 0x120 */ 138 uint32 oobseloutb74; /* 0x124 */ 139 uint32 PAD[6]; 140 uint32 oobseloutc30; /* 0x140 */ 141 uint32 oobseloutc74; /* 0x144 */ 142 uint32 PAD[6]; 143 uint32 oobseloutd30; /* 0x160 */ 144 uint32 oobseloutd74; /* 0x164 */ 145 uint32 PAD[38]; 146 uint32 oobsynca; /* 0x200 */ 147 uint32 oobseloutaen; /* 0x204 */ 148 uint32 PAD[6]; 149 uint32 oobsyncb; /* 0x220 */ 150 uint32 oobseloutben; /* 0x224 */ 151 uint32 PAD[6]; 152 uint32 oobsyncc; /* 0x240 */ 153 uint32 oobseloutcen; /* 0x244 */ 154 uint32 PAD[6]; 155 uint32 oobsyncd; /* 0x260 */ 156 uint32 oobseloutden; /* 0x264 */ 157 uint32 PAD[38]; 158 uint32 oobaextwidth; /* 0x300 */ 159 uint32 oobainwidth; /* 0x304 */ 160 uint32 oobaoutwidth; /* 0x308 */ 161 uint32 PAD[5]; 162 uint32 oobbextwidth; /* 0x320 */ 163 uint32 oobbinwidth; /* 0x324 */ 164 uint32 oobboutwidth; /* 0x328 */ 165 uint32 PAD[5]; 166 uint32 oobcextwidth; /* 0x340 */ 167 uint32 oobcinwidth; /* 0x344 */ 168 uint32 oobcoutwidth; /* 0x348 */ 169 uint32 PAD[5]; 170 uint32 oobdextwidth; /* 0x360 */ 171 uint32 oobdinwidth; /* 0x364 */ 172 uint32 oobdoutwidth; /* 0x368 */ 173 uint32 PAD[37]; 174 uint32 ioctrlset; /* 0x400 */ 175 uint32 ioctrlclear; /* 0x404 */ 176 uint32 ioctrl; /* 0x408 */ 177 uint32 PAD[61]; 178 uint32 iostatus; /* 0x500 */ 179 uint32 PAD[127]; 180 uint32 ioctrlwidth; /* 0x700 */ 181 uint32 iostatuswidth; /* 0x704 */ 182 uint32 PAD[62]; 183 uint32 resetctrl; /* 0x800 */ 184 uint32 resetstatus; /* 0x804 */ 185 uint32 resetreadid; /* 0x808 */ 186 uint32 resetwriteid; /* 0x80c */ 187 uint32 PAD[60]; 188 uint32 errlogctrl; /* 0x900 */ 189 uint32 errlogdone; /* 0x904 */ 190 uint32 errlogstatus; /* 0x908 */ 191 uint32 errlogaddrlo; /* 0x90c */ 192 uint32 errlogaddrhi; /* 0x910 */ 193 uint32 errlogid; /* 0x914 */ 194 uint32 errloguser; /* 0x918 */ 195 uint32 errlogflags; /* 0x91c */ 196 uint32 PAD[56]; 197 uint32 intstatus; /* 0xa00 */ 198 uint32 PAD[255]; 199 uint32 config; /* 0xe00 */ 200 uint32 PAD[63]; 201 uint32 itcr; /* 0xf00 */ 202 uint32 PAD[3]; 203 uint32 itipooba; /* 0xf10 */ 204 uint32 itipoobb; /* 0xf14 */ 205 uint32 itipoobc; /* 0xf18 */ 206 uint32 itipoobd; /* 0xf1c */ 207 uint32 PAD[4]; 208 uint32 itipoobaout; /* 0xf30 */ 209 uint32 itipoobbout; /* 0xf34 */ 210 uint32 itipoobcout; /* 0xf38 */ 211 uint32 itipoobdout; /* 0xf3c */ 212 uint32 PAD[4]; 213 uint32 itopooba; /* 0xf50 */ 214 uint32 itopoobb; /* 0xf54 */ 215 uint32 itopoobc; /* 0xf58 */ 216 uint32 itopoobd; /* 0xf5c */ 217 uint32 PAD[4]; 218 uint32 itopoobain; /* 0xf70 */ 219 uint32 itopoobbin; /* 0xf74 */ 220 uint32 itopoobcin; /* 0xf78 */ 221 uint32 itopoobdin; /* 0xf7c */ 222 uint32 PAD[4]; 223 uint32 itopreset; /* 0xf90 */ 224 uint32 PAD[15]; 225 uint32 peripherialid4; /* 0xfd0 */ 226 uint32 peripherialid5; /* 0xfd4 */ 227 uint32 peripherialid6; /* 0xfd8 */ 228 uint32 peripherialid7; /* 0xfdc */ 229 uint32 peripherialid0; /* 0xfe0 */ 230 uint32 peripherialid1; /* 0xfe4 */ 231 uint32 peripherialid2; /* 0xfe8 */ 232 uint32 peripherialid3; /* 0xfec */ 233 uint32 componentid0; /* 0xff0 */ 234 uint32 componentid1; /* 0xff4 */ 235 uint32 componentid2; /* 0xff8 */ 236 uint32 componentid3; /* 0xffc */ 237 } aidmp_t; 238 239 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ 240 241 /* Out-of-band Router registers */ 242 #define OOB_BUSCONFIG 0x020 243 #define OOB_STATUSA 0x100 244 #define OOB_STATUSB 0x104 245 #define OOB_STATUSC 0x108 246 #define OOB_STATUSD 0x10c 247 #define OOB_ENABLEA0 0x200 248 #define OOB_ENABLEA1 0x204 249 #define OOB_ENABLEA2 0x208 250 #define OOB_ENABLEA3 0x20c 251 #define OOB_ENABLEB0 0x280 252 #define OOB_ENABLEB1 0x284 253 #define OOB_ENABLEB2 0x288 254 #define OOB_ENABLEB3 0x28c 255 #define OOB_ENABLEC0 0x300 256 #define OOB_ENABLEC1 0x304 257 #define OOB_ENABLEC2 0x308 258 #define OOB_ENABLEC3 0x30c 259 #define OOB_ENABLED0 0x380 260 #define OOB_ENABLED1 0x384 261 #define OOB_ENABLED2 0x388 262 #define OOB_ENABLED3 0x38c 263 #define OOB_ITCR 0xf00 264 #define OOB_ITIPOOBA 0xf10 265 #define OOB_ITIPOOBB 0xf14 266 #define OOB_ITIPOOBC 0xf18 267 #define OOB_ITIPOOBD 0xf1c 268 #define OOB_ITOPOOBA 0xf30 269 #define OOB_ITOPOOBB 0xf34 270 #define OOB_ITOPOOBC 0xf38 271 #define OOB_ITOPOOBD 0xf3c 272 273 /* DMP wrapper registers */ 274 #define AI_OOBSELINA30 0x000 275 #define AI_OOBSELINA74 0x004 276 #define AI_OOBSELINB30 0x020 277 #define AI_OOBSELINB74 0x024 278 #define AI_OOBSELINC30 0x040 279 #define AI_OOBSELINC74 0x044 280 #define AI_OOBSELIND30 0x060 281 #define AI_OOBSELIND74 0x064 282 #define AI_OOBSELOUTA30 0x100 283 #define AI_OOBSELOUTA74 0x104 284 #define AI_OOBSELOUTB30 0x120 285 #define AI_OOBSELOUTB74 0x124 286 #define AI_OOBSELOUTC30 0x140 287 #define AI_OOBSELOUTC74 0x144 288 #define AI_OOBSELOUTD30 0x160 289 #define AI_OOBSELOUTD74 0x164 290 #define AI_OOBSYNCA 0x200 291 #define AI_OOBSELOUTAEN 0x204 292 #define AI_OOBSYNCB 0x220 293 #define AI_OOBSELOUTBEN 0x224 294 #define AI_OOBSYNCC 0x240 295 #define AI_OOBSELOUTCEN 0x244 296 #define AI_OOBSYNCD 0x260 297 #define AI_OOBSELOUTDEN 0x264 298 #define AI_OOBAEXTWIDTH 0x300 299 #define AI_OOBAINWIDTH 0x304 300 #define AI_OOBAOUTWIDTH 0x308 301 #define AI_OOBBEXTWIDTH 0x320 302 #define AI_OOBBINWIDTH 0x324 303 #define AI_OOBBOUTWIDTH 0x328 304 #define AI_OOBCEXTWIDTH 0x340 305 #define AI_OOBCINWIDTH 0x344 306 #define AI_OOBCOUTWIDTH 0x348 307 #define AI_OOBDEXTWIDTH 0x360 308 #define AI_OOBDINWIDTH 0x364 309 #define AI_OOBDOUTWIDTH 0x368 310 311 #define AI_IOCTRLSET 0x400 312 #define AI_IOCTRLCLEAR 0x404 313 #define AI_IOCTRL 0x408 314 #define AI_IOSTATUS 0x500 315 #define AI_RESETCTRL 0x800 316 #define AI_RESETSTATUS 0x804 317 318 #define AI_IOCTRLWIDTH 0x700 319 #define AI_IOSTATUSWIDTH 0x704 320 321 #define AI_RESETREADID 0x808 322 #define AI_RESETWRITEID 0x80c 323 #define AI_ERRLOGCTRL 0x900 324 #define AI_ERRLOGDONE 0x904 325 #define AI_ERRLOGSTATUS 0x908 326 #define AI_ERRLOGADDRLO 0x90c 327 #define AI_ERRLOGADDRHI 0x910 328 #define AI_ERRLOGID 0x914 329 #define AI_ERRLOGUSER 0x918 330 #define AI_ERRLOGFLAGS 0x91c 331 #define AI_INTSTATUS 0xa00 332 #define AI_CONFIG 0xe00 333 #define AI_ITCR 0xf00 334 #define AI_ITIPOOBA 0xf10 335 #define AI_ITIPOOBB 0xf14 336 #define AI_ITIPOOBC 0xf18 337 #define AI_ITIPOOBD 0xf1c 338 #define AI_ITIPOOBAOUT 0xf30 339 #define AI_ITIPOOBBOUT 0xf34 340 #define AI_ITIPOOBCOUT 0xf38 341 #define AI_ITIPOOBDOUT 0xf3c 342 #define AI_ITOPOOBA 0xf50 343 #define AI_ITOPOOBB 0xf54 344 #define AI_ITOPOOBC 0xf58 345 #define AI_ITOPOOBD 0xf5c 346 #define AI_ITOPOOBAIN 0xf70 347 #define AI_ITOPOOBBIN 0xf74 348 #define AI_ITOPOOBCIN 0xf78 349 #define AI_ITOPOOBDIN 0xf7c 350 #define AI_ITOPRESET 0xf90 351 #define AI_PERIPHERIALID4 0xfd0 352 #define AI_PERIPHERIALID5 0xfd4 353 #define AI_PERIPHERIALID6 0xfd8 354 #define AI_PERIPHERIALID7 0xfdc 355 #define AI_PERIPHERIALID0 0xfe0 356 #define AI_PERIPHERIALID1 0xfe4 357 #define AI_PERIPHERIALID2 0xfe8 358 #define AI_PERIPHERIALID3 0xfec 359 #define AI_COMPONENTID0 0xff0 360 #define AI_COMPONENTID1 0xff4 361 #define AI_COMPONENTID2 0xff8 362 #define AI_COMPONENTID3 0xffc 363 364 /* resetctrl */ 365 #define AIRC_RESET 1 366 367 /* errlogctrl */ 368 #define AIELC_TO_EXP_MASK 0x0000001f0 /* backplane timeout exponent */ 369 #define AIELC_TO_EXP_SHIFT 4 370 #define AIELC_TO_ENAB_SHIFT 9 /* backplane timeout enable */ 371 372 /* errlogdone */ 373 #define AIELD_ERRDONE_MASK 0x3 374 375 /* errlogstatus */ 376 #define AIELS_SLAVE_ERR 0x1 377 #define AIELS_TIMEOUT 0x2 378 #define AIELS_DECODE 0x3 379 #define AIELS_TIMEOUT_MASK 0x3 380 381 /* errorlog status bit map, for SW use */ 382 #define AXI_WRAP_STS_NONE (0) 383 #define AXI_WRAP_STS_TIMEOUT (1<<0) 384 #define AXI_WRAP_STS_SLAVE_ERR (1<<1) 385 #define AXI_WRAP_STS_DECODE_ERR (1<<2) 386 #define AXI_WRAP_STS_PCI_RD_ERR (1<<3) 387 #define AXI_WRAP_STS_WRAP_RD_ERR (1<<4) 388 #define AXI_WRAP_STS_SET_CORE_FAIL (1<<5) 389 390 /* errlogFrags */ 391 #define AXI_ERRLOG_FLAGS_WRITE_REQ (1<<24) 392 393 /* config */ 394 #define AICFG_OOB 0x00000020 395 #define AICFG_IOS 0x00000010 396 #define AICFG_IOC 0x00000008 397 #define AICFG_TO 0x00000004 398 #define AICFG_ERRL 0x00000002 399 #define AICFG_RST 0x00000001 400 401 /* bit defines for AI_OOBSELOUTB74 reg */ 402 #define OOB_SEL_OUTEN_B_5 15 403 #define OOB_SEL_OUTEN_B_6 23 404 405 /* AI_OOBSEL for A/B/C/D, 0-7 */ 406 #define AI_OOBSEL_MASK 0x1F 407 #define AI_OOBSEL_0_SHIFT 0 408 #define AI_OOBSEL_1_SHIFT 8 409 #define AI_OOBSEL_2_SHIFT 16 410 #define AI_OOBSEL_3_SHIFT 24 411 #define AI_OOBSEL_4_SHIFT 0 412 #define AI_OOBSEL_5_SHIFT 8 413 #define AI_OOBSEL_6_SHIFT 16 414 #define AI_OOBSEL_7_SHIFT 24 415 #define AI_IOCTRL_ENABLE_D11_PME (1 << 14) 416 417 /* bit Specific for AI_OOBSELOUTB30 */ 418 #define OOB_B_ALP_REQUEST 0 419 #define OOB_B_HT_REQUEST 1 420 #define OOB_B_ILP_REQUEST 2 421 #define OOB_B_ALP_AVAIL_REQUEST 3 422 #define OOB_B_HT_AVAIL_REQUEST 4 423 424 /* mask for interrupts from each core to wrapper */ 425 #define AI_OOBSELINA74_CORE_MASK 0x80808080 426 #define AI_OOBSELINA30_CORE_MASK 0x80808080 427 428 /* axi id mask in the error log id */ 429 #define AI_ERRLOGID_AXI_ID_MASK 0x07 430 431 #endif /* _AIDMP_H */ 432