1 /* 2 * Broadcom AMBA Interconnect definitions. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _AIDMP_H 25 #define _AIDMP_H 26 27 /* Manufacturer Ids */ 28 #define MFGID_ARM 0x43b 29 #define MFGID_BRCM 0x4bf 30 #define MFGID_MIPS 0x4a7 31 32 /* Component Classes */ 33 #define CC_SIM 0 34 #define CC_EROM 1 35 #define CC_CORESIGHT 9 36 #define CC_VERIF 0xb 37 #define CC_OPTIMO 0xd 38 #define CC_GEN 0xe 39 #define CC_PRIMECELL 0xf 40 41 /* Enumeration ROM registers */ 42 #define ER_EROMENTRY 0x000 43 #define ER_REMAPCONTROL 0xe00 44 #define ER_REMAPSELECT 0xe04 45 #define ER_MASTERSELECT 0xe10 46 #define ER_ITCR 0xf00 47 #define ER_ITIP 0xf04 48 49 /* Erom entries */ 50 #define ER_TAG 0xe 51 #define ER_TAG1 0x6 52 #define ER_VALID 1 53 #define ER_CI 0 54 #define ER_MP 2 55 #define ER_ADD 4 56 #define ER_END 0xe 57 #define ER_BAD 0xffffffff 58 #define ER_SZ_MAX 4096 /* 4KB */ 59 60 /* EROM CompIdentA */ 61 #define CIA_MFG_MASK 0xfff00000u 62 #define CIA_MFG_SHIFT 20u 63 #define CIA_CID_MASK 0x000fff00u 64 #define CIA_CID_SHIFT 8u 65 #define CIA_CCL_MASK 0x000000f0u 66 #define CIA_CCL_SHIFT 4u 67 68 /* EROM CompIdentB */ 69 #define CIB_REV_MASK 0xff000000u 70 #define CIB_REV_SHIFT 24u 71 #define CIB_NSW_MASK 0x00f80000u 72 #define CIB_NSW_SHIFT 19u 73 #define CIB_NMW_MASK 0x0007c000u 74 #define CIB_NMW_SHIFT 14u 75 #define CIB_NSP_MASK 0x00003e00u 76 #define CIB_NSP_SHIFT 9u 77 #define CIB_NMP_MASK 0x000001f0u 78 #define CIB_NMP_SHIFT 4u 79 80 /* EROM MasterPortDesc */ 81 #define MPD_MUI_MASK 0x0000ff00u 82 #define MPD_MUI_SHIFT 8u 83 #define MPD_MP_MASK 0x000000f0u 84 #define MPD_MP_SHIFT 4u 85 86 /* EROM AddrDesc */ 87 #define AD_ADDR_MASK 0xfffff000u 88 #define AD_SP_MASK 0x00000f00u 89 #define AD_SP_SHIFT 8u 90 #define AD_ST_MASK 0x000000c0u 91 #define AD_ST_SHIFT 6u 92 #define AD_ST_SLAVE 0x00000000u 93 #define AD_ST_BRIDGE 0x00000040u 94 #define AD_ST_SWRAP 0x00000080u 95 #define AD_ST_MWRAP 0x000000c0u 96 #define AD_SZ_MASK 0x00000030u 97 #define AD_SZ_SHIFT 4u 98 #define AD_SZ_4K 0x00000000u 99 #define AD_SZ_8K 0x00000010u 100 #define AD_SZ_16K 0x00000020u 101 #define AD_SZ_SZD 0x00000030u 102 #define AD_AG32 0x00000008u 103 #define AD_ADDR_ALIGN 0x00000fffu 104 #define AD_SZ_BASE 0x00001000u /* 4KB */ 105 106 /* EROM SizeDesc */ 107 #define SD_SZ_MASK 0xfffff000u 108 #define SD_SG32 0x00000008u 109 #define SD_SZ_ALIGN 0x00000fffu 110 111 #define WRAPPER_TIMEOUT_CONFIG 0x4u 112 113 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 114 115 typedef volatile struct _aidmp { 116 uint32 oobselina30; /* 0x000 */ 117 uint32 oobselina74; /* 0x004 */ 118 uint32 PAD[6]; 119 uint32 oobselinb30; /* 0x020 */ 120 uint32 oobselinb74; /* 0x024 */ 121 uint32 PAD[6]; 122 uint32 oobselinc30; /* 0x040 */ 123 uint32 oobselinc74; /* 0x044 */ 124 uint32 PAD[6]; 125 uint32 oobselind30; /* 0x060 */ 126 uint32 oobselind74; /* 0x064 */ 127 uint32 PAD[38]; 128 uint32 oobselouta30; /* 0x100 */ 129 uint32 oobselouta74; /* 0x104 */ 130 uint32 PAD[6]; 131 uint32 oobseloutb30; /* 0x120 */ 132 uint32 oobseloutb74; /* 0x124 */ 133 uint32 PAD[6]; 134 uint32 oobseloutc30; /* 0x140 */ 135 uint32 oobseloutc74; /* 0x144 */ 136 uint32 PAD[6]; 137 uint32 oobseloutd30; /* 0x160 */ 138 uint32 oobseloutd74; /* 0x164 */ 139 uint32 PAD[38]; 140 uint32 oobsynca; /* 0x200 */ 141 uint32 oobseloutaen; /* 0x204 */ 142 uint32 PAD[6]; 143 uint32 oobsyncb; /* 0x220 */ 144 uint32 oobseloutben; /* 0x224 */ 145 uint32 PAD[6]; 146 uint32 oobsyncc; /* 0x240 */ 147 uint32 oobseloutcen; /* 0x244 */ 148 uint32 PAD[6]; 149 uint32 oobsyncd; /* 0x260 */ 150 uint32 oobseloutden; /* 0x264 */ 151 uint32 PAD[38]; 152 uint32 oobaextwidth; /* 0x300 */ 153 uint32 oobainwidth; /* 0x304 */ 154 uint32 oobaoutwidth; /* 0x308 */ 155 uint32 PAD[5]; 156 uint32 oobbextwidth; /* 0x320 */ 157 uint32 oobbinwidth; /* 0x324 */ 158 uint32 oobboutwidth; /* 0x328 */ 159 uint32 PAD[5]; 160 uint32 oobcextwidth; /* 0x340 */ 161 uint32 oobcinwidth; /* 0x344 */ 162 uint32 oobcoutwidth; /* 0x348 */ 163 uint32 PAD[5]; 164 uint32 oobdextwidth; /* 0x360 */ 165 uint32 oobdinwidth; /* 0x364 */ 166 uint32 oobdoutwidth; /* 0x368 */ 167 uint32 PAD[37]; 168 uint32 ioctrlset; /* 0x400 */ 169 uint32 ioctrlclear; /* 0x404 */ 170 uint32 ioctrl; /* 0x408 */ 171 uint32 PAD[61]; 172 uint32 iostatus; /* 0x500 */ 173 uint32 PAD[127]; 174 uint32 ioctrlwidth; /* 0x700 */ 175 uint32 iostatuswidth; /* 0x704 */ 176 uint32 PAD[62]; 177 uint32 resetctrl; /* 0x800 */ 178 uint32 resetstatus; /* 0x804 */ 179 uint32 resetreadid; /* 0x808 */ 180 uint32 resetwriteid; /* 0x80c */ 181 uint32 PAD[60]; 182 uint32 errlogctrl; /* 0x900 */ 183 uint32 errlogdone; /* 0x904 */ 184 uint32 errlogstatus; /* 0x908 */ 185 uint32 errlogaddrlo; /* 0x90c */ 186 uint32 errlogaddrhi; /* 0x910 */ 187 uint32 errlogid; /* 0x914 */ 188 uint32 errloguser; /* 0x918 */ 189 uint32 errlogflags; /* 0x91c */ 190 uint32 PAD[56]; 191 uint32 intstatus; /* 0xa00 */ 192 uint32 PAD[255]; 193 uint32 config; /* 0xe00 */ 194 uint32 PAD[63]; 195 uint32 itcr; /* 0xf00 */ 196 uint32 PAD[3]; 197 uint32 itipooba; /* 0xf10 */ 198 uint32 itipoobb; /* 0xf14 */ 199 uint32 itipoobc; /* 0xf18 */ 200 uint32 itipoobd; /* 0xf1c */ 201 uint32 PAD[4]; 202 uint32 itipoobaout; /* 0xf30 */ 203 uint32 itipoobbout; /* 0xf34 */ 204 uint32 itipoobcout; /* 0xf38 */ 205 uint32 itipoobdout; /* 0xf3c */ 206 uint32 PAD[4]; 207 uint32 itopooba; /* 0xf50 */ 208 uint32 itopoobb; /* 0xf54 */ 209 uint32 itopoobc; /* 0xf58 */ 210 uint32 itopoobd; /* 0xf5c */ 211 uint32 PAD[4]; 212 uint32 itopoobain; /* 0xf70 */ 213 uint32 itopoobbin; /* 0xf74 */ 214 uint32 itopoobcin; /* 0xf78 */ 215 uint32 itopoobdin; /* 0xf7c */ 216 uint32 PAD[4]; 217 uint32 itopreset; /* 0xf90 */ 218 uint32 PAD[15]; 219 uint32 peripherialid4; /* 0xfd0 */ 220 uint32 peripherialid5; /* 0xfd4 */ 221 uint32 peripherialid6; /* 0xfd8 */ 222 uint32 peripherialid7; /* 0xfdc */ 223 uint32 peripherialid0; /* 0xfe0 */ 224 uint32 peripherialid1; /* 0xfe4 */ 225 uint32 peripherialid2; /* 0xfe8 */ 226 uint32 peripherialid3; /* 0xfec */ 227 uint32 componentid0; /* 0xff0 */ 228 uint32 componentid1; /* 0xff4 */ 229 uint32 componentid2; /* 0xff8 */ 230 uint32 componentid3; /* 0xffc */ 231 } aidmp_t; 232 233 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ 234 235 /* Out-of-band Router registers */ 236 #define OOB_BUSCONFIG 0x020 237 #define OOB_STATUSA 0x100 238 #define OOB_STATUSB 0x104 239 #define OOB_STATUSC 0x108 240 #define OOB_STATUSD 0x10c 241 #define OOB_ENABLEA0 0x200 242 #define OOB_ENABLEA1 0x204 243 #define OOB_ENABLEA2 0x208 244 #define OOB_ENABLEA3 0x20c 245 #define OOB_ENABLEB0 0x280 246 #define OOB_ENABLEB1 0x284 247 #define OOB_ENABLEB2 0x288 248 #define OOB_ENABLEB3 0x28c 249 #define OOB_ENABLEC0 0x300 250 #define OOB_ENABLEC1 0x304 251 #define OOB_ENABLEC2 0x308 252 #define OOB_ENABLEC3 0x30c 253 #define OOB_ENABLED0 0x380 254 #define OOB_ENABLED1 0x384 255 #define OOB_ENABLED2 0x388 256 #define OOB_ENABLED3 0x38c 257 #define OOB_ITCR 0xf00 258 #define OOB_ITIPOOBA 0xf10 259 #define OOB_ITIPOOBB 0xf14 260 #define OOB_ITIPOOBC 0xf18 261 #define OOB_ITIPOOBD 0xf1c 262 #define OOB_ITOPOOBA 0xf30 263 #define OOB_ITOPOOBB 0xf34 264 #define OOB_ITOPOOBC 0xf38 265 #define OOB_ITOPOOBD 0xf3c 266 267 /* DMP wrapper registers */ 268 #define AI_OOBSELINA30 0x000 269 #define AI_OOBSELINA74 0x004 270 #define AI_OOBSELINB30 0x020 271 #define AI_OOBSELINB74 0x024 272 #define AI_OOBSELINC30 0x040 273 #define AI_OOBSELINC74 0x044 274 #define AI_OOBSELIND30 0x060 275 #define AI_OOBSELIND74 0x064 276 #define AI_OOBSELOUTA30 0x100 277 #define AI_OOBSELOUTA74 0x104 278 #define AI_OOBSELOUTB30 0x120 279 #define AI_OOBSELOUTB74 0x124 280 #define AI_OOBSELOUTC30 0x140 281 #define AI_OOBSELOUTC74 0x144 282 #define AI_OOBSELOUTD30 0x160 283 #define AI_OOBSELOUTD74 0x164 284 #define AI_OOBSYNCA 0x200 285 #define AI_OOBSELOUTAEN 0x204 286 #define AI_OOBSYNCB 0x220 287 #define AI_OOBSELOUTBEN 0x224 288 #define AI_OOBSYNCC 0x240 289 #define AI_OOBSELOUTCEN 0x244 290 #define AI_OOBSYNCD 0x260 291 #define AI_OOBSELOUTDEN 0x264 292 #define AI_OOBAEXTWIDTH 0x300 293 #define AI_OOBAINWIDTH 0x304 294 #define AI_OOBAOUTWIDTH 0x308 295 #define AI_OOBBEXTWIDTH 0x320 296 #define AI_OOBBINWIDTH 0x324 297 #define AI_OOBBOUTWIDTH 0x328 298 #define AI_OOBCEXTWIDTH 0x340 299 #define AI_OOBCINWIDTH 0x344 300 #define AI_OOBCOUTWIDTH 0x348 301 #define AI_OOBDEXTWIDTH 0x360 302 #define AI_OOBDINWIDTH 0x364 303 #define AI_OOBDOUTWIDTH 0x368 304 305 #if !defined(IL_BIGENDIAN) 306 #define AI_IOCTRLSET 0x400 307 #define AI_IOCTRLCLEAR 0x404 308 #define AI_IOCTRL 0x408 309 #define AI_IOCTRL_BOOKER 0x248 /* Starting from OOBR base - 0x18006000 */ 310 #define AI_IOSTATUS 0x500 311 #define AI_RESETCTRL 0x800 312 #define AI_RESETSTATUS 0x804 313 #endif /* IL_BIGENDIAN */ 314 315 #define AI_IOCTRLWIDTH 0x700 316 #define AI_IOSTATUSWIDTH 0x704 317 318 #define AI_RESETREADID 0x808 319 #define AI_RESETWRITEID 0x80c 320 #define AI_ERRLOGCTRL 0x900 321 #define AI_ERRLOGDONE 0x904 322 #define AI_ERRLOGSTATUS 0x908 323 #define AI_ERRLOGADDRLO 0x90c 324 #define AI_ERRLOGADDRHI 0x910 325 #define AI_ERRLOGID 0x914 326 #define AI_ERRLOGUSER 0x918 327 #define AI_ERRLOGFLAGS 0x91c 328 #define AI_INTSTATUS 0xa00 329 #define AI_CONFIG 0xe00 330 #define AI_ITCR 0xf00 331 #define AI_ITIPOOBA 0xf10 332 #define AI_ITIPOOBB 0xf14 333 #define AI_ITIPOOBC 0xf18 334 #define AI_ITIPOOBD 0xf1c 335 #define AI_ITIPOOBAOUT 0xf30 336 #define AI_ITIPOOBBOUT 0xf34 337 #define AI_ITIPOOBCOUT 0xf38 338 #define AI_ITIPOOBDOUT 0xf3c 339 #define AI_ITOPOOBA 0xf50 340 #define AI_ITOPOOBB 0xf54 341 #define AI_ITOPOOBC 0xf58 342 #define AI_ITOPOOBD 0xf5c 343 #define AI_ITOPOOBAIN 0xf70 344 #define AI_ITOPOOBBIN 0xf74 345 #define AI_ITOPOOBCIN 0xf78 346 #define AI_ITOPOOBDIN 0xf7c 347 #define AI_ITOPRESET 0xf90 348 #define AI_PERIPHERIALID4 0xfd0 349 #define AI_PERIPHERIALID5 0xfd4 350 #define AI_PERIPHERIALID6 0xfd8 351 #define AI_PERIPHERIALID7 0xfdc 352 #define AI_PERIPHERIALID0 0xfe0 353 #define AI_PERIPHERIALID1 0xfe4 354 #define AI_PERIPHERIALID2 0xfe8 355 #define AI_PERIPHERIALID3 0xfec 356 #define AI_COMPONENTID0 0xff0 357 #define AI_COMPONENTID1 0xff4 358 #define AI_COMPONENTID2 0xff8 359 #define AI_COMPONENTID3 0xffc 360 361 /* resetctrl */ 362 #define AIRC_RESET 1 363 364 /* errlogctrl */ 365 #define AIELC_TO_EXP_MASK 0x0000001f0 /* backplane timeout exponent */ 366 #define AIELC_TO_EXP_SHIFT 4 367 #define AIELC_TO_ENAB_SHIFT 9 /* backplane timeout enable */ 368 369 /* errlogdone */ 370 #define AIELD_ERRDONE_MASK 0x3 371 372 /* errlogstatus */ 373 #define AIELS_SLAVE_ERR 0x1 374 #define AIELS_TIMEOUT 0x2 375 #define AIELS_DECODE 0x3 376 #define AIELS_ERROR_MASK 0x3 377 #define AIELS_MULTIPLE_ERRORS 0x4 378 #define ERRLOGID_AXIID_MASK 0xF 379 380 /* errorlog status bit map, for SW use */ 381 #define AXI_WRAP_STS_NONE (0) 382 #define AXI_WRAP_STS_TIMEOUT (1<<0) 383 #define AXI_WRAP_STS_SLAVE_ERR (1<<1) 384 #define AXI_WRAP_STS_DECODE_ERR (1<<2) 385 #define AXI_WRAP_STS_PCI_RD_ERR (1<<3) 386 #define AXI_WRAP_STS_WRAP_RD_ERR (1<<4) 387 #define AXI_WRAP_STS_SET_CORE_FAIL (1<<5) 388 #define AXI_WRAP_STS_MULTIPLE_ERRORS (1<<6) 389 390 /* errlogFrags */ 391 #define AXI_ERRLOG_FLAGS_WRITE_REQ (1<<24) 392 393 /* config */ 394 #define AICFG_OOB 0x00000020 395 #define AICFG_IOS 0x00000010 396 #define AICFG_IOC 0x00000008 397 #define AICFG_TO 0x00000004 398 #define AICFG_ERRL 0x00000002 399 #define AICFG_RST 0x00000001 400 401 /* bit defines for AI_OOBSELOUTB74 reg */ 402 #define OOB_SEL_OUTEN_B_5 15 403 #define OOB_SEL_OUTEN_B_6 23 404 405 /* AI_OOBSEL for A/B/C/D, 0-7 */ 406 #define AI_OOBSEL_MASK 0x1F 407 #define AI_OOBSEL_0_SHIFT 0 408 #define AI_OOBSEL_1_SHIFT 8 409 #define AI_OOBSEL_2_SHIFT 16 410 #define AI_OOBSEL_3_SHIFT 24 411 #define AI_OOBSEL_4_SHIFT 0 412 #define AI_OOBSEL_5_SHIFT 8 413 #define AI_OOBSEL_6_SHIFT 16 414 #define AI_OOBSEL_7_SHIFT 24 415 #define AI_IOCTRL_ENABLE_D11_PME (1 << 14) 416 417 /* bit Specific for AI_OOBSELOUTB30 */ 418 #define OOB_B_ALP_REQUEST 0 419 #define OOB_B_HT_REQUEST 1 420 #define OOB_B_ILP_REQUEST 2 421 #define OOB_B_ALP_AVAIL_REQUEST 3 422 #define OOB_B_HT_AVAIL_REQUEST 4 423 424 /* mask for interrupts from each core to wrapper */ 425 #define AI_OOBSELINA74_CORE_MASK 0x80808080 426 #define AI_OOBSELINA30_CORE_MASK 0x80808080 427 428 #define AI_OOBSEL_30_0_INTR_MASK 0x00000080 429 #define AI_OOBSEL_30_3_INTR_MASK 0x80000000 430 431 #define AI_OOBSEL_74_4_INTR_MASK 0x00000080 432 #define AI_OOBSEL_74_7_INTR_MASK 0x80000000 433 434 /* axi id mask in the error log id */ 435 #define AI_ERRLOGID_AXI_ID_MASK 0x07 436 #define AI_ERRLOGID_AXI_ID_MASK_EXTD 0x1F 437 438 #endif /* _AIDMP_H */ 439