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Searched +full:0 +full:xa400 (Results 1 – 25 of 39) sorted by relevance

12

/OK3568_Linux_fs/u-boot/board/renesas/r2dplus/
H A Dlowlevel_init.S74 CCR_D_D: .long 0x0808 /* Flush the cache, disable */
75 CCR_D_E: .long 0x8000090B
78 FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
80 BCR1_D: .long 0x00180008
82 BCR2_D: .long 0xabe8
84 BCR3_D: .long 0x0000
86 BCR4_D: .long 0x00000010
88 WCR1_D: .long 0x33343333
90 WCR2_D: .long 0xcff86fbf
92 WCR3_D: .long 0x07777707
[all …]
/OK3568_Linux_fs/kernel/drivers/net/mdio/
H A Dmdio-mvusb.c9 #define USB_MARVELL_VID 0x1286
12 { USB_DEVICE(USB_MARVELL_VID, 0x1fa4) },
40 mvusb->buf[MVUSB_CMD_ADDR] = cpu_to_le16(0xa400 | (dev << 5) | reg); in mvusb_mdio_read()
63 mvusb->buf[MVUSB_CMD_ADDR] = cpu_to_le16(0x8000 | (dev << 5) | reg); in mvusb_mdio_write()
86 mvusb->buf[MVUSB_CMD_PREAMBLE0] = cpu_to_le16(0xe800); in mvusb_mdio_probe()
87 mvusb->buf[MVUSB_CMD_PREAMBLE1] = cpu_to_le16(0x0001); in mvusb_mdio_probe()
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dstv6111.c46 { 2572, 0 },
82 { 1548, 0 },
118 { 4870, 0x3000 },
119 { 4850, 0x3C00 },
120 { 4800, 0x4500 },
121 { 4750, 0x4800 },
122 { 4700, 0x4B00 },
123 { 4650, 0x4D00 },
124 { 4600, 0x4F00 },
125 { 4550, 0x5100 },
[all …]
H A Dmxl5xx_regs.h23 #define HYDRA_INTR_STATUS_REG 0x80030008
24 #define HYDRA_INTR_MASK_REG 0x8003000C
26 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
27 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
29 #define HYDRA_CPU_RESET_REG 0x8003003C
30 #define HYDRA_CPU_RESET_DATA 0x00000400
32 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
33 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
35 #define HYDRA_RESET_BBAND_REG 0x80030024
36 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_dbgdev.h37 CONTEXT_REG_BASE = 0xA000,
38 CONTEXT_REG_END = 0xA400,
44 USERCONFIG_REG_BASE = 0xC000,
45 USERCONFIG_REG_END = 0x10000,
51 AMD_CONFIG_REG_BASE = 0x2000, /* in dwords */
52 AMD_CONFIG_REG_END = 0x2B00,
58 SH_REG_BASE = 0x2C00,
59 SH_REG_END = 0x3000,
64 #define SQ_CMD 0x8DEC
67 SQ_IND_CMD_CMD_NULL = 0x00000000,
[all …]
/OK3568_Linux_fs/u-boot/board/ms7750se/
H A Dlowlevel_init.S18 #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
19 #define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
21 #define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
24 #define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
27 #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
28 A2: 1-3 A1: 1-3 A0: 0-1 */
29 #define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
30 #define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
31 #define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
32 #define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dqcom,qmp-usb3-dp-phy.yaml81 "^usb3-phy@[0-9a-f]+$":
109 const: 0
112 const: 0
121 "^dp-phy@[0-9a-f]+$":
139 const: 0
167 reg = <0x088e9000 0x18c>,
168 <0x088e8000 0x10>,
169 <0x088ea000 0x40>;
174 ranges = <0x0 0x088e9000 0x2000>;
190 reg = <0x200 0x128>,
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/octeon/
H A Dcvmx-ciu-defs.h13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
16 #define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17 #define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18 #define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19 #define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20 #define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21 #define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22 #define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23 #define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24 #define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/ap325rxa/
H A Dcpld-ap325rxa.c29 #define SCIF_BASE 0xffe00000 /* SCIF0 */
30 #define SCSMR (vu_short *)(SCIF_BASE + 0x00)
31 #define SCBRR (vu_char *)(SCIF_BASE + 0x04)
32 #define SCSCR (vu_short *)(SCIF_BASE + 0x08)
33 #define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
34 #define SC_SR (vu_short *)(SCIF_BASE + 0x10)
35 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
36 #define RFCR (vu_long *)0xFE400020
38 #define SCSCR_INIT 0x0038
39 #define SCSCR_CLR 0x0000
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
398 base = of_iomap(np, 0); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
407 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
H A Dclk-imx8mm.c309 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
318 base = of_iomap(np, 0); in imx8mm_clocks_probe()
323 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
324 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
325 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
326 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
327 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
328 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
329 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
330 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
H A Dclk-imx8mq.c291 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
301 base = of_iomap(np, 0); in imx8mq_clocks_probe()
306 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
307 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
308 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
309 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
310 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
311 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe()
312 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
313 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
[all …]
H A Dclk-imx8mp.c424 anatop_base = of_iomap(np, 0); in imx8mp_clocks_probe()
430 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
445 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
453 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe()
454 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe()
455 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe()
456 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe()
457 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe()
458 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe()
459 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe()
[all …]
/OK3568_Linux_fs/kernel/arch/c6x/platforms/
H A Dcache.c16 #define IMCR_CCFG 0x0000
17 #define IMCR_L1PCFG 0x0020
18 #define IMCR_L1PCC 0x0024
19 #define IMCR_L1DCFG 0x0040
20 #define IMCR_L1DCC 0x0044
21 #define IMCR_L2ALLOC0 0x2000
22 #define IMCR_L2ALLOC1 0x2004
23 #define IMCR_L2ALLOC2 0x2008
24 #define IMCR_L2ALLOC3 0x200c
25 #define IMCR_L2WBAR 0x4000
[all …]
/OK3568_Linux_fs/kernel/drivers/media/usb/dvb-usb/
H A Daf9005.c26 module_param_named(dump_eeprom, dvb_usb_af9005_dump_eeprom, int, 0);
37 u8 regmask[8] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff };
62 st->data[0] = 14; /* rest of buffer length low */ in af9005_generic_read_write()
63 st->data[1] = 0; /* rest of buffer length high */ in af9005_generic_read_write()
71 st->data[6] = (u8) (reg & 0xff); in af9005_generic_read_write()
84 for (i = 0; i < len; i++) in af9005_generic_read_write()
88 st->data[8] = values[0]; in af9005_generic_read_write()
91 ret = dvb_usb_generic_rw(d, st->data, 16, st->data, 17, 0); in af9005_generic_read_write()
101 if (st->data[3] != 0x0d) { in af9005_generic_read_write()
118 if (st->data[16] != 0x01) { in af9005_generic_read_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43legacy/
H A Dilt.c23 0xFEB93FFD, 0xFEC63FFD, /* 0 */
24 0xFED23FFD, 0xFEDF3FFD,
25 0xFEEC3FFE, 0xFEF83FFE,
26 0xFF053FFE, 0xFF113FFE,
27 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
28 0xFF373FFF, 0xFF443FFF,
29 0xFF503FFF, 0xFF5D3FFF,
30 0xFF693FFF, 0xFF763FFF,
31 0xFF824000, 0xFF8F4000, /* 16 */
32 0xFF9B4000, 0xFFA84000,
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/eth/
H A Dr8152.h13 #define PLA_IDR 0xc000
14 #define PLA_RCR 0xc010
15 #define PLA_RMS 0xc016
16 #define PLA_RXFIFO_CTRL0 0xc0a0
17 #define PLA_RXFIFO_CTRL1 0xc0a4
18 #define PLA_RXFIFO_CTRL2 0xc0a8
19 #define PLA_DMY_REG0 0xc0b0
20 #define PLA_FMC 0xc0b4
21 #define PLA_CFG_WOL 0xc0b6
22 #define PLA_TEREDO_CFG 0xc0bc
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dstm32mp157-pinctrl.dtsi14 ranges = <0 0x50002000 0xa400>;
16 st,syscfg = <&exti 0x60 0xff>;
24 reg = <0x0 0x400>;
28 gpio-ranges = <&pinctrl 0 0 16>;
36 reg = <0x1000 0x400>;
40 gpio-ranges = <&pinctrl 0 16 16>;
48 reg = <0x2000 0x400>;
52 gpio-ranges = <&pinctrl 0 32 16>;
60 reg = <0x3000 0x400>;
64 gpio-ranges = <&pinctrl 0 48 16>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/OK3568_Linux_fs/kernel/Documentation/networking/device_drivers/ethernet/3com/
H A Dvortex.rst91 Where N is a number from 0 to 7. Anything above 3 produces a lot
98 them with option 0x204 you would use::
100 options=0x204,0x204
108 0 10baseT
125 0x8000 Set driver debugging level to 7
126 0x4000 Set driver debugging level to 2
127 0x0400 Enable Wake-on-LAN
128 0x0200 Force full duplex mode.
129 0x0010 Bus-master enable bit (Old Vortex cards only)
134 insmod 3c59x options=0x204
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h13 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
14 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
15 0x8400, 0x840b,
19 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
20 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
21 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
22 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
26 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
27 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
31 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/
H A Dtables.c21 0xFEB93FFD, 0xFEC63FFD, /* 0 */
22 0xFED23FFD, 0xFEDF3FFD,
23 0xFEEC3FFE, 0xFEF83FFE,
24 0xFF053FFE, 0xFF113FFE,
25 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
26 0xFF373FFF, 0xFF443FFF,
27 0xFF503FFF, 0xFF5D3FFF,
28 0xFF693FFF, 0xFF763FFF,
29 0xFF824000, 0xFF8F4000, /* 16 */
30 0xFF9B4000, 0xFFA84000,
[all …]
/OK3568_Linux_fs/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dar0822.c7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 support conversion gain switch.
9 * V0.0X01.0X02 add debug interface for conversion gain switch.
10 * V0.0X01.0X03 support enum sensor fmt
11 * V0.0X01.0X04 add quick stream on/off
34 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
50 #define CHIP_ID 0x0F56
51 #define AR0822_REG_CHIP_ID 0x3000
53 #define AR0822_REG_CTRL_MODE 0x301A
54 #define AR0822_MODE_SW_STANDBY 0x0018
[all …]
/OK3568_Linux_fs/kernel/sound/pci/vx222/
H A Dvx222_ops.c23 [VX_ICR] = 0x00,
24 [VX_CVR] = 0x04,
25 [VX_ISR] = 0x08,
26 [VX_IVR] = 0x0c,
27 [VX_RXH] = 0x14,
28 [VX_RXM] = 0x18,
29 [VX_RXL] = 0x1c,
30 [VX_DMA] = 0x10,
31 [VX_CDSP] = 0x20,
32 [VX_CFG] = 0x24,
[all …]

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