xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/stm32mp157-pinctrl.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8/ {
9	soc {
10		pinctrl: pin-controller@50002000 {
11			#address-cells = <1>;
12			#size-cells = <1>;
13			compatible = "st,stm32mp157-pinctrl";
14			ranges = <0 0x50002000 0xa400>;
15			interrupt-parent = <&exti>;
16			st,syscfg = <&exti 0x60 0xff>;
17			pins-are-numbered;
18
19			gpioa: gpio@50002000 {
20				gpio-controller;
21				#gpio-cells = <2>;
22				interrupt-controller;
23				#interrupt-cells = <2>;
24				reg = <0x0 0x400>;
25				clocks = <&rcc GPIOA>;
26				st,bank-name = "GPIOA";
27				ngpios = <16>;
28				gpio-ranges = <&pinctrl 0 0 16>;
29			};
30
31			gpiob: gpio@50003000 {
32				gpio-controller;
33				#gpio-cells = <2>;
34				interrupt-controller;
35				#interrupt-cells = <2>;
36				reg = <0x1000 0x400>;
37				clocks = <&rcc GPIOB>;
38				st,bank-name = "GPIOB";
39				ngpios = <16>;
40				gpio-ranges = <&pinctrl 0 16 16>;
41			};
42
43			gpioc: gpio@50004000 {
44				gpio-controller;
45				#gpio-cells = <2>;
46				interrupt-controller;
47				#interrupt-cells = <2>;
48				reg = <0x2000 0x400>;
49				clocks = <&rcc GPIOC>;
50				st,bank-name = "GPIOC";
51				ngpios = <16>;
52				gpio-ranges = <&pinctrl 0 32 16>;
53			};
54
55			gpiod: gpio@50005000 {
56				gpio-controller;
57				#gpio-cells = <2>;
58				interrupt-controller;
59				#interrupt-cells = <2>;
60				reg = <0x3000 0x400>;
61				clocks = <&rcc GPIOD>;
62				st,bank-name = "GPIOD";
63				ngpios = <16>;
64				gpio-ranges = <&pinctrl 0 48 16>;
65			};
66
67			gpioe: gpio@50006000 {
68				gpio-controller;
69				#gpio-cells = <2>;
70				interrupt-controller;
71				#interrupt-cells = <2>;
72				reg = <0x4000 0x400>;
73				clocks = <&rcc GPIOE>;
74				st,bank-name = "GPIOE";
75				ngpios = <16>;
76				gpio-ranges = <&pinctrl 0 64 16>;
77			};
78
79			gpiof: gpio@50007000 {
80				gpio-controller;
81				#gpio-cells = <2>;
82				interrupt-controller;
83				#interrupt-cells = <2>;
84				reg = <0x5000 0x400>;
85				clocks = <&rcc GPIOF>;
86				st,bank-name = "GPIOF";
87				ngpios = <16>;
88				gpio-ranges = <&pinctrl 0 80 16>;
89			};
90
91			gpiog: gpio@50008000 {
92				gpio-controller;
93				#gpio-cells = <2>;
94				interrupt-controller;
95				#interrupt-cells = <2>;
96				reg = <0x6000 0x400>;
97				clocks = <&rcc GPIOG>;
98				st,bank-name = "GPIOG";
99				ngpios = <16>;
100				gpio-ranges = <&pinctrl 0 96 16>;
101			};
102
103			gpioh: gpio@50009000 {
104				gpio-controller;
105				#gpio-cells = <2>;
106				interrupt-controller;
107				#interrupt-cells = <2>;
108				reg = <0x7000 0x400>;
109				clocks = <&rcc GPIOH>;
110				st,bank-name = "GPIOH";
111				ngpios = <16>;
112				gpio-ranges = <&pinctrl 0 112 16>;
113			};
114
115			gpioi: gpio@5000a000 {
116				gpio-controller;
117				#gpio-cells = <2>;
118				interrupt-controller;
119				#interrupt-cells = <2>;
120				reg = <0x8000 0x400>;
121				clocks = <&rcc GPIOI>;
122				st,bank-name = "GPIOI";
123				ngpios = <16>;
124				gpio-ranges = <&pinctrl 0 128 16>;
125			};
126
127			gpioj: gpio@5000b000 {
128				gpio-controller;
129				#gpio-cells = <2>;
130				interrupt-controller;
131				#interrupt-cells = <2>;
132				reg = <0x9000 0x400>;
133				clocks = <&rcc GPIOJ>;
134				st,bank-name = "GPIOJ";
135				ngpios = <16>;
136				gpio-ranges = <&pinctrl 0 144 16>;
137			};
138
139			gpiok: gpio@5000c000 {
140				gpio-controller;
141				#gpio-cells = <2>;
142				interrupt-controller;
143				#interrupt-cells = <2>;
144				reg = <0xa000 0x400>;
145				clocks = <&rcc GPIOK>;
146				st,bank-name = "GPIOK";
147				ngpios = <8>;
148				gpio-ranges = <&pinctrl 0 160 8>;
149			};
150
151			adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
152				pins {
153					pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
154						 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
155				};
156			};
157
158			cec_pins_a: cec-0 {
159				pins {
160					pinmux = <STM32_PINMUX('A', 15, AF4)>;
161					bias-disable;
162					drive-open-drain;
163					slew-rate = <0>;
164				};
165			};
166
167			ethernet0_rgmii_pins_a: rgmii-0 {
168				pins1 {
169					pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
170						 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
171						 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
172						 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
173						 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
174						 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
175						 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
176						 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
177						 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
178					bias-disable;
179					drive-push-pull;
180					slew-rate = <3>;
181				};
182				pins2 {
183					pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
184						 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
185						 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
186						 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
187						 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
188						 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
189					bias-disable;
190				};
191			};
192
193			ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
194				pins1 {
195					pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
196						 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
197						 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
198						 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
199						 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
200						 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
201						 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
202						 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
203						 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
204						 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
205						 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
206						 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
207						 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
208						 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
209						 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
210				};
211			};
212
213			i2c1_pins_a: i2c1-0 {
214				pins {
215					pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
216						 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
217					bias-disable;
218					drive-open-drain;
219					slew-rate = <0>;
220				};
221			};
222
223			i2c2_pins_a: i2c2-0 {
224				pins {
225					pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
226						 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
227					bias-disable;
228					drive-open-drain;
229					slew-rate = <0>;
230				};
231			};
232
233			i2c5_pins_a: i2c5-0 {
234				pins {
235					pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
236						 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
237					bias-disable;
238					drive-open-drain;
239					slew-rate = <0>;
240				};
241			};
242
243			m_can1_pins_a: m-can1-0 {
244				pins1 {
245					pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
246					slew-rate = <1>;
247					drive-push-pull;
248					bias-disable;
249				};
250				pins2 {
251					pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
252					bias-disable;
253				};
254			};
255
256			pwm2_pins_a: pwm2-0 {
257				pins {
258					pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
259					bias-pull-down;
260					drive-push-pull;
261					slew-rate = <0>;
262				};
263			};
264
265			pwm8_pins_a: pwm8-0 {
266				pins {
267					pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
268					bias-pull-down;
269					drive-push-pull;
270					slew-rate = <0>;
271				};
272			};
273
274			pwm12_pins_a: pwm12-0 {
275				pins {
276					pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
277					bias-pull-down;
278					drive-push-pull;
279					slew-rate = <0>;
280				};
281			};
282
283			qspi_clk_pins_a: qspi-clk-0 {
284				pins {
285					pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
286					bias-disable;
287					drive-push-pull;
288					slew-rate = <3>;
289				};
290			};
291
292			qspi_bk1_pins_a: qspi-bk1-0 {
293				pins1 {
294					pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
295						 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
296						 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
297						 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
298					bias-disable;
299					drive-push-pull;
300					slew-rate = <3>;
301				};
302				pins2 {
303					pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
304					bias-pull-up;
305					drive-push-pull;
306					slew-rate = <3>;
307				};
308			};
309
310			qspi_bk2_pins_a: qspi-bk2-0 {
311				pins1 {
312					pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
313						 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
314						 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
315						 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
316					bias-disable;
317					drive-push-pull;
318					slew-rate = <3>;
319				};
320				pins2 {
321					pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
322					bias-pull-up;
323					drive-push-pull;
324					slew-rate = <3>;
325				};
326			};
327			sdmmc1_b4_pins_a: sdmmc1-b4@0 {
328				pins {
329					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
330						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
331						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
332						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
333						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
334						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
335					slew-rate = <3>;
336					drive-push-pull;
337					bias-disable;
338				};
339			};
340
341			sdmmc1_dir_pins_a: sdmmc1-dir@0 {
342				pins {
343					pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
344						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
345						 <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
346						 <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
347					slew-rate = <3>;
348					drive-push-pull;
349					bias-pull-up;
350				};
351			};
352			sdmmc2_b4_pins_a: sdmmc2-b4@0 {
353				pins {
354					pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
355						 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
356						 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
357						 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
358						 <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
359						 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
360					slew-rate = <3>;
361					drive-push-pull;
362					bias-pull-up;
363				};
364			};
365
366			sdmmc2_d47_pins_a: sdmmc2-d47@0 {
367				pins {
368					pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
369						 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
370						 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
371						 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
372					slew-rate = <3>;
373					drive-push-pull;
374					bias-pull-up;
375				};
376			};
377
378			stusb1600_pins_a: stusb1600-0 {
379				pins {
380					pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
381					bias-pull-up;
382				};
383			};
384
385			uart4_pins_a: uart4-0 {
386				pins1 {
387					pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
388					bias-disable;
389					drive-push-pull;
390					slew-rate = <0>;
391				};
392				pins2 {
393					pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
394					bias-disable;
395				};
396			};
397
398			usbotg_hs_pins_a: usbotg_hs-0 {
399				pins {
400					pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
401				};
402			};
403		};
404
405		pinctrl_z: pin-controller-z@54004000 {
406			#address-cells = <1>;
407			#size-cells = <1>;
408			compatible = "st,stm32mp157-z-pinctrl";
409			ranges = <0 0x54004000 0x400>;
410			pins-are-numbered;
411			interrupt-parent = <&exti>;
412			st,syscfg = <&exti 0x60 0xff>;
413
414			gpioz: gpio@54004000 {
415				gpio-controller;
416				#gpio-cells = <2>;
417				interrupt-controller;
418				#interrupt-cells = <2>;
419				reg = <0 0x400>;
420				clocks = <&rcc GPIOZ>;
421				st,bank-name = "GPIOZ";
422				st,bank-ioport = <11>;
423				ngpios = <8>;
424				gpio-ranges = <&pinctrl_z 0 400 8>;
425			};
426
427			i2c4_pins_a: i2c4-0 {
428				pins {
429					pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
430						 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
431					bias-disable;
432					drive-open-drain;
433					slew-rate = <0>;
434				};
435			};
436
437			spi1_pins_a: spi1-0 {
438				pins1 {
439					pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
440						 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
441					bias-disable;
442					drive-push-pull;
443					slew-rate = <1>;
444				};
445
446				pins2 {
447					pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
448					bias-disable;
449				};
450			};
451		};
452	};
453};
454