1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun modified from SH-IPL+g 3*4882a593Smuzhiyun Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun*/ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include <config.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#include <asm/processor.h> 15*4882a593Smuzhiyun#include <asm/macro.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun#ifdef CONFIG_CPU_SH7751 18*4882a593Smuzhiyun#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ 19*4882a593Smuzhiyun#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ 20*4882a593Smuzhiyun#ifdef CONFIG_MARUBUN_PCCARD 21*4882a593Smuzhiyun#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 22*4882a593Smuzhiyun A3:2 A2:15 A1:15 A0:6 A0B:7 */ 23*4882a593Smuzhiyun#else /* CONFIG_MARUBUN_PCCARD */ 24*4882a593Smuzhiyun#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 25*4882a593Smuzhiyun A3:2 A2:15 A1:15 A0:6 A0B:7 */ 26*4882a593Smuzhiyun#endif /* CONFIG_MARUBUN_PCCARD */ 27*4882a593Smuzhiyun#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 28*4882a593Smuzhiyun A2: 1-3 A1: 1-3 A0: 0-1 */ 29*4882a593Smuzhiyun#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ 30*4882a593Smuzhiyun#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ 31*4882a593Smuzhiyun#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ 32*4882a593Smuzhiyun#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ 33*4882a593Smuzhiyun#else /* CONFIG_CPU_SH7751 */ 34*4882a593Smuzhiyun#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ 35*4882a593Smuzhiyun#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ 36*4882a593Smuzhiyun#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 37*4882a593Smuzhiyun A3:2 A2:15 A1:15 A0:15 A0B:7 */ 38*4882a593Smuzhiyun#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 39*4882a593Smuzhiyun A2: 1-3 A1: 1-3 A0: 0-1 */ 40*4882a593Smuzhiyun#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ 41*4882a593Smuzhiyun#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ 42*4882a593Smuzhiyun#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ 43*4882a593Smuzhiyun#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ 44*4882a593Smuzhiyun#endif /* CONFIG_CPU_SH7751 */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun .global lowlevel_init 47*4882a593Smuzhiyun .text 48*4882a593Smuzhiyun .align 2 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunlowlevel_init: 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun write32 CCR_A, CCR_D_DISABLE 53*4882a593Smuzhiyun 54*4882a593Smuzhiyuninit_bsc: 55*4882a593Smuzhiyun write16 FRQCR_A, FRQCR_D 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun write32 BCR1_A, BCR1_D 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun write16 BCR2_A, BCR2_D 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun write32 WCR1_A, WCR1_D 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun write32 WCR2_A, WCR2_D 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun write32 WCR3_A, WCR3_D 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun write32 MCR_A, MCR_D1 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Set SDRAM mode */ 70*4882a593Smuzhiyun write8 SDMR3_A, SDMR3_D 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun ! Do you need PCMCIA setting? 73*4882a593Smuzhiyun ! If so, please add the lines here... 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun write16 RTCNT_A, RTCNT_D 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun write16 RTCOR_A, RTCOR_D 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun write16 RTCSR_A, RTCSR_D 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun write16 RFCR_A, RFCR_D 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Wait DRAM refresh 30 times */ 84*4882a593Smuzhiyun mov #30, r3 85*4882a593Smuzhiyun1: 86*4882a593Smuzhiyun mov.w @r1, r0 87*4882a593Smuzhiyun extu.w r0, r2 88*4882a593Smuzhiyun cmp/hi r3, r2 89*4882a593Smuzhiyun bf 1b 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun write32 MCR_A, MCR_D2 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Set SDRAM mode */ 94*4882a593Smuzhiyun write8 SDMR3_A, SDMR3_D 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun rts 97*4882a593Smuzhiyun nop 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun .align 2 100*4882a593Smuzhiyun 101*4882a593SmuzhiyunCCR_A: .long CCR 102*4882a593SmuzhiyunCCR_D_DISABLE: .long 0x0808 103*4882a593SmuzhiyunFRQCR_A: .long FRQCR 104*4882a593SmuzhiyunFRQCR_D: 105*4882a593Smuzhiyun#ifdef CONFIG_CPU_TYPE_R 106*4882a593Smuzhiyun .word 0x0e1a /* 12:3:3 */ 107*4882a593Smuzhiyun#else /* CONFIG_CPU_TYPE_R */ 108*4882a593Smuzhiyun#ifdef CONFIG_GOOD_SESH4 109*4882a593Smuzhiyun .word 0x00e13 /* 6:2:1 */ 110*4882a593Smuzhiyun#else 111*4882a593Smuzhiyun .word 0x00e23 /* 6:1:1 */ 112*4882a593Smuzhiyun#endif 113*4882a593Smuzhiyun.align 2 114*4882a593Smuzhiyun#endif /* CONFIG_CPU_TYPE_R */ 115*4882a593Smuzhiyun 116*4882a593SmuzhiyunBCR1_A: .long BCR1 117*4882a593SmuzhiyunBCR1_D: .long 0x00000008 /* Area 3 SDRAM */ 118*4882a593SmuzhiyunBCR2_A: .long BCR2 119*4882a593SmuzhiyunBCR2_D: .long BCR2_D_VALUE /* Bus width settings */ 120*4882a593SmuzhiyunWCR1_A: .long WCR1 121*4882a593SmuzhiyunWCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ 122*4882a593SmuzhiyunWCR2_A: .long WCR2 123*4882a593SmuzhiyunWCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ 124*4882a593SmuzhiyunWCR3_A: .long WCR3 125*4882a593SmuzhiyunWCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ 126*4882a593SmuzhiyunRTCSR_A: .long RTCSR 127*4882a593SmuzhiyunRTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ 128*4882a593Smuzhiyun.align 2 129*4882a593SmuzhiyunRTCNT_A: .long RTCNT 130*4882a593SmuzhiyunRTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ 131*4882a593Smuzhiyun.align 2 132*4882a593SmuzhiyunRTCOR_A: .long RTCOR 133*4882a593SmuzhiyunRTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ 134*4882a593Smuzhiyun.align 2 135*4882a593SmuzhiyunSDMR3_A: .long SDMR3_ADDRESS 136*4882a593SmuzhiyunSDMR3_D: .long 0x00 137*4882a593SmuzhiyunMCR_A: .long MCR 138*4882a593SmuzhiyunMCR_D1: .long MCR_D1_VALUE 139*4882a593SmuzhiyunMCR_D2: .long MCR_D2_VALUE 140*4882a593SmuzhiyunRFCR_A: .long RFCR 141*4882a593SmuzhiyunRFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ 142*4882a593Smuzhiyun.align 2 143