Lines Matching +full:0 +full:xa400
18 #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
19 #define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
21 #define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
24 #define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
27 #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
28 A2: 1-3 A1: 1-3 A0: 0-1 */
29 #define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
30 #define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
31 #define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
32 #define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
34 #define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
35 #define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
36 #define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
38 #define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
39 A2: 1-3 A1: 1-3 A0: 0-1 */
40 #define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
41 #define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
42 #define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
43 #define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
102 CCR_D_DISABLE: .long 0x0808
106 .word 0x0e1a /* 12:3:3 */
109 .word 0x00e13 /* 6:2:1 */
111 .word 0x00e23 /* 6:1:1 */
117 BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
127 RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
130 RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
136 SDMR3_D: .long 0x00
141 RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */