1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ar0822 driver
4 *
5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 support conversion gain switch.
9 * V0.0X01.0X02 add debug interface for conversion gain switch.
10 * V0.0X01.0X03 support enum sensor fmt
11 * V0.0X01.0X04 add quick stream on/off
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/version.h>
25 #include <linux/rk-camera-module.h>
26 #include <media/media-entity.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-subdev.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/rk-preisp.h>
32 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
33
34 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
35 #ifndef V4L2_CID_DIGITAL_GAIN
36 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
37 #endif
38
39 #define MIPI_FREQ_492M 492000000//500000000
40 #define MIPI_FREQ_657M 657000000
41 #define MIPI_FREQ_823M 823000000
42 #define MIPI_FREQ_986M 986000000/*657M for 1.314Gbps,986M for 1.972Gbps */
43
44 #define PIXEL_RATE_MAX (MIPI_FREQ_986M / 12 *2 * 4)
45
46 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
47
48 #define AR0822_XVCLK_FREQ 27000000 /*MCLK* need to config if XCLK from SOC; open.k*/
49
50 #define CHIP_ID 0x0F56
51 #define AR0822_REG_CHIP_ID 0x3000
52
53 #define AR0822_REG_CTRL_MODE 0x301A
54 #define AR0822_MODE_SW_STANDBY 0x0018
55 #define AR0822_MODE_STREAMING 0x001C
56
57 #define AR0822_EXPOSURE_MIN 2 /* 最小曝光时间 行 * need to config; open.k*/
58 #define AR0822_EXPOSURE_STEP 1
59 #define AR0822_VTS_MAX 0xffff /* Frame length line; open.k*/
60
61 #define AR0822_REG_EXP 0x3012
62
63 #define AR0822_REG_GAIN 0x5900
64 #define AR0822_REG_GAIN2 0x5902
65 #define AR0822_REG_GAIN3 0x5904
66 #define AR0822_GAIN_MIN 0
67 #define AR0822_GAIN_MAX 119
68 #define AR0822_GAIN_STEP 1
69 #define AR0822_GAIN_DEFAULT 0x20
70
71 #define AR0822_GROUP_UPDATE_ADDRESS 0x301A
72 #define AR0822_GROUP_UPDATE_START_DATA 0x801C
73 #define AR0822_GROUP_UPDATE_END_DATA 0x001C /* make sure exposure and gain take effect from N+2 frame; open.k*/
74
75 #define AR0822_SOFTWARE_RESET_REG 0x301A
76
77 #define AR0822_REG_VTS 0x300A
78
79 #define REG_NULL 0xFFFF /* Flag address for I2C array write,indicate this is the last row of I2C register table; open.k*/
80 #define REG_DELAY 0xFFFE
81
82 #define AR0822_REG_VALUE_08BIT 1
83 #define AR0822_REG_VALUE_16BIT 2
84 #define AR0822_REG_VALUE_24BIT 3
85
86 #define AR0822_LANES 4
87 #define AR0822_BPP12 12
88 #define AR0822_BPP14 14
89
90 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
91 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
92
93 #define AR0822_NAME "ar0822"
94
95 #define USED_SYS_DEBUG
96
97
98 /* sensor power on config, need check power, MCLK, GPIO etc,,, need go to .dts file to change the config; open.k */
99 static const char * const ar0822_supply_names[] = {
100 "avdd", /* Analog power */
101 "dovdd", /* Digital I/O power */
102 "dvdd", /* Digital core power */
103 };
104
105
106 #define AR0822_NUM_SUPPLIES ARRAY_SIZE(ar0822_supply_names)
107
108 #define AR0822_FLIP_REG 0x3040
109 #define MIRROR_BIT_MASK BIT(14)
110 #define FLIP_BIT_MASK BIT(15)
111
112 struct regval {
113 u16 addr;
114 u16 val;
115 };
116
117 /* Config resolution ,LLPCLK, FLL, exposure time,fps, MIPI channel config, HDR mode , open.k */
118 struct ar0822_mode {
119 u32 bus_fmt;
120 u32 width;
121 u32 height;
122 struct v4l2_fract max_fps;
123 u32 hts_def;
124 u32 vts_def;
125 u32 exp_def;
126 const struct regval *reg_list;
127 u32 hdr_mode;
128 u32 mipi_freq;
129 u32 mipi_rate;
130 u32 vc[PAD_MAX];
131 };
132
133 struct ar0822 {
134 struct i2c_client *client;
135 struct clk *xvclk;
136 struct gpio_desc *reset_gpio;
137 struct gpio_desc *pwdn_gpio;
138 struct regulator_bulk_data supplies[AR0822_NUM_SUPPLIES];
139
140 struct pinctrl *pinctrl;
141 struct pinctrl_state *pins_default;
142 struct pinctrl_state *pins_sleep;
143
144 struct v4l2_subdev subdev;
145 struct media_pad pad;
146 struct v4l2_ctrl_handler ctrl_handler;
147 struct v4l2_ctrl *exposure;
148 struct v4l2_ctrl *anal_gain;
149 struct v4l2_ctrl *digi_gain;
150 struct v4l2_ctrl *hblank;
151 struct v4l2_ctrl *vblank;
152 struct v4l2_ctrl *test_pattern;
153 struct v4l2_ctrl *pixel_rate;
154 struct v4l2_ctrl *link_freq;
155 struct v4l2_ctrl *h_flip;
156 struct v4l2_ctrl *v_flip;
157 struct mutex mutex;
158 bool streaming;
159 bool power_on;
160 const struct ar0822_mode *cur_mode;
161 u32 cfg_num;
162 u32 module_index;
163 const char *module_facing;
164 const char *module_name;
165 const char *len_name;
166 bool has_init_exp;
167 struct preisp_hdrae_exp_s init_hdrae_exp;
168 bool long_hcg;
169 bool middle_hcg;
170 bool short_hcg;
171 bool is_thunderboot;
172 bool is_thunderboot_ng;
173 bool is_first_streamoff;
174 u8 flip;
175 };
176 #define to_ar0822(sd) container_of(sd, struct ar0822, subdev)
177
178 /*
179 * Xclk 27Mhz
180 */
181 static const struct regval ar0822_linear_global_regs[] = {
182 {REG_DELAY, 2000},
183 {0x3030,0x0092},//PLL_MULTIPLIER
184 {0x302E,0x0002},//PRE_PLL_CLK_DIV
185 {0x302C,0x0002},//VT_SYS_CLK_DIV
186 {0x302A,0x0006},//VT_PIX_CLK_DIV
187 {0x3038,0x0004},//OP_SYS_CLK_DIV
188 {0x3036,0x0006},//OP_WORD_CLK_DIV
189 {0x31B0,0x0071},//FRAME_PREAMBLE
190 {0x31B2,0x004D},//LINE_PREAMBLE
191 {0x31B4,0x51C8},//MIPI_TIMING_0
192 {0x31B6,0x5288},//MIPI_TIMING_1
193 {0x31B8,0x70CA},//MIPI_TIMING_2
194 {0x31BA,0x030B},//MIPI_TIMING_3
195 {0x31BC,0x0C89},//MIPI_TIMING_4
196 {0x3342,0x122C},//MIPI_F1_PDT_EDT
197 {0x2512,0xA000},//SEQ_CTRL_PORT
198 {0x2510,0x0720},//SEQ_DATA_PORT
199 {0x2510,0xFFFF},//SEQ_DATA_PORT
200 {0x2510,0xFFFF},//SEQ_DATA_PORT
201 {0x2510,0xFFFF},//SEQ_DATA_PORT
202 {0x2510,0xFFFF},//SEQ_DATA_PORT
203 {0x2510,0xFFFF},//SEQ_DATA_PORT
204 {0x2510,0xFFFF},//SEQ_DATA_PORT
205 {0x2510,0xFFFF},//SEQ_DATA_PORT
206 {0x2510,0x2122},//SEQ_DATA_PORT
207 {0x2510,0xFFFF},//SEQ_DATA_PORT
208 {0x2510,0xFFFF},//SEQ_DATA_PORT
209 {0x2510,0xFFFF},//SEQ_DATA_PORT
210 {0x2510,0x26FF},//SEQ_DATA_PORT
211 {0x2510,0xFFFF},//SEQ_DATA_PORT
212 {0x2510,0xFFFF},//SEQ_DATA_PORT
213 {0x2510,0xFFFF},//SEQ_DATA_PORT
214 {0x2510,0xFFFF},//SEQ_DATA_PORT
215 {0x2510,0xFFFF},//SEQ_DATA_PORT
216 {0x2510,0xFFFF},//SEQ_DATA_PORT
217 {0x2510,0xFFFF},//SEQ_DATA_PORT
218 {0x2510,0xFFFF},//SEQ_DATA_PORT
219 {0x2510,0xFFFF},//SEQ_DATA_PORT
220 {0x2510,0xFFFF},//SEQ_DATA_PORT
221 {0x2510,0xFFFF},//SEQ_DATA_PORT
222 {0x2510,0xFFFF},//SEQ_DATA_PORT
223 {0x2510,0xFFFF},//SEQ_DATA_PORT
224 {0x2510,0xFFFF},//SEQ_DATA_PORT
225 {0x2510,0xFFFF},//SEQ_DATA_PORT
226 {0x2510,0x20FF},//SEQ_DATA_PORT
227 {0x2510,0x20FF},//SEQ_DATA_PORT
228 {0x2510,0x20FF},//SEQ_DATA_PORT
229 {0x2510,0x20FF},//SEQ_DATA_PORT
230 {0x2510,0x20FF},//SEQ_DATA_PORT
231 {0x2510,0x20FF},//SEQ_DATA_PORT
232 {0x2510,0x20FF},//SEQ_DATA_PORT
233 {0x2510,0x20FF},//SEQ_DATA_PORT
234 {0x2510,0x20FF},//SEQ_DATA_PORT
235 {0x2510,0x20FF},//SEQ_DATA_PORT
236 {0x2510,0x20FF},//SEQ_DATA_PORT
237 {0x2510,0x20FF},//SEQ_DATA_PORT
238 {0x2510,0x20FF},//SEQ_DATA_PORT
239 {0x2510,0x20FF},//SEQ_DATA_PORT
240 {0x2510,0x20FF},//SEQ_DATA_PORT
241 {0x2510,0x20FF},//SEQ_DATA_PORT
242 {0x2510,0x20FF},//SEQ_DATA_PORT
243 {0x2510,0x0F8C},//SEQ_DATA_PORT
244 {0x2510,0x20FF},//SEQ_DATA_PORT
245 {0x2510,0x20FF},//SEQ_DATA_PORT
246 {0x2510,0x20FF},//SEQ_DATA_PORT
247 {0x2510,0x20FF},//SEQ_DATA_PORT
248 {0x2510,0x20FF},//SEQ_DATA_PORT
249 {0x2510,0x20FF},//SEQ_DATA_PORT
250 {0x2510,0x20FF},//SEQ_DATA_PORT
251 {0x2510,0x20FF},//SEQ_DATA_PORT
252 {0x2510,0x20FF},//SEQ_DATA_PORT
253 {0x2510,0x20FF},//SEQ_DATA_PORT
254 {0x2510,0x20FF},//SEQ_DATA_PORT
255 {0x2510,0x20FF},//SEQ_DATA_PORT
256 {0x2510,0x20FF},//SEQ_DATA_PORT
257 {0x2510,0x20FF},//SEQ_DATA_PORT
258 {0x2510,0x20FF},//SEQ_DATA_PORT
259 {0x2510,0x20FF},//SEQ_DATA_PORT
260 {0x2510,0x20FF},//SEQ_DATA_PORT
261 {0x2510,0x20FF},//SEQ_DATA_PORT
262 {0x2510,0x20FF},//SEQ_DATA_PORT
263 {0x2510,0x20FF},//SEQ_DATA_PORT
264 {0x2510,0x20FF},//SEQ_DATA_PORT
265 {0x2510,0x20FF},//SEQ_DATA_PORT
266 {0x2510,0x20FF},//SEQ_DATA_PORT
267 {0x2510,0x20E0},//SEQ_DATA_PORT
268 {0x2510,0x8055},//SEQ_DATA_PORT
269 {0x2510,0xA0E1},//SEQ_DATA_PORT
270 {0x2510,0x3041},//SEQ_DATA_PORT
271 {0x2510,0x2000},//SEQ_DATA_PORT
272 {0x2510,0x3088},//SEQ_DATA_PORT
273 {0x2510,0x3282},//SEQ_DATA_PORT
274 {0x2510,0xA681},//SEQ_DATA_PORT
275 {0x2510,0x20FF},//SEQ_DATA_PORT
276 {0x2510,0x20FF},//SEQ_DATA_PORT
277 {0x2510,0x20FF},//SEQ_DATA_PORT
278 {0x2510,0x20FF},//SEQ_DATA_PORT
279 {0x2510,0x20FE},//SEQ_DATA_PORT
280 {0x2510,0x9070},//SEQ_DATA_PORT
281 {0x2510,0x891D},//SEQ_DATA_PORT
282 {0x2510,0x867F},//SEQ_DATA_PORT
283 {0x2510,0x20FF},//SEQ_DATA_PORT
284 {0x2510,0x20FC},//SEQ_DATA_PORT
285 {0x2510,0x893F},//SEQ_DATA_PORT
286 {0x2510,0x0F92},//SEQ_DATA_PORT
287 {0x2510,0x20E0},//SEQ_DATA_PORT
288 {0x2510,0x0F8F},//SEQ_DATA_PORT
289 {0x2510,0x20FF},//SEQ_DATA_PORT
290 {0x2510,0x20FF},//SEQ_DATA_PORT
291 {0x2510,0x20FF},//SEQ_DATA_PORT
292 {0x2510,0x20FF},//SEQ_DATA_PORT
293 {0x2510,0x20FF},//SEQ_DATA_PORT
294 {0x2510,0x20E0},//SEQ_DATA_PORT
295 {0x2510,0x9770},//SEQ_DATA_PORT
296 {0x2510,0x20FC},//SEQ_DATA_PORT
297 {0x2510,0x8054},//SEQ_DATA_PORT
298 {0x2510,0x896C},//SEQ_DATA_PORT
299 {0x2510,0x200A},//SEQ_DATA_PORT
300 {0x2510,0x9030},//SEQ_DATA_PORT
301 {0x2510,0x200A},//SEQ_DATA_PORT
302 {0x2510,0x8040},//SEQ_DATA_PORT
303 {0x2510,0x8948},//SEQ_DATA_PORT
304 {0x2510,0x200A},//SEQ_DATA_PORT
305 {0x2510,0x1597},//SEQ_DATA_PORT
306 {0x2510,0x8808},//SEQ_DATA_PORT
307 {0x2510,0x200A},//SEQ_DATA_PORT
308 {0x2510,0x1F96},//SEQ_DATA_PORT
309 {0x2510,0x20FF},//SEQ_DATA_PORT
310 {0x2510,0x20E0},//SEQ_DATA_PORT
311 {0x2510,0xA0C0},//SEQ_DATA_PORT
312 {0x2510,0x200A},//SEQ_DATA_PORT
313 {0x2510,0x3044},//SEQ_DATA_PORT
314 {0x2510,0x3088},//SEQ_DATA_PORT
315 {0x2510,0x3282},//SEQ_DATA_PORT
316 {0x2510,0x2004},//SEQ_DATA_PORT
317 {0x2510,0x1FAA},//SEQ_DATA_PORT
318 {0x2510,0x20FF},//SEQ_DATA_PORT
319 {0x2510,0x20FF},//SEQ_DATA_PORT
320 {0x2510,0x20FF},//SEQ_DATA_PORT
321 {0x2510,0x20FF},//SEQ_DATA_PORT
322 {0x2510,0x20E0},//SEQ_DATA_PORT
323 {0x2510,0x7FFF},//SEQ_DATA_PORT
324 {0x2510,0x7FFF},//SEQ_DATA_PORT
325 {0x2510,0x7FFF},//SEQ_DATA_PORT
326 {0x2510,0x20FF},//SEQ_DATA_PORT
327 {0x2510,0x7FFF},//SEQ_DATA_PORT
328 {0x2510,0x7FFF},//SEQ_DATA_PORT
329 {0x2510,0x7FFF},//SEQ_DATA_PORT
330 {0x2510,0x3108},//SEQ_DATA_PORT
331 {0x2510,0x2400},//SEQ_DATA_PORT
332 {0x2510,0x3244},//SEQ_DATA_PORT
333 {0x2510,0x7FFF},//SEQ_DATA_PORT
334 {0x2510,0x3108},//SEQ_DATA_PORT
335 {0x2510,0x2400},//SEQ_DATA_PORT
336 {0x2510,0x2702},//SEQ_DATA_PORT
337 {0x2510,0x3242},//SEQ_DATA_PORT
338 {0x2510,0x3108},//SEQ_DATA_PORT
339 {0x2510,0x2420},//SEQ_DATA_PORT
340 {0x2510,0x2703},//SEQ_DATA_PORT
341 {0x2510,0x3242},//SEQ_DATA_PORT
342 {0x2510,0x3108},//SEQ_DATA_PORT
343 {0x2510,0x2420},//SEQ_DATA_PORT
344 {0x2510,0x2704},//SEQ_DATA_PORT
345 {0x2510,0x3244},//SEQ_DATA_PORT
346 {0x2510,0x7FFF},//SEQ_DATA_PORT
347 {0x2510,0x7FFF},//SEQ_DATA_PORT
348 {0x2510,0x7FFF},//SEQ_DATA_PORT
349 {0x2510,0x7FFF},//SEQ_DATA_PORT
350 {0x2510,0x8801},//SEQ_DATA_PORT
351 {0x2510,0x000F},//SEQ_DATA_PORT
352 {0x2510,0x109C},//SEQ_DATA_PORT
353 {0x2510,0x8855},//SEQ_DATA_PORT
354 {0x2510,0x3101},//SEQ_DATA_PORT
355 {0x2510,0x3041},//SEQ_DATA_PORT
356 {0x2510,0x2000},//SEQ_DATA_PORT
357 {0x2510,0x3102},//SEQ_DATA_PORT
358 {0x2510,0x3041},//SEQ_DATA_PORT
359 {0x2510,0x2000},//SEQ_DATA_PORT
360 {0x2510,0x3181},//SEQ_DATA_PORT
361 {0x2510,0x3041},//SEQ_DATA_PORT
362 {0x2510,0x2000},//SEQ_DATA_PORT
363 {0x2510,0x3188},//SEQ_DATA_PORT
364 {0x2510,0x3041},//SEQ_DATA_PORT
365 {0x2510,0x2000},//SEQ_DATA_PORT
366 {0x2510,0x3282},//SEQ_DATA_PORT
367 {0x2510,0x3104},//SEQ_DATA_PORT
368 {0x2510,0x2000},//SEQ_DATA_PORT
369 {0x2510,0xB0E4},//SEQ_DATA_PORT
370 {0x2510,0xAD92},//SEQ_DATA_PORT
371 {0x2510,0xBC0C},//SEQ_DATA_PORT
372 {0x2510,0x1028},//SEQ_DATA_PORT
373 {0x2510,0x0022},//SEQ_DATA_PORT
374 {0x2510,0xC020},//SEQ_DATA_PORT
375 {0x2510,0x003E},//SEQ_DATA_PORT
376 {0x2510,0x0045},//SEQ_DATA_PORT
377 {0x2510,0x00B0},//SEQ_DATA_PORT
378 {0x2510,0x0028},//SEQ_DATA_PORT
379 {0x2510,0x30C1},//SEQ_DATA_PORT
380 {0x2510,0x8015},//SEQ_DATA_PORT
381 {0x2510,0xA038},//SEQ_DATA_PORT
382 {0x2510,0x100F},//SEQ_DATA_PORT
383 {0x2510,0x0507},//SEQ_DATA_PORT
384 {0x2510,0xA220},//SEQ_DATA_PORT
385 {0x2510,0x0010},//SEQ_DATA_PORT
386 {0x2510,0x10C2},//SEQ_DATA_PORT
387 {0x2510,0xB760},//SEQ_DATA_PORT
388 {0x2510,0x0033},//SEQ_DATA_PORT
389 {0x2510,0x1082},//SEQ_DATA_PORT
390 {0x2510,0x100B},//SEQ_DATA_PORT
391 {0x2510,0x1029},//SEQ_DATA_PORT
392 {0x2510,0xA85A},//SEQ_DATA_PORT
393 {0x2510,0x998D},//SEQ_DATA_PORT
394 {0x2510,0xC810},//SEQ_DATA_PORT
395 {0x2510,0x2004},//SEQ_DATA_PORT
396 {0x2510,0x0ECE},//SEQ_DATA_PORT
397 {0x2510,0x123B},//SEQ_DATA_PORT
398 {0x2510,0xC000},//SEQ_DATA_PORT
399 {0x2510,0x032F},//SEQ_DATA_PORT
400 {0x2510,0x11D5},//SEQ_DATA_PORT
401 {0x2510,0x162F},//SEQ_DATA_PORT
402 {0x2510,0x9000},//SEQ_DATA_PORT
403 {0x2510,0x2034},//SEQ_DATA_PORT
404 {0x2510,0x0015},//SEQ_DATA_PORT
405 {0x2510,0x04CB},//SEQ_DATA_PORT
406 {0x2510,0x1022},//SEQ_DATA_PORT
407 {0x2510,0x1031},//SEQ_DATA_PORT
408 {0x2510,0x002D},//SEQ_DATA_PORT
409 {0x2510,0x1015},//SEQ_DATA_PORT
410 {0x2510,0x80B9},//SEQ_DATA_PORT
411 {0x2510,0xA101},//SEQ_DATA_PORT
412 {0x2510,0x001C},//SEQ_DATA_PORT
413 {0x2510,0x008E},//SEQ_DATA_PORT
414 {0x2510,0x124B},//SEQ_DATA_PORT
415 {0x2510,0x01B5},//SEQ_DATA_PORT
416 {0x2510,0x0B92},//SEQ_DATA_PORT
417 {0x2510,0xA400},//SEQ_DATA_PORT
418 {0x2510,0x8091},//SEQ_DATA_PORT
419 {0x2510,0x0028},//SEQ_DATA_PORT
420 {0x2510,0x3002},//SEQ_DATA_PORT
421 {0x2510,0x2004},//SEQ_DATA_PORT
422 {0x2510,0x1012},//SEQ_DATA_PORT
423 {0x2510,0x100E},//SEQ_DATA_PORT
424 {0x2510,0x10A8},//SEQ_DATA_PORT
425 {0x2510,0x00A1},//SEQ_DATA_PORT
426 {0x2510,0x132D},//SEQ_DATA_PORT
427 {0x2510,0x09AF},//SEQ_DATA_PORT
428 {0x2510,0x0159},//SEQ_DATA_PORT
429 {0x2510,0x121D},//SEQ_DATA_PORT
430 {0x2510,0x1259},//SEQ_DATA_PORT
431 {0x2510,0x11AF},//SEQ_DATA_PORT
432 {0x2510,0x18B5},//SEQ_DATA_PORT
433 {0x2510,0x0395},//SEQ_DATA_PORT
434 {0x2510,0x054B},//SEQ_DATA_PORT
435 {0x2510,0x1021},//SEQ_DATA_PORT
436 {0x2510,0x0020},//SEQ_DATA_PORT
437 {0x2510,0x1015},//SEQ_DATA_PORT
438 {0x2510,0x1030},//SEQ_DATA_PORT
439 {0x2510,0x00CF},//SEQ_DATA_PORT
440 {0x2510,0xB146},//SEQ_DATA_PORT
441 {0x2510,0xC290},//SEQ_DATA_PORT
442 {0x2510,0x103C},//SEQ_DATA_PORT
443 {0x2510,0xA882},//SEQ_DATA_PORT
444 {0x2510,0x8055},//SEQ_DATA_PORT
445 {0x2510,0x00A9},//SEQ_DATA_PORT
446 {0x2510,0x8801},//SEQ_DATA_PORT
447 {0x2510,0xB700},//SEQ_DATA_PORT
448 {0x2510,0x0001},//SEQ_DATA_PORT
449 {0x2510,0x02A2},//SEQ_DATA_PORT
450 {0x2510,0x000A},//SEQ_DATA_PORT
451 {0x2510,0x98BB},//SEQ_DATA_PORT
452 {0x2510,0x203F},//SEQ_DATA_PORT
453 {0x2510,0x0036},//SEQ_DATA_PORT
454 {0x2510,0x1001},//SEQ_DATA_PORT
455 {0x2510,0x99BE},//SEQ_DATA_PORT
456 {0x2510,0x0139},//SEQ_DATA_PORT
457 {0x2510,0x100A},//SEQ_DATA_PORT
458 {0x2510,0x0040},//SEQ_DATA_PORT
459 {0x2510,0x1022},//SEQ_DATA_PORT
460 {0x2510,0x124C},//SEQ_DATA_PORT
461 {0x2510,0x109F},//SEQ_DATA_PORT
462 {0x2510,0x15A3},//SEQ_DATA_PORT
463 {0x2510,0x002A},//SEQ_DATA_PORT
464 {0x2510,0x3081},//SEQ_DATA_PORT
465 {0x2510,0x2001},//SEQ_DATA_PORT
466 {0x2510,0x3044},//SEQ_DATA_PORT
467 {0x2510,0x2000},//SEQ_DATA_PORT
468 {0x2510,0x112A},//SEQ_DATA_PORT
469 {0x2510,0x101D},//SEQ_DATA_PORT
470 {0x2510,0x202B},//SEQ_DATA_PORT
471 {0x2510,0x02B8},//SEQ_DATA_PORT
472 {0x2510,0x10B8},//SEQ_DATA_PORT
473 {0x2510,0x1136},//SEQ_DATA_PORT
474 {0x2510,0x996B},//SEQ_DATA_PORT
475 {0x2510,0x004C},//SEQ_DATA_PORT
476 {0x2510,0x1039},//SEQ_DATA_PORT
477 {0x2510,0x1040},//SEQ_DATA_PORT
478 {0x2510,0x00B5},//SEQ_DATA_PORT
479 {0x2510,0x03C4},//SEQ_DATA_PORT
480 {0x2510,0x1144},//SEQ_DATA_PORT
481 {0x2510,0x1245},//SEQ_DATA_PORT
482 {0x2510,0x9A7B},//SEQ_DATA_PORT
483 {0x2510,0x002B},//SEQ_DATA_PORT
484 {0x2510,0x30D0},//SEQ_DATA_PORT
485 {0x2510,0x3141},//SEQ_DATA_PORT
486 {0x2510,0x3041},//SEQ_DATA_PORT
487 {0x2510,0x2000},//SEQ_DATA_PORT
488 {0x2510,0x3142},//SEQ_DATA_PORT
489 {0x2510,0x3041},//SEQ_DATA_PORT
490 {0x2510,0x2000},//SEQ_DATA_PORT
491 {0x2510,0x3110},//SEQ_DATA_PORT
492 {0x2510,0x3041},//SEQ_DATA_PORT
493 {0x2510,0x2000},//SEQ_DATA_PORT
494 {0x2510,0x3120},//SEQ_DATA_PORT
495 {0x2510,0x3041},//SEQ_DATA_PORT
496 {0x2510,0x2000},//SEQ_DATA_PORT
497 {0x2510,0x3144},//SEQ_DATA_PORT
498 {0x2510,0x3041},//SEQ_DATA_PORT
499 {0x2510,0x2000},//SEQ_DATA_PORT
500 {0x2510,0x3148},//SEQ_DATA_PORT
501 {0x2510,0x3041},//SEQ_DATA_PORT
502 {0x2510,0x2000},//SEQ_DATA_PORT
503 {0x2510,0x3182},//SEQ_DATA_PORT
504 {0x2510,0x3041},//SEQ_DATA_PORT
505 {0x2510,0x2000},//SEQ_DATA_PORT
506 {0x2510,0x3184},//SEQ_DATA_PORT
507 {0x2510,0x2000},//SEQ_DATA_PORT
508 {0x2510,0x3190},//SEQ_DATA_PORT
509 {0x2510,0x3041},//SEQ_DATA_PORT
510 {0x2510,0x2000},//SEQ_DATA_PORT
511 {0x2510,0x31A0},//SEQ_DATA_PORT
512 {0x2510,0x3088},//SEQ_DATA_PORT
513 {0x2510,0x2201},//SEQ_DATA_PORT
514 {0x2510,0x807D},//SEQ_DATA_PORT
515 {0x2510,0x2206},//SEQ_DATA_PORT
516 {0x2510,0x8815},//SEQ_DATA_PORT
517 {0x2510,0x8877},//SEQ_DATA_PORT
518 {0x2510,0x0092},//SEQ_DATA_PORT
519 {0x2510,0x220E},//SEQ_DATA_PORT
520 {0x2510,0x2211},//SEQ_DATA_PORT
521 {0x2510,0x8055},//SEQ_DATA_PORT
522 {0x2510,0x3001},//SEQ_DATA_PORT
523 {0x2510,0x2000},//SEQ_DATA_PORT
524 {0x2510,0x8A61},//SEQ_DATA_PORT
525 {0x2510,0x8801},//SEQ_DATA_PORT
526 {0x2510,0x1092},//SEQ_DATA_PORT
527 {0x2510,0x181F},//SEQ_DATA_PORT
528 {0x2510,0x0B1F},//SEQ_DATA_PORT
529 {0x2510,0x101F},//SEQ_DATA_PORT
530 {0x2510,0x00B6},//SEQ_DATA_PORT
531 {0x2510,0x0023},//SEQ_DATA_PORT
532 {0x2510,0x00B9},//SEQ_DATA_PORT
533 {0x2510,0x104C},//SEQ_DATA_PORT
534 {0x2510,0x996E},//SEQ_DATA_PORT
535 {0x2510,0x0140},//SEQ_DATA_PORT
536 {0x2510,0x0257},//SEQ_DATA_PORT
537 {0x2510,0x1035},//SEQ_DATA_PORT
538 {0x2510,0x9F26},//SEQ_DATA_PORT
539 {0x2510,0x1423},//SEQ_DATA_PORT
540 {0x2510,0x0048},//SEQ_DATA_PORT
541 {0x2510,0xC878},//SEQ_DATA_PORT
542 {0x2510,0x200A},//SEQ_DATA_PORT
543 {0x2510,0x1548},//SEQ_DATA_PORT
544 {0x2510,0x0C49},//SEQ_DATA_PORT
545 {0x2510,0x1149},//SEQ_DATA_PORT
546 {0x2510,0x002A},//SEQ_DATA_PORT
547 {0x2510,0x1057},//SEQ_DATA_PORT
548 {0x2510,0x3281},//SEQ_DATA_PORT
549 {0x2510,0x2000},//SEQ_DATA_PORT
550 {0x2510,0x3044},//SEQ_DATA_PORT
551 {0x2510,0x2001},//SEQ_DATA_PORT
552 {0x2510,0xA020},//SEQ_DATA_PORT
553 {0x2510,0x000C},//SEQ_DATA_PORT
554 {0x2510,0x9825},//SEQ_DATA_PORT
555 {0x2510,0x1040},//SEQ_DATA_PORT
556 {0x2510,0x1054},//SEQ_DATA_PORT
557 {0x2510,0xB06D},//SEQ_DATA_PORT
558 {0x2510,0x0035},//SEQ_DATA_PORT
559 {0x2510,0x004D},//SEQ_DATA_PORT
560 {0x2510,0x9905},//SEQ_DATA_PORT
561 {0x2510,0xB064},//SEQ_DATA_PORT
562 {0x2510,0x99C5},//SEQ_DATA_PORT
563 {0x2510,0x0047},//SEQ_DATA_PORT
564 {0x2510,0xB920},//SEQ_DATA_PORT
565 {0x2510,0x1447},//SEQ_DATA_PORT
566 {0x2510,0x7FFF},//SEQ_DATA_PORT
567 {0x2510,0x7FFF},//SEQ_DATA_PORT
568 {0x2510,0x7FFF},//SEQ_DATA_PORT
569 {0x2510,0x7FFF},//SEQ_DATA_PORT
570 {0x2510,0x7FFF},//SEQ_DATA_PORT
571 {0x2510,0x7FFF},//SEQ_DATA_PORT
572 {0x2510,0x7FFF},//SEQ_DATA_PORT
573 {0x2510,0x7FFF},//SEQ_DATA_PORT
574 {0x2510,0x7FFF},//SEQ_DATA_PORT
575 {0x31F8,0x0008},//MIPI_CONFIG_2
576 {0x3C70,0x6828},//CALIB_ROWS
577 {0x3092,0x0826},//ROW_NOISE_CONTROL
578 {0x3428,0x0209},//SEQUENCER_CONTROL
579 {0x3516,0xFF04},//DAC_LD_22_23
580 {0x3526,0x6480},//DAC_LD_38_39
581 {0x3504,0x8AAA},//DAC_LD_4_5
582 {0x353C,0x220C},//DAC_LD_60_61
583 {0x3536,0x4C6E},//DAC_LD_54_55
584 {0x3D2A,0x0FFF},//T1_END_DEC_TH
585 {0x3364,0x00EC},//DCG_TRIM
586 {0x3512,0x8888},//DAC_LD_18_19
587 {0x3514,0x888F},//DAC_LD_20_21
588 {0x3520,0xFBF0},//DAC_LD_32_33
589 {0x3524,0xB2A1},//DAC_LD_36_37
590 {0x3528,0xCC84},//DAC_LD_40_41
591 {0x3532,0x4C8E},//DAC_LD_50_51
592 {0x3534,0x4E64},//DAC_LD_52_53
593 {0x351E,0x5856},//DAC_LD_30_31
594 {0x353E,0x98F2},//DAC_LD_62_63
595 {0x352E,0x6A8A},//DAC_LD_46_47
596 {0x3370,0x0211},//DBLC_CONTROL
597 {0x3372,0x700F},//DBLC_FS0_CONTROL
598 {0x3540,0x3597},//DAC_LD_64_65
599 {0x58E2,0x0BE3},//COL_COUNT_VALUES1
600 {0x58E4,0x18B4},//COL_COUNT_VALUES2
601 {0x3522,0x7C97},//DAC_LD_34_35
602 {0x30BA,0x0024},//DIGITAL_CTRL
603 {0x31D4,0x0042},//CLK_MEM_GATING_CTRL
604 {0x352A,0x6F8F},//DAC_LD_42_43
605 {0x3530,0x4A08},//DAC_LD_48_49
606 {0x351A,0x5FFF},//DAC_LD_26_27
607 {0x350E,0x39D9},//DAC_LD_14_15
608 {0x3510,0x9988},//DAC_LD_16_17
609 {0x3380,0x1FFF},//DBLC_OFFSET1
610 {0x337A,0x1000},//DBLC_SCALE1
611 {0x3092,0x0800},//ROW_NOISE_CONTROL
612 {0x350A,0x0654},//DAC_LD_10_11
613 {0x3364,0x00E0},//DCG_TRIM
614 {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA
615 {0x591E,0x722C},//ANALOG_GAIN_WR_DATA
616 {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA
617 {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA
618 {0x591E,0xA447},//ANALOG_GAIN_WR_DATA
619 {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA
620 {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA
621 {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA
622 {0x3532,0x4C8A},//DAC_LD_50_51
623 {0x3534,0x4E60},//DAC_LD_52_53
624 {0x353E,0x90F2},//DAC_LD_62_63
625 {0x351A,0x4FFF},//DAC_LD_26_27
626 {0x591C,0x00D7},//DGR_AMP_GAIN
627 {0x3522,0x6097},//DAC_LD_34_35
628 {0x5002,0x37C3},//T1_PIX_DEF_ID2
629 {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0
630 {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1
631 {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2
632 {0x51D0,0x0001},//T1_NOISE_FLOOR0
633 {0x51D2,0x0002},//T1_NOISE_FLOOR1
634 {0x51D4,0x0003},//T1_NOISE_FLOOR2
635 {0x51D6,0x0004},//T1_NOISE_FLOOR3
636 {0x5202,0x37C3},//T2_PIX_DEF_ID2
637 {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0
638 {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1
639 {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2
640 {0x51EE,0x0001},//T2_NOISE_FLOOR0
641 {0x51F0,0x0002},//T2_NOISE_FLOOR1
642 {0x51F2,0x0003},//T2_NOISE_FLOOR2
643 {0x51F4,0x0004},//T2_NOISE_FLOOR3
644 {0x5402,0x37C3},//T4_PIX_DEF_ID2
645 {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0
646 {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1
647 {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2
648 {0x5564,0x0001},//T4_NOISE_FLOOR0
649 {0x5566,0x0002},//T4_NOISE_FLOOR1
650 {0x5568,0x0003},//T4_NOISE_FLOOR2
651 {0x556A,0x0004},//T4_NOISE_FLOOR3
652 {0x31E0,0x0001},//PIX_DEF_ID
653 {0x5000,0x0080},//T1_PIX_DEF_ID
654 {0x5000,0x0180},//T1_PIX_DEF_ID
655 {0x5000,0x0180},//T1_PIX_DEF_ID
656 {0x5200,0x0080},//T2_PIX_DEF_ID
657 {0x5200,0x0180},//T2_PIX_DEF_ID
658 {0x5200,0x0180},//T2_PIX_DEF_ID
659 {0x5400,0x0080},//T4_PIX_DEF_ID
660 {0x5400,0x0180},//T4_PIX_DEF_ID
661 {0x5400,0x0180},//T4_PIX_DEF_ID
662 {0x5000,0x1180},//T1_PIX_DEF_ID
663 {0x50A2,0x2553},//BMT0
664 {0x50A4,0xDFD4},//BMT1
665 {0x50A6,0x030F},//SINGLEK_FACTOR0
666 {0x50A6,0x0F0F},//SINGLEK_FACTOR0
667 {0x50A8,0x030F},//SINGLEK_FACTOR1
668 {0x50A8,0x0F0F},//SINGLEK_FACTOR1
669 {0x50AA,0x030F},//SINGLEK_FACTOR2
670 {0x50AA,0x050F},//SINGLEK_FACTOR2
671 {0x50AC,0x0301},//CROSS_FACTOR0
672 {0x50AC,0x0101},//CROSS_FACTOR0
673 {0x50AE,0x0301},//CROSS_FACTOR1
674 {0x50AE,0x0101},//CROSS_FACTOR1
675 {0x50B0,0x0301},//CROSS_FACTOR2
676 {0x50B0,0x0101},//CROSS_FACTOR2
677 {0x50B2,0x03FF},//SINGLE_MAX_FACTOR
678 {0x50B4,0x030F},//COUPLE_FACTOR0
679 {0x50B4,0x0F0F},//COUPLE_FACTOR0
680 {0x50B6,0x030F},//COUPLE_FACTOR1
681 {0x50B6,0x0F0F},//COUPLE_FACTOR1
682 {0x50B8,0x030F},//COUPLE_FACTOR2
683 {0x50B8,0x050F},//COUPLE_FACTOR2
684 {0x31AE,0x0204},//SERIAL_FORMAT
685 {0x31AC,0x0C0C},//DATA_FORMAT_BITS
686 {0x3082,0x0001},//OPERATION_MODE_CTRL
687 {0x30BA,0x0024},//DIGITAL_CTRL
688 {0x31AE,0x0204},//SERIAL_FORMAT
689 {0x31AC,0x0C0C},//DATA_FORMAT_BITS
690 {0x300C,0x0866},//LINE_LENGTH_PCK_
691 {0x300A,0x09F3},//FRAME_LENGTH_LINES_
692 {0x3012,0x08F4},//COARSE_INTEGRATION_TIME_
693 {0x5914,0x4012},//SENSOR_GAIN_TABLE_SEL
694 {REG_DELAY,100},
695 {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL
696 {0x5910,0x608A},//SENSOR_GAIN_REG1
697 {0x5910,0x7091},//SENSOR_GAIN_REG1
698 {0x5910,0x689C},//SENSOR_GAIN_REG1
699 {0x5910,0x8885},//SENSOR_GAIN_REG1
700 {0x5910,0x98AD},//SENSOR_GAIN_REG1
701 {0x5910,0xA8A9},//SENSOR_GAIN_REG1
702 {0x5910,0xC894},//SENSOR_GAIN_REG1
703 {0x5910,0xC8D1},//SENSOR_GAIN_REG1
704 {0x5910,0xD88A},//SENSOR_GAIN_REG1
705 {0x5910,0xD8C3},//SENSOR_GAIN_REG1
706 {0x5910,0xD915},//SENSOR_GAIN_REG1
707 {0x5910,0xD988},//SENSOR_GAIN_REG1
708 {0x5910,0xDA2A},//SENSOR_GAIN_REG1
709 {0x5910,0xDB0E},//SENSOR_GAIN_REG1
710 {0x5910,0xDC53},//SENSOR_GAIN_REG1
711 {0x5910,0x608A},//SENSOR_GAIN_REG1
712 {0x5910,0xC919},//SENSOR_GAIN_REG1
713 {0x5910,0xCA00},//SENSOR_GAIN_REG1
714 {0x5910,0x0000},//SENSOR_GAIN_REG1
715 {0x5910,0x0000},//SENSOR_GAIN_REG1
716 {0x5910,0x0000},//SENSOR_GAIN_REG1
717 {0x5910,0x0001},//SENSOR_GAIN_REG1
718 {0x5910,0x0001},//SENSOR_GAIN_REG1
719 {0x5910,0x0003},//SENSOR_GAIN_REG1
720 {0x5910,0x0003},//SENSOR_GAIN_REG1
721 {0x5910,0x0003},//SENSOR_GAIN_REG1
722 {0x5910,0x0004},//SENSOR_GAIN_REG1
723 {0x5910,0x0004},//SENSOR_GAIN_REG1
724 {0x5910,0x0004},//SENSOR_GAIN_REG1
725 {0x5910,0x0004},//SENSOR_GAIN_REG1
726 {0x5910,0x0004},//SENSOR_GAIN_REG1
727 {0x5910,0x0004},//SENSOR_GAIN_REG1
728 {0x5910,0x0004},//SENSOR_GAIN_REG1
729 {0x5910,0x0002},//SENSOR_GAIN_REG1
730 {0x5910,0x0003},//SENSOR_GAIN_REG1
731 {0x5910,0x0003},//SENSOR_GAIN_REG1
732 {0x5910,0x5A8B},//SENSOR_GAIN_REG1
733 {0x5910,0xFF04},//SENSOR_GAIN_REG1
734 {0x5910,0xF704},//SENSOR_GAIN_REG1
735 {0x5910,0xFF04},//SENSOR_GAIN_REG1
736 {0x5910,0xF704},//SENSOR_GAIN_REG1
737 {0x5910,0xF704},//SENSOR_GAIN_REG1
738 {0x5910,0x0005},//SENSOR_GAIN_REG1
739 {0x5910,0x0006},//SENSOR_GAIN_REG1
740 {0x5910,0x0007},//SENSOR_GAIN_REG1
741 {0x5910,0x9A8B},//SENSOR_GAIN_REG1
742 {0x5910,0xFF04},//SENSOR_GAIN_REG1
743 {0x5910,0xF704},//SENSOR_GAIN_REG1
744 {0x5910,0xF704},//SENSOR_GAIN_REG1
745 {0x5910,0xF704},//SENSOR_GAIN_REG1
746 {0x5910,0xF704},//SENSOR_GAIN_REG1
747 {0x5910,0x0015},//SENSOR_GAIN_REG1
748 {0x5910,0x0016},//SENSOR_GAIN_REG1
749 {0x5910,0x0017},//SENSOR_GAIN_REG1
750 {0x5910,0xDA8B},//SENSOR_GAIN_REG1
751 {0x5910,0xFF04},//SENSOR_GAIN_REG1
752 {0x5910,0xF704},//SENSOR_GAIN_REG1
753 {0x5910,0xF704},//SENSOR_GAIN_REG1
754 {0x5910,0xF704},//SENSOR_GAIN_REG1
755 {0x5910,0xF704},//SENSOR_GAIN_REG1
756 {0x5910,0x0025},//SENSOR_GAIN_REG1
757 {0x5910,0x0026},//SENSOR_GAIN_REG1
758 {0x5910,0x0027},//SENSOR_GAIN_REG1
759 {0x5910,0x59B9},//SENSOR_GAIN_REG1
760 {0x5910,0x700F},//SENSOR_GAIN_REG1
761 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
762 {0x5910,0x700F},//SENSOR_GAIN_REG1
763 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
764 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
765 {0x5910,0x0035},//SENSOR_GAIN_REG1
766 {0x5910,0x0036},//SENSOR_GAIN_REG1
767 {0x5910,0x0037},//SENSOR_GAIN_REG1
768 {0x5910,0x99B9},//SENSOR_GAIN_REG1
769 {0x5910,0x700F},//SENSOR_GAIN_REG1
770 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
771 {0x5910,0x700F},//SENSOR_GAIN_REG1
772 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
773 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
774 {0x5910,0x0045},//SENSOR_GAIN_REG1
775 {0x5910,0x0046},//SENSOR_GAIN_REG1
776 {0x5910,0x0047},//SENSOR_GAIN_REG1
777 {0x5910,0xD9B9},//SENSOR_GAIN_REG1
778 {0x5910,0x700F},//SENSOR_GAIN_REG1
779 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
780 {0x5910,0x700F},//SENSOR_GAIN_REG1
781 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
782 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
783 {0x5910,0x0055},//SENSOR_GAIN_REG1
784 {0x5910,0x0056},//SENSOR_GAIN_REG1
785 {0x5910,0x0057},//SENSOR_GAIN_REG1
786 {0x5910,0x9A85},//SENSOR_GAIN_REG1
787 {0x5910,0x0654},//SENSOR_GAIN_REG1
788 {0x5910,0x0654},//SENSOR_GAIN_REG1
789 {0x5910,0x0684},//SENSOR_GAIN_REG1
790 {0x5910,0x0654},//SENSOR_GAIN_REG1
791 {0x5910,0x0654},//SENSOR_GAIN_REG1
792 {0x5910,0x0065},//SENSOR_GAIN_REG1
793 {0x5910,0x0066},//SENSOR_GAIN_REG1
794 {0x5910,0x0067},//SENSOR_GAIN_REG1
795 {0x5910,0x59BD},//SENSOR_GAIN_REG1
796 {0x5910,0x1000},//SENSOR_GAIN_REG1
797 {0x5910,0x0C00},//SENSOR_GAIN_REG1
798 {0x5910,0x0F00},//SENSOR_GAIN_REG1
799 {0x5910,0x1000},//SENSOR_GAIN_REG1
800 {0x5910,0x10F0},//SENSOR_GAIN_REG1
801 {0x5910,0x0075},//SENSOR_GAIN_REG1
802 {0x5910,0x0076},//SENSOR_GAIN_REG1
803 {0x5910,0x0077},//SENSOR_GAIN_REG1
804 {0x5912,0x608A},//SENSOR_GAIN_REG2
805 {0x5912,0x7091},//SENSOR_GAIN_REG2
806 {0x5912,0x689C},//SENSOR_GAIN_REG2
807 {0x5912,0x8885},//SENSOR_GAIN_REG2
808 {0x5912,0x98AD},//SENSOR_GAIN_REG2
809 {0x5912,0xA8A9},//SENSOR_GAIN_REG2
810 {0x5912,0xC894},//SENSOR_GAIN_REG2
811 {0x5912,0xC8D1},//SENSOR_GAIN_REG2
812 {0x5912,0xC927},//SENSOR_GAIN_REG2
813 {0x5912,0xC9A0},//SENSOR_GAIN_REG2
814 {0x5912,0xCA4C},//SENSOR_GAIN_REG2
815 {0x5912,0xCB3F},//SENSOR_GAIN_REG2
816 {0x5912,0xCC97},//SENSOR_GAIN_REG2
817 {0x5912,0xCE7C},//SENSOR_GAIN_REG2
818 {0x5912,0xCFFF},//SENSOR_GAIN_REG2
819 {0x5912,0x608A},//SENSOR_GAIN_REG2
820 {0x5912,0xC8F0},//SENSOR_GAIN_REG2
821 {0x5912,0xCA00},//SENSOR_GAIN_REG2
822 {0x5912,0x0000},//SENSOR_GAIN_REG2
823 {0x5912,0x0000},//SENSOR_GAIN_REG2
824 {0x5912,0x0000},//SENSOR_GAIN_REG2
825 {0x5912,0x0001},//SENSOR_GAIN_REG2
826 {0x5912,0x0001},//SENSOR_GAIN_REG2
827 {0x5912,0x0003},//SENSOR_GAIN_REG2
828 {0x5912,0x0003},//SENSOR_GAIN_REG2
829 {0x5912,0x0003},//SENSOR_GAIN_REG2
830 {0x5912,0x0004},//SENSOR_GAIN_REG2
831 {0x5912,0x0004},//SENSOR_GAIN_REG2
832 {0x5912,0x0004},//SENSOR_GAIN_REG2
833 {0x5912,0x0004},//SENSOR_GAIN_REG2
834 {0x5912,0x0004},//SENSOR_GAIN_REG2
835 {0x5912,0x0004},//SENSOR_GAIN_REG2
836 {0x5912,0x0004},//SENSOR_GAIN_REG2
837 {0x5912,0x0002},//SENSOR_GAIN_REG2
838 {0x5912,0x0003},//SENSOR_GAIN_REG2
839 {0x5912,0x0003},//SENSOR_GAIN_REG2
840 {0x5912,0x5A8B},//SENSOR_GAIN_REG2
841 {0x5912,0xFF04},//SENSOR_GAIN_REG2
842 {0x5912,0xF704},//SENSOR_GAIN_REG2
843 {0x5912,0xFF04},//SENSOR_GAIN_REG2
844 {0x5912,0xF704},//SENSOR_GAIN_REG2
845 {0x5912,0xF704},//SENSOR_GAIN_REG2
846 {0x5912,0x0005},//SENSOR_GAIN_REG2
847 {0x5912,0x0006},//SENSOR_GAIN_REG2
848 {0x5912,0x0007},//SENSOR_GAIN_REG2
849 {0x5912,0x9A8B},//SENSOR_GAIN_REG2
850 {0x5912,0xFF04},//SENSOR_GAIN_REG2
851 {0x5912,0xF704},//SENSOR_GAIN_REG2
852 {0x5912,0xF704},//SENSOR_GAIN_REG2
853 {0x5912,0xF704},//SENSOR_GAIN_REG2
854 {0x5912,0xF704},//SENSOR_GAIN_REG2
855 {0x5912,0x0015},//SENSOR_GAIN_REG2
856 {0x5912,0x0016},//SENSOR_GAIN_REG2
857 {0x5912,0x0017},//SENSOR_GAIN_REG2
858 {0x5912,0xDA8B},//SENSOR_GAIN_REG2
859 {0x5912,0xFF04},//SENSOR_GAIN_REG2
860 {0x5912,0xF704},//SENSOR_GAIN_REG2
861 {0x5912,0xF704},//SENSOR_GAIN_REG2
862 {0x5912,0xF704},//SENSOR_GAIN_REG2
863 {0x5912,0xF704},//SENSOR_GAIN_REG2
864 {0x5912,0x0025},//SENSOR_GAIN_REG2
865 {0x5912,0x0026},//SENSOR_GAIN_REG2
866 {0x5912,0x0027},//SENSOR_GAIN_REG2
867 {0x5912,0x59B9},//SENSOR_GAIN_REG2
868 {0x5912,0x700F},//SENSOR_GAIN_REG2
869 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
870 {0x5912,0x700F},//SENSOR_GAIN_REG2
871 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
872 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
873 {0x5912,0x0035},//SENSOR_GAIN_REG2
874 {0x5912,0x0036},//SENSOR_GAIN_REG2
875 {0x5912,0x0037},//SENSOR_GAIN_REG2
876 {0x5912,0x99B9},//SENSOR_GAIN_REG2
877 {0x5912,0x700F},//SENSOR_GAIN_REG2
878 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
879 {0x5912,0x700F},//SENSOR_GAIN_REG2
880 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
881 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
882 {0x5912,0x0045},//SENSOR_GAIN_REG2
883 {0x5912,0x0046},//SENSOR_GAIN_REG2
884 {0x5912,0x0047},//SENSOR_GAIN_REG2
885 {0x5912,0xD9B9},//SENSOR_GAIN_REG2
886 {0x5912,0x700F},//SENSOR_GAIN_REG2
887 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
888 {0x5912,0x700F},//SENSOR_GAIN_REG2
889 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
890 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
891 {0x5912,0x0055},//SENSOR_GAIN_REG2
892 {0x5912,0x0056},//SENSOR_GAIN_REG2
893 {0x5912,0x0057},//SENSOR_GAIN_REG2
894 {0x5912,0x9A85},//SENSOR_GAIN_REG2
895 {0x5912,0x0654},//SENSOR_GAIN_REG2
896 {0x5912,0x0654},//SENSOR_GAIN_REG2
897 {0x5912,0x0684},//SENSOR_GAIN_REG2
898 {0x5912,0x0654},//SENSOR_GAIN_REG2
899 {0x5912,0x0654},//SENSOR_GAIN_REG2
900 {0x5912,0x0065},//SENSOR_GAIN_REG2
901 {0x5912,0x0066},//SENSOR_GAIN_REG2
902 {0x5912,0x0067},//SENSOR_GAIN_REG2
903 {0x5912,0x59BD},//SENSOR_GAIN_REG2
904 {0x5912,0x1000},//SENSOR_GAIN_REG2
905 {0x5912,0x0C00},//SENSOR_GAIN_REG2
906 {0x5912,0x0F00},//SENSOR_GAIN_REG2
907 {0x5912,0x1000},//SENSOR_GAIN_REG2
908 {0x5912,0x10F0},//SENSOR_GAIN_REG2
909 {0x5912,0x0075},//SENSOR_GAIN_REG2
910 {0x5912,0x0076},//SENSOR_GAIN_REG2
911 {0x5912,0x0077},//SENSOR_GAIN_REG2
912 {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL
913 {0x5900,0x0000},//SENSOR_GAIN
914 {REG_NULL, 0x00},
915 };
916
917 static const struct regval ar0822_hdr12bit_3840x2160_25fps_regs[] = {
918 {REG_DELAY, 2000},
919 {0x3030,0x007A},//PLL_MULTIPLIER
920 {0x302E,0x0002},//PRE_PLL_CLK_DIV
921 {0x302C,0x0002},//VT_SYS_CLK_DIV
922 {0x302A,0x0005},//VT_PIX_CLK_DIV
923 {0x3038,0x0002},//OP_SYS_CLK_DIV
924 {0x3036,0x0006},//OP_WORD_CLK_DIV
925 {0x31B0,0x00A3},//FRAME_PREAMBLE
926 {0x31B2,0x006C},//LINE_PREAMBLE
927 {0x31B4,0x72CC},//MIPI_TIMING_0
928 {0x31B6,0x73CE},//MIPI_TIMING_1
929 {0x31B8,0xB0CD},//MIPI_TIMING_2
930 {0x31BA,0x0411},//MIPI_TIMING_3
931 {0x31BC,0x550E},//MIPI_TIMING_4
932 {0x3342,0x122C},//MIPI_F1_PDT_EDT
933 {0x31BC,0x550E},//MIPI_TIMING_4
934 {0x31DE,0x0004},//MIPI_HISPI_TRIM
935 {0x31C6,0xC000},//HISPI_CONTROL
936 {0x31C8,0x0B28},//MIPI_DESKEW_PAT_WIDTH
937 {0x2512,0xA000},//SEQ_CTRL_PORT
938 {0x2510,0x0720},//SEQ_DATA_PORT
939 {0x2510,0xFFFF},//SEQ_DATA_PORT
940 {0x2510,0xFFFF},//SEQ_DATA_PORT
941 {0x2510,0xFFFF},//SEQ_DATA_PORT
942 {0x2510,0xFFFF},//SEQ_DATA_PORT
943 {0x2510,0xFFFF},//SEQ_DATA_PORT
944 {0x2510,0xFFFF},//SEQ_DATA_PORT
945 {0x2510,0xFFFF},//SEQ_DATA_PORT
946 {0x2510,0x2122},//SEQ_DATA_PORT
947 {0x2510,0xFFFF},//SEQ_DATA_PORT
948 {0x2510,0xFFFF},//SEQ_DATA_PORT
949 {0x2510,0xFFFF},//SEQ_DATA_PORT
950 {0x2510,0x26FF},//SEQ_DATA_PORT
951 {0x2510,0xFFFF},//SEQ_DATA_PORT
952 {0x2510,0xFFFF},//SEQ_DATA_PORT
953 {0x2510,0xFFFF},//SEQ_DATA_PORT
954 {0x2510,0xFFFF},//SEQ_DATA_PORT
955 {0x2510,0xFFFF},//SEQ_DATA_PORT
956 {0x2510,0xFFFF},//SEQ_DATA_PORT
957 {0x2510,0xFFFF},//SEQ_DATA_PORT
958 {0x2510,0xFFFF},//SEQ_DATA_PORT
959 {0x2510,0xFFFF},//SEQ_DATA_PORT
960 {0x2510,0xFFFF},//SEQ_DATA_PORT
961 {0x2510,0xFFFF},//SEQ_DATA_PORT
962 {0x2510,0xFFFF},//SEQ_DATA_PORT
963 {0x2510,0xFFFF},//SEQ_DATA_PORT
964 {0x2510,0xFFFF},//SEQ_DATA_PORT
965 {0x2510,0xFFFF},//SEQ_DATA_PORT
966 {0x2510,0x20FF},//SEQ_DATA_PORT
967 {0x2510,0x20FF},//SEQ_DATA_PORT
968 {0x2510,0x20FF},//SEQ_DATA_PORT
969 {0x2510,0x20FF},//SEQ_DATA_PORT
970 {0x2510,0x20FF},//SEQ_DATA_PORT
971 {0x2510,0x20FF},//SEQ_DATA_PORT
972 {0x2510,0x20FF},//SEQ_DATA_PORT
973 {0x2510,0x20FF},//SEQ_DATA_PORT
974 {0x2510,0x20FF},//SEQ_DATA_PORT
975 {0x2510,0x20FF},//SEQ_DATA_PORT
976 {0x2510,0x20FF},//SEQ_DATA_PORT
977 {0x2510,0x20FF},//SEQ_DATA_PORT
978 {0x2510,0x20FF},//SEQ_DATA_PORT
979 {0x2510,0x20FF},//SEQ_DATA_PORT
980 {0x2510,0x20FF},//SEQ_DATA_PORT
981 {0x2510,0x20FF},//SEQ_DATA_PORT
982 {0x2510,0x20FF},//SEQ_DATA_PORT
983 {0x2510,0x0F8C},//SEQ_DATA_PORT
984 {0x2510,0x20FF},//SEQ_DATA_PORT
985 {0x2510,0x20FF},//SEQ_DATA_PORT
986 {0x2510,0x20FF},//SEQ_DATA_PORT
987 {0x2510,0x20FF},//SEQ_DATA_PORT
988 {0x2510,0x20FF},//SEQ_DATA_PORT
989 {0x2510,0x20FF},//SEQ_DATA_PORT
990 {0x2510,0x20FF},//SEQ_DATA_PORT
991 {0x2510,0x20FF},//SEQ_DATA_PORT
992 {0x2510,0x20FF},//SEQ_DATA_PORT
993 {0x2510,0x20FF},//SEQ_DATA_PORT
994 {0x2510,0x20FF},//SEQ_DATA_PORT
995 {0x2510,0x20FF},//SEQ_DATA_PORT
996 {0x2510,0x20FF},//SEQ_DATA_PORT
997 {0x2510,0x20FF},//SEQ_DATA_PORT
998 {0x2510,0x20FF},//SEQ_DATA_PORT
999 {0x2510,0x20FF},//SEQ_DATA_PORT
1000 {0x2510,0x20FF},//SEQ_DATA_PORT
1001 {0x2510,0x20FF},//SEQ_DATA_PORT
1002 {0x2510,0x20FF},//SEQ_DATA_PORT
1003 {0x2510,0x20FF},//SEQ_DATA_PORT
1004 {0x2510,0x20FF},//SEQ_DATA_PORT
1005 {0x2510,0x20FF},//SEQ_DATA_PORT
1006 {0x2510,0x20FF},//SEQ_DATA_PORT
1007 {0x2510,0x20E0},//SEQ_DATA_PORT
1008 {0x2510,0x8055},//SEQ_DATA_PORT
1009 {0x2510,0xA0E1},//SEQ_DATA_PORT
1010 {0x2510,0x3041},//SEQ_DATA_PORT
1011 {0x2510,0x2000},//SEQ_DATA_PORT
1012 {0x2510,0x3088},//SEQ_DATA_PORT
1013 {0x2510,0x3282},//SEQ_DATA_PORT
1014 {0x2510,0xA681},//SEQ_DATA_PORT
1015 {0x2510,0x20FF},//SEQ_DATA_PORT
1016 {0x2510,0x20FF},//SEQ_DATA_PORT
1017 {0x2510,0x20FF},//SEQ_DATA_PORT
1018 {0x2510,0x20FF},//SEQ_DATA_PORT
1019 {0x2510,0x20FE},//SEQ_DATA_PORT
1020 {0x2510,0x9070},//SEQ_DATA_PORT
1021 {0x2510,0x891D},//SEQ_DATA_PORT
1022 {0x2510,0x867F},//SEQ_DATA_PORT
1023 {0x2510,0x20FF},//SEQ_DATA_PORT
1024 {0x2510,0x20FC},//SEQ_DATA_PORT
1025 {0x2510,0x893F},//SEQ_DATA_PORT
1026 {0x2510,0x0F92},//SEQ_DATA_PORT
1027 {0x2510,0x20E0},//SEQ_DATA_PORT
1028 {0x2510,0x0F8F},//SEQ_DATA_PORT
1029 {0x2510,0x20FF},//SEQ_DATA_PORT
1030 {0x2510,0x20FF},//SEQ_DATA_PORT
1031 {0x2510,0x20FF},//SEQ_DATA_PORT
1032 {0x2510,0x20FF},//SEQ_DATA_PORT
1033 {0x2510,0x20FF},//SEQ_DATA_PORT
1034 {0x2510,0x20E0},//SEQ_DATA_PORT
1035 {0x2510,0x9770},//SEQ_DATA_PORT
1036 {0x2510,0x20FC},//SEQ_DATA_PORT
1037 {0x2510,0x8054},//SEQ_DATA_PORT
1038 {0x2510,0x896C},//SEQ_DATA_PORT
1039 {0x2510,0x200A},//SEQ_DATA_PORT
1040 {0x2510,0x9030},//SEQ_DATA_PORT
1041 {0x2510,0x200A},//SEQ_DATA_PORT
1042 {0x2510,0x8040},//SEQ_DATA_PORT
1043 {0x2510,0x8948},//SEQ_DATA_PORT
1044 {0x2510,0x200A},//SEQ_DATA_PORT
1045 {0x2510,0x1597},//SEQ_DATA_PORT
1046 {0x2510,0x8808},//SEQ_DATA_PORT
1047 {0x2510,0x200A},//SEQ_DATA_PORT
1048 {0x2510,0x1F96},//SEQ_DATA_PORT
1049 {0x2510,0x20FF},//SEQ_DATA_PORT
1050 {0x2510,0x20E0},//SEQ_DATA_PORT
1051 {0x2510,0xA0C0},//SEQ_DATA_PORT
1052 {0x2510,0x200A},//SEQ_DATA_PORT
1053 {0x2510,0x3044},//SEQ_DATA_PORT
1054 {0x2510,0x3088},//SEQ_DATA_PORT
1055 {0x2510,0x3282},//SEQ_DATA_PORT
1056 {0x2510,0x2004},//SEQ_DATA_PORT
1057 {0x2510,0x1FAA},//SEQ_DATA_PORT
1058 {0x2510,0x20FF},//SEQ_DATA_PORT
1059 {0x2510,0x20FF},//SEQ_DATA_PORT
1060 {0x2510,0x20FF},//SEQ_DATA_PORT
1061 {0x2510,0x20FF},//SEQ_DATA_PORT
1062 {0x2510,0x20E0},//SEQ_DATA_PORT
1063 {0x2510,0x7FFF},//SEQ_DATA_PORT
1064 {0x2510,0x7FFF},//SEQ_DATA_PORT
1065 {0x2510,0x7FFF},//SEQ_DATA_PORT
1066 {0x2510,0x20FF},//SEQ_DATA_PORT
1067 {0x2510,0x7FFF},//SEQ_DATA_PORT
1068 {0x2510,0x7FFF},//SEQ_DATA_PORT
1069 {0x2510,0x7FFF},//SEQ_DATA_PORT
1070 {0x2510,0x3108},//SEQ_DATA_PORT
1071 {0x2510,0x2400},//SEQ_DATA_PORT
1072 {0x2510,0x3244},//SEQ_DATA_PORT
1073 {0x2510,0x7FFF},//SEQ_DATA_PORT
1074 {0x2510,0x3108},//SEQ_DATA_PORT
1075 {0x2510,0x2400},//SEQ_DATA_PORT
1076 {0x2510,0x2702},//SEQ_DATA_PORT
1077 {0x2510,0x3242},//SEQ_DATA_PORT
1078 {0x2510,0x3108},//SEQ_DATA_PORT
1079 {0x2510,0x2420},//SEQ_DATA_PORT
1080 {0x2510,0x2703},//SEQ_DATA_PORT
1081 {0x2510,0x3242},//SEQ_DATA_PORT
1082 {0x2510,0x3108},//SEQ_DATA_PORT
1083 {0x2510,0x2420},//SEQ_DATA_PORT
1084 {0x2510,0x2704},//SEQ_DATA_PORT
1085 {0x2510,0x3244},//SEQ_DATA_PORT
1086 {0x2510,0x7FFF},//SEQ_DATA_PORT
1087 {0x2510,0x7FFF},//SEQ_DATA_PORT
1088 {0x2510,0x7FFF},//SEQ_DATA_PORT
1089 {0x2510,0x7FFF},//SEQ_DATA_PORT
1090 {0x2510,0x8801},//SEQ_DATA_PORT
1091 {0x2510,0x000F},//SEQ_DATA_PORT
1092 {0x2510,0x109C},//SEQ_DATA_PORT
1093 {0x2510,0x8855},//SEQ_DATA_PORT
1094 {0x2510,0x3101},//SEQ_DATA_PORT
1095 {0x2510,0x3041},//SEQ_DATA_PORT
1096 {0x2510,0x2000},//SEQ_DATA_PORT
1097 {0x2510,0x3102},//SEQ_DATA_PORT
1098 {0x2510,0x3041},//SEQ_DATA_PORT
1099 {0x2510,0x2000},//SEQ_DATA_PORT
1100 {0x2510,0x3181},//SEQ_DATA_PORT
1101 {0x2510,0x3041},//SEQ_DATA_PORT
1102 {0x2510,0x2000},//SEQ_DATA_PORT
1103 {0x2510,0x3188},//SEQ_DATA_PORT
1104 {0x2510,0x3041},//SEQ_DATA_PORT
1105 {0x2510,0x2000},//SEQ_DATA_PORT
1106 {0x2510,0x3282},//SEQ_DATA_PORT
1107 {0x2510,0x3104},//SEQ_DATA_PORT
1108 {0x2510,0x2000},//SEQ_DATA_PORT
1109 {0x2510,0xB0E4},//SEQ_DATA_PORT
1110 {0x2510,0xAD92},//SEQ_DATA_PORT
1111 {0x2510,0xBC0C},//SEQ_DATA_PORT
1112 {0x2510,0x1028},//SEQ_DATA_PORT
1113 {0x2510,0x0022},//SEQ_DATA_PORT
1114 {0x2510,0xC020},//SEQ_DATA_PORT
1115 {0x2510,0x003E},//SEQ_DATA_PORT
1116 {0x2510,0x0045},//SEQ_DATA_PORT
1117 {0x2510,0x00B0},//SEQ_DATA_PORT
1118 {0x2510,0x0028},//SEQ_DATA_PORT
1119 {0x2510,0x30C1},//SEQ_DATA_PORT
1120 {0x2510,0x8015},//SEQ_DATA_PORT
1121 {0x2510,0xA038},//SEQ_DATA_PORT
1122 {0x2510,0x100F},//SEQ_DATA_PORT
1123 {0x2510,0x0507},//SEQ_DATA_PORT
1124 {0x2510,0xA220},//SEQ_DATA_PORT
1125 {0x2510,0x0010},//SEQ_DATA_PORT
1126 {0x2510,0x10C2},//SEQ_DATA_PORT
1127 {0x2510,0xB760},//SEQ_DATA_PORT
1128 {0x2510,0x0033},//SEQ_DATA_PORT
1129 {0x2510,0x1082},//SEQ_DATA_PORT
1130 {0x2510,0x100B},//SEQ_DATA_PORT
1131 {0x2510,0x1029},//SEQ_DATA_PORT
1132 {0x2510,0xA85A},//SEQ_DATA_PORT
1133 {0x2510,0x998D},//SEQ_DATA_PORT
1134 {0x2510,0xC810},//SEQ_DATA_PORT
1135 {0x2510,0x2004},//SEQ_DATA_PORT
1136 {0x2510,0x0ECE},//SEQ_DATA_PORT
1137 {0x2510,0x123B},//SEQ_DATA_PORT
1138 {0x2510,0xC000},//SEQ_DATA_PORT
1139 {0x2510,0x032F},//SEQ_DATA_PORT
1140 {0x2510,0x11D5},//SEQ_DATA_PORT
1141 {0x2510,0x162F},//SEQ_DATA_PORT
1142 {0x2510,0x9000},//SEQ_DATA_PORT
1143 {0x2510,0x2034},//SEQ_DATA_PORT
1144 {0x2510,0x0015},//SEQ_DATA_PORT
1145 {0x2510,0x04CB},//SEQ_DATA_PORT
1146 {0x2510,0x1022},//SEQ_DATA_PORT
1147 {0x2510,0x1031},//SEQ_DATA_PORT
1148 {0x2510,0x002D},//SEQ_DATA_PORT
1149 {0x2510,0x1015},//SEQ_DATA_PORT
1150 {0x2510,0x80B9},//SEQ_DATA_PORT
1151 {0x2510,0xA101},//SEQ_DATA_PORT
1152 {0x2510,0x001C},//SEQ_DATA_PORT
1153 {0x2510,0x008E},//SEQ_DATA_PORT
1154 {0x2510,0x124B},//SEQ_DATA_PORT
1155 {0x2510,0x01B5},//SEQ_DATA_PORT
1156 {0x2510,0x0B92},//SEQ_DATA_PORT
1157 {0x2510,0xA400},//SEQ_DATA_PORT
1158 {0x2510,0x8091},//SEQ_DATA_PORT
1159 {0x2510,0x0028},//SEQ_DATA_PORT
1160 {0x2510,0x3002},//SEQ_DATA_PORT
1161 {0x2510,0x2004},//SEQ_DATA_PORT
1162 {0x2510,0x1012},//SEQ_DATA_PORT
1163 {0x2510,0x100E},//SEQ_DATA_PORT
1164 {0x2510,0x10A8},//SEQ_DATA_PORT
1165 {0x2510,0x00A1},//SEQ_DATA_PORT
1166 {0x2510,0x132D},//SEQ_DATA_PORT
1167 {0x2510,0x09AF},//SEQ_DATA_PORT
1168 {0x2510,0x0159},//SEQ_DATA_PORT
1169 {0x2510,0x121D},//SEQ_DATA_PORT
1170 {0x2510,0x1259},//SEQ_DATA_PORT
1171 {0x2510,0x11AF},//SEQ_DATA_PORT
1172 {0x2510,0x18B5},//SEQ_DATA_PORT
1173 {0x2510,0x0395},//SEQ_DATA_PORT
1174 {0x2510,0x054B},//SEQ_DATA_PORT
1175 {0x2510,0x1021},//SEQ_DATA_PORT
1176 {0x2510,0x0020},//SEQ_DATA_PORT
1177 {0x2510,0x1015},//SEQ_DATA_PORT
1178 {0x2510,0x1030},//SEQ_DATA_PORT
1179 {0x2510,0x00CF},//SEQ_DATA_PORT
1180 {0x2510,0xB146},//SEQ_DATA_PORT
1181 {0x2510,0xC290},//SEQ_DATA_PORT
1182 {0x2510,0x103C},//SEQ_DATA_PORT
1183 {0x2510,0xA882},//SEQ_DATA_PORT
1184 {0x2510,0x8055},//SEQ_DATA_PORT
1185 {0x2510,0x00A9},//SEQ_DATA_PORT
1186 {0x2510,0x8801},//SEQ_DATA_PORT
1187 {0x2510,0xB700},//SEQ_DATA_PORT
1188 {0x2510,0x0001},//SEQ_DATA_PORT
1189 {0x2510,0x02A2},//SEQ_DATA_PORT
1190 {0x2510,0x000A},//SEQ_DATA_PORT
1191 {0x2510,0x98BB},//SEQ_DATA_PORT
1192 {0x2510,0x203F},//SEQ_DATA_PORT
1193 {0x2510,0x0036},//SEQ_DATA_PORT
1194 {0x2510,0x1001},//SEQ_DATA_PORT
1195 {0x2510,0x99BE},//SEQ_DATA_PORT
1196 {0x2510,0x0139},//SEQ_DATA_PORT
1197 {0x2510,0x100A},//SEQ_DATA_PORT
1198 {0x2510,0x0040},//SEQ_DATA_PORT
1199 {0x2510,0x1022},//SEQ_DATA_PORT
1200 {0x2510,0x124C},//SEQ_DATA_PORT
1201 {0x2510,0x109F},//SEQ_DATA_PORT
1202 {0x2510,0x15A3},//SEQ_DATA_PORT
1203 {0x2510,0x002A},//SEQ_DATA_PORT
1204 {0x2510,0x3081},//SEQ_DATA_PORT
1205 {0x2510,0x2001},//SEQ_DATA_PORT
1206 {0x2510,0x3044},//SEQ_DATA_PORT
1207 {0x2510,0x2000},//SEQ_DATA_PORT
1208 {0x2510,0x112A},//SEQ_DATA_PORT
1209 {0x2510,0x101D},//SEQ_DATA_PORT
1210 {0x2510,0x202B},//SEQ_DATA_PORT
1211 {0x2510,0x02B8},//SEQ_DATA_PORT
1212 {0x2510,0x10B8},//SEQ_DATA_PORT
1213 {0x2510,0x1136},//SEQ_DATA_PORT
1214 {0x2510,0x996B},//SEQ_DATA_PORT
1215 {0x2510,0x004C},//SEQ_DATA_PORT
1216 {0x2510,0x1039},//SEQ_DATA_PORT
1217 {0x2510,0x1040},//SEQ_DATA_PORT
1218 {0x2510,0x00B5},//SEQ_DATA_PORT
1219 {0x2510,0x03C4},//SEQ_DATA_PORT
1220 {0x2510,0x1144},//SEQ_DATA_PORT
1221 {0x2510,0x1245},//SEQ_DATA_PORT
1222 {0x2510,0x9A7B},//SEQ_DATA_PORT
1223 {0x2510,0x002B},//SEQ_DATA_PORT
1224 {0x2510,0x30D0},//SEQ_DATA_PORT
1225 {0x2510,0x3141},//SEQ_DATA_PORT
1226 {0x2510,0x3041},//SEQ_DATA_PORT
1227 {0x2510,0x2000},//SEQ_DATA_PORT
1228 {0x2510,0x3142},//SEQ_DATA_PORT
1229 {0x2510,0x3041},//SEQ_DATA_PORT
1230 {0x2510,0x2000},//SEQ_DATA_PORT
1231 {0x2510,0x3110},//SEQ_DATA_PORT
1232 {0x2510,0x3041},//SEQ_DATA_PORT
1233 {0x2510,0x2000},//SEQ_DATA_PORT
1234 {0x2510,0x3120},//SEQ_DATA_PORT
1235 {0x2510,0x3041},//SEQ_DATA_PORT
1236 {0x2510,0x2000},//SEQ_DATA_PORT
1237 {0x2510,0x3144},//SEQ_DATA_PORT
1238 {0x2510,0x3041},//SEQ_DATA_PORT
1239 {0x2510,0x2000},//SEQ_DATA_PORT
1240 {0x2510,0x3148},//SEQ_DATA_PORT
1241 {0x2510,0x3041},//SEQ_DATA_PORT
1242 {0x2510,0x2000},//SEQ_DATA_PORT
1243 {0x2510,0x3182},//SEQ_DATA_PORT
1244 {0x2510,0x3041},//SEQ_DATA_PORT
1245 {0x2510,0x2000},//SEQ_DATA_PORT
1246 {0x2510,0x3184},//SEQ_DATA_PORT
1247 {0x2510,0x2000},//SEQ_DATA_PORT
1248 {0x2510,0x3190},//SEQ_DATA_PORT
1249 {0x2510,0x3041},//SEQ_DATA_PORT
1250 {0x2510,0x2000},//SEQ_DATA_PORT
1251 {0x2510,0x31A0},//SEQ_DATA_PORT
1252 {0x2510,0x3088},//SEQ_DATA_PORT
1253 {0x2510,0x2201},//SEQ_DATA_PORT
1254 {0x2510,0x807D},//SEQ_DATA_PORT
1255 {0x2510,0x2206},//SEQ_DATA_PORT
1256 {0x2510,0x8815},//SEQ_DATA_PORT
1257 {0x2510,0x8877},//SEQ_DATA_PORT
1258 {0x2510,0x0092},//SEQ_DATA_PORT
1259 {0x2510,0x220E},//SEQ_DATA_PORT
1260 {0x2510,0x2211},//SEQ_DATA_PORT
1261 {0x2510,0x8055},//SEQ_DATA_PORT
1262 {0x2510,0x3001},//SEQ_DATA_PORT
1263 {0x2510,0x2000},//SEQ_DATA_PORT
1264 {0x2510,0x8A61},//SEQ_DATA_PORT
1265 {0x2510,0x8801},//SEQ_DATA_PORT
1266 {0x2510,0x1092},//SEQ_DATA_PORT
1267 {0x2510,0x181F},//SEQ_DATA_PORT
1268 {0x2510,0x0B1F},//SEQ_DATA_PORT
1269 {0x2510,0x101F},//SEQ_DATA_PORT
1270 {0x2510,0x00B6},//SEQ_DATA_PORT
1271 {0x2510,0x0023},//SEQ_DATA_PORT
1272 {0x2510,0x00B9},//SEQ_DATA_PORT
1273 {0x2510,0x104C},//SEQ_DATA_PORT
1274 {0x2510,0x996E},//SEQ_DATA_PORT
1275 {0x2510,0x0140},//SEQ_DATA_PORT
1276 {0x2510,0x0257},//SEQ_DATA_PORT
1277 {0x2510,0x1035},//SEQ_DATA_PORT
1278 {0x2510,0x9F26},//SEQ_DATA_PORT
1279 {0x2510,0x1423},//SEQ_DATA_PORT
1280 {0x2510,0x0048},//SEQ_DATA_PORT
1281 {0x2510,0xC878},//SEQ_DATA_PORT
1282 {0x2510,0x200A},//SEQ_DATA_PORT
1283 {0x2510,0x1548},//SEQ_DATA_PORT
1284 {0x2510,0x0C49},//SEQ_DATA_PORT
1285 {0x2510,0x1149},//SEQ_DATA_PORT
1286 {0x2510,0x002A},//SEQ_DATA_PORT
1287 {0x2510,0x1057},//SEQ_DATA_PORT
1288 {0x2510,0x3281},//SEQ_DATA_PORT
1289 {0x2510,0x2000},//SEQ_DATA_PORT
1290 {0x2510,0x3044},//SEQ_DATA_PORT
1291 {0x2510,0x2001},//SEQ_DATA_PORT
1292 {0x2510,0xA020},//SEQ_DATA_PORT
1293 {0x2510,0x000C},//SEQ_DATA_PORT
1294 {0x2510,0x9825},//SEQ_DATA_PORT
1295 {0x2510,0x1040},//SEQ_DATA_PORT
1296 {0x2510,0x1054},//SEQ_DATA_PORT
1297 {0x2510,0xB06D},//SEQ_DATA_PORT
1298 {0x2510,0x0035},//SEQ_DATA_PORT
1299 {0x2510,0x004D},//SEQ_DATA_PORT
1300 {0x2510,0x9905},//SEQ_DATA_PORT
1301 {0x2510,0xB064},//SEQ_DATA_PORT
1302 {0x2510,0x99C5},//SEQ_DATA_PORT
1303 {0x2510,0x0047},//SEQ_DATA_PORT
1304 {0x2510,0xB920},//SEQ_DATA_PORT
1305 {0x2510,0x1447},//SEQ_DATA_PORT
1306 {0x2510,0x7FFF},//SEQ_DATA_PORT
1307 {0x2510,0x7FFF},//SEQ_DATA_PORT
1308 {0x2510,0x7FFF},//SEQ_DATA_PORT
1309 {0x2510,0x7FFF},//SEQ_DATA_PORT
1310 {0x2510,0x7FFF},//SEQ_DATA_PORT
1311 {0x2510,0x7FFF},//SEQ_DATA_PORT
1312 {0x2510,0x7FFF},//SEQ_DATA_PORT
1313 {0x2510,0x7FFF},//SEQ_DATA_PORT
1314 {0x2510,0x7FFF},//SEQ_DATA_PORT
1315 {0x31F8,0x0008},//MIPI_CONFIG_2
1316 {0x3C70,0x6828},//CALIB_ROWS
1317 {0x3092,0x0826},//ROW_NOISE_CONTROL
1318 {0x3428,0x0209},//SEQUENCER_CONTROL
1319 {0x3516,0xFF04},//DAC_LD_22_23
1320 {0x3526,0x6480},//DAC_LD_38_39
1321 {0x3504,0x8AAA},//DAC_LD_4_5
1322 {0x353C,0x220C},//DAC_LD_60_61
1323 {0x3536,0x4C6E},//DAC_LD_54_55
1324 {0x3D2A,0x0FFF},//T1_END_DEC_TH
1325 {0x3364,0x00EC},//DCG_TRIM
1326 {0x3512,0x8888},//DAC_LD_18_19
1327 {0x3514,0x888F},//DAC_LD_20_21
1328 {0x3520,0xFBF0},//DAC_LD_32_33
1329 {0x3524,0xB2A1},//DAC_LD_36_37
1330 {0x3528,0xCC84},//DAC_LD_40_41
1331 {0x3532,0x4C8E},//DAC_LD_50_51
1332 {0x3534,0x4E64},//DAC_LD_52_53
1333 {0x351E,0x5856},//DAC_LD_30_31
1334 {0x353E,0x98F2},//DAC_LD_62_63
1335 {0x352E,0x6A8A},//DAC_LD_46_47
1336 {0x3370,0x0211},//DBLC_CONTROL
1337 {0x3372,0x700F},//DBLC_FS0_CONTROL
1338 {0x3540,0x3597},//DAC_LD_64_65
1339 {0x58E2,0x0BE3},//COL_COUNT_VALUES1
1340 {0x58E4,0x18B4},//COL_COUNT_VALUES2
1341 {0x3522,0x7C97},//DAC_LD_34_35
1342 {0x30BA,0x0024},//DIGITAL_CTRL
1343 {0x31D4,0x0042},//CLK_MEM_GATING_CTRL
1344 {0x352A,0x6F8F},//DAC_LD_42_43
1345 {0x3530,0x4A08},//DAC_LD_48_49
1346 {0x351A,0x5FFF},//DAC_LD_26_27
1347 {0x350E,0x39D9},//DAC_LD_14_15
1348 {0x3510,0x9988},//DAC_LD_16_17
1349 {0x3380,0x1FFF},//DBLC_OFFSET1
1350 {0x337A,0x1000},//DBLC_SCALE1
1351 {0x3092,0x0800},//ROW_NOISE_CONTROL
1352 {0x350A,0x0654},//DAC_LD_10_11
1353 {0x3364,0x00E0},//DCG_TRIM
1354 {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA
1355 {0x591E,0x722C},//ANALOG_GAIN_WR_DATA
1356 {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA
1357 {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA
1358 {0x591E,0xA447},//ANALOG_GAIN_WR_DATA
1359 {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA
1360 {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA
1361 {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA
1362 {0x3532,0x4C8A},//DAC_LD_50_51
1363 {0x3534,0x4E60},//DAC_LD_52_53
1364 {0x353E,0x90F2},//DAC_LD_62_63
1365 {0x351A,0x4FFF},//DAC_LD_26_27
1366 {0x591C,0x00D7},//DGR_AMP_GAIN
1367 {0x3522,0x6097},//DAC_LD_34_35
1368 {0x5002,0x37C3},//T1_PIX_DEF_ID2
1369 {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0
1370 {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1
1371 {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2
1372 {0x51D0,0x0001},//T1_NOISE_FLOOR0
1373 {0x51D2,0x0002},//T1_NOISE_FLOOR1
1374 {0x51D4,0x0003},//T1_NOISE_FLOOR2
1375 {0x51D6,0x0004},//T1_NOISE_FLOOR3
1376 {0x5202,0x37C3},//T2_PIX_DEF_ID2
1377 {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0
1378 {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1
1379 {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2
1380 {0x51EE,0x0001},//T2_NOISE_FLOOR0
1381 {0x51F0,0x0002},//T2_NOISE_FLOOR1
1382 {0x51F2,0x0003},//T2_NOISE_FLOOR2
1383 {0x51F4,0x0004},//T2_NOISE_FLOOR3
1384 {0x5402,0x37C3},//T4_PIX_DEF_ID2
1385 {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0
1386 {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1
1387 {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2
1388 {0x5564,0x0001},//T4_NOISE_FLOOR0
1389 {0x5566,0x0002},//T4_NOISE_FLOOR1
1390 {0x5568,0x0003},//T4_NOISE_FLOOR2
1391 {0x556A,0x0004},//T4_NOISE_FLOOR3
1392 {0x31E0,0x0001},//PIX_DEF_ID
1393 {0x5000,0x0080},//T1_PIX_DEF_ID
1394 {0x5000,0x0180},//T1_PIX_DEF_ID
1395 {0x5000,0x0180},//T1_PIX_DEF_ID
1396 {0x5200,0x0080},//T2_PIX_DEF_ID
1397 {0x5200,0x0180},//T2_PIX_DEF_ID
1398 {0x5200,0x0180},//T2_PIX_DEF_ID
1399 {0x5400,0x0080},//T4_PIX_DEF_ID
1400 {0x5400,0x0180},//T4_PIX_DEF_ID
1401 {0x5400,0x0180},//T4_PIX_DEF_ID
1402 {0x5000,0x0180},//T1_PIX_DEF_ID
1403 {0x5200,0x0180},//T2_PIX_DEF_ID
1404 {0x5400,0x0180},//T4_PIX_DEF_ID
1405 {0x50A2,0x3F2A},//BMT0
1406 {0x50A4,0x875A},//BMT1
1407 {0x50A6,0x030F},//SINGLEK_FACTOR0
1408 {0x50A6,0x0F0F},//SINGLEK_FACTOR0
1409 {0x50A8,0x030F},//SINGLEK_FACTOR1
1410 {0x50A8,0x0F0F},//SINGLEK_FACTOR1
1411 {0x50AA,0x030F},//SINGLEK_FACTOR2
1412 {0x50AA,0x050F},//SINGLEK_FACTOR2
1413 {0x50AC,0x0301},//CROSS_FACTOR0
1414 {0x50AC,0x0101},//CROSS_FACTOR0
1415 {0x50AE,0x0301},//CROSS_FACTOR1
1416 {0x50AE,0x0101},//CROSS_FACTOR1
1417 {0x50B0,0x0301},//CROSS_FACTOR2
1418 {0x50B0,0x0101},//CROSS_FACTOR2
1419 {0x50B2,0x03FF},//SINGLE_MAX_FACTOR
1420 {0x50B4,0x030F},//COUPLE_FACTOR0
1421 {0x50B4,0x0F0F},//COUPLE_FACTOR0
1422 {0x50B6,0x030F},//COUPLE_FACTOR1
1423 {0x50B6,0x0F0F},//COUPLE_FACTOR1
1424 {0x50B8,0x030F},//COUPLE_FACTOR2
1425 {0x50B8,0x050F},//COUPLE_FACTOR2
1426 {0x3D2A,0x0FFF},//T1_END_DEC_TH
1427 {0x3D34,0x9C40},//T2_STR_DEC_TH
1428 {0x3D36,0xFFFF},//T2_END_DEC_TH
1429 {0x3D02,0x5033},//MEC_CTRL2
1430 {0x3086,0x1A28},//PARK_ROW_ADDR
1431 {0x33E4,0x0040},//VERT_SHADING_CONTROL
1432 {0x3C70,0x6222},//CALIB_ROWS
1433 {0x3110,0x0011},//HDR_CONTROL0
1434 {0x30B0,0x0820},//DIGITAL_TEST
1435 {0x3280,0x0ED8},//T1_BARRIER_C0
1436 {0x3282,0x0ED8},//T1_BARRIER_C1
1437 {0x3284,0x0ED8},//T1_BARRIER_C2
1438 {0x3286,0x0ED8},//T1_BARRIER_C3
1439 {0x3288,0x0ED8},//T2_BARRIER_C0
1440 {0x328A,0x0ED8},//T2_BARRIER_C1
1441 {0x328C,0x0ED8},//T2_BARRIER_C2
1442 {0x328E,0x0ED8},//T2_BARRIER_C3
1443 {0x3290,0x0ED8},//T3_BARRIER_C0
1444 {0x3292,0x0ED8},//T3_BARRIER_C1
1445 {0x3294,0x0ED8},//T3_BARRIER_C2
1446 {0x3296,0x0ED8},//T3_BARRIER_C3
1447 {0x3100,0xC001},//DLO_CONTROL0
1448 {0x3102,0xBED8},//DLO_CONTROL1
1449 {0x3104,0xBED8},//DLO_CONTROL2
1450 {0x3106,0xBED8},//DLO_CONTROL3
1451 {0x3108,0x07D0},//DLO_CONTROL4
1452 {0x3116,0x2001},//HDR_CONTROL3
1453 {0x3124,0x006D},//HDR_MD_CONTROL0
1454 {0x3126,0x003C},//HDR_MD_CONTROL1
1455 {0x31AE,0x0204},//SERIAL_FORMAT
1456 {0x31AC,0x0C0C},//DATA_FORMAT_BITS
1457 {0x3082,0x0014},//OPERATION_MODE_CTRL
1458 {0x30BA,0x0135},//DIGITAL_CTRL
1459 {0x3238,0x0044},//EXPOSURE_RATIO
1460 {0x3012,0x07A0},//COARSE_INTEGRATION_TIME_
1461 {0x3212,0x007A},//COARSE_INTEGRATION_TIME2
1462 {0x300C,0x0A8C},//LINE_LENGTH_PCK_
1463 {0x300A,0x0980},//FRAME_LENGTH_LINES_
1464 {0x5914,0x4012},//SENSOR_GAIN_TABLE_SEL
1465 {REG_DELAY,100},
1466 {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL
1467 {0x5910,0x608A},//SENSOR_GAIN_REG1
1468 {0x5910,0x7091},//SENSOR_GAIN_REG1
1469 {0x5910,0x689C},//SENSOR_GAIN_REG1
1470 {0x5910,0x8885},//SENSOR_GAIN_REG1
1471 {0x5910,0x98AD},//SENSOR_GAIN_REG1
1472 {0x5910,0xA8A9},//SENSOR_GAIN_REG1
1473 {0x5910,0xC894},//SENSOR_GAIN_REG1
1474 {0x5910,0xC8D1},//SENSOR_GAIN_REG1
1475 {0x5910,0xD88A},//SENSOR_GAIN_REG1
1476 {0x5910,0xD8C3},//SENSOR_GAIN_REG1
1477 {0x5910,0xD915},//SENSOR_GAIN_REG1
1478 {0x5910,0xD988},//SENSOR_GAIN_REG1
1479 {0x5910,0xDA2A},//SENSOR_GAIN_REG1
1480 {0x5910,0xDB0E},//SENSOR_GAIN_REG1
1481 {0x5910,0xDC53},//SENSOR_GAIN_REG1
1482 {0x5910,0x608A},//SENSOR_GAIN_REG1
1483 {0x5910,0xC919},//SENSOR_GAIN_REG1
1484 {0x5910,0xCA00},//SENSOR_GAIN_REG1
1485 {0x5910,0x0000},//SENSOR_GAIN_REG1
1486 {0x5910,0x0000},//SENSOR_GAIN_REG1
1487 {0x5910,0x0000},//SENSOR_GAIN_REG1
1488 {0x5910,0x0001},//SENSOR_GAIN_REG1
1489 {0x5910,0x0001},//SENSOR_GAIN_REG1
1490 {0x5910,0x0003},//SENSOR_GAIN_REG1
1491 {0x5910,0x0003},//SENSOR_GAIN_REG1
1492 {0x5910,0x0003},//SENSOR_GAIN_REG1
1493 {0x5910,0x0004},//SENSOR_GAIN_REG1
1494 {0x5910,0x0004},//SENSOR_GAIN_REG1
1495 {0x5910,0x0004},//SENSOR_GAIN_REG1
1496 {0x5910,0x0004},//SENSOR_GAIN_REG1
1497 {0x5910,0x0004},//SENSOR_GAIN_REG1
1498 {0x5910,0x0004},//SENSOR_GAIN_REG1
1499 {0x5910,0x0004},//SENSOR_GAIN_REG1
1500 {0x5910,0x0002},//SENSOR_GAIN_REG1
1501 {0x5910,0x0003},//SENSOR_GAIN_REG1
1502 {0x5910,0x0003},//SENSOR_GAIN_REG1
1503 {0x5910,0x5A8B},//SENSOR_GAIN_REG1
1504 {0x5910,0xFF04},//SENSOR_GAIN_REG1
1505 {0x5910,0xF704},//SENSOR_GAIN_REG1
1506 {0x5910,0xFF04},//SENSOR_GAIN_REG1
1507 {0x5910,0xF704},//SENSOR_GAIN_REG1
1508 {0x5910,0xF704},//SENSOR_GAIN_REG1
1509 {0x5910,0x0005},//SENSOR_GAIN_REG1
1510 {0x5910,0x0006},//SENSOR_GAIN_REG1
1511 {0x5910,0x0007},//SENSOR_GAIN_REG1
1512 {0x5910,0x9A8B},//SENSOR_GAIN_REG1
1513 {0x5910,0xFF04},//SENSOR_GAIN_REG1
1514 {0x5910,0xF704},//SENSOR_GAIN_REG1
1515 {0x5910,0xF704},//SENSOR_GAIN_REG1
1516 {0x5910,0xF704},//SENSOR_GAIN_REG1
1517 {0x5910,0xF704},//SENSOR_GAIN_REG1
1518 {0x5910,0x0015},//SENSOR_GAIN_REG1
1519 {0x5910,0x0016},//SENSOR_GAIN_REG1
1520 {0x5910,0x0017},//SENSOR_GAIN_REG1
1521 {0x5910,0xDA8B},//SENSOR_GAIN_REG1
1522 {0x5910,0xFF04},//SENSOR_GAIN_REG1
1523 {0x5910,0xF704},//SENSOR_GAIN_REG1
1524 {0x5910,0xF704},//SENSOR_GAIN_REG1
1525 {0x5910,0xF704},//SENSOR_GAIN_REG1
1526 {0x5910,0xF704},//SENSOR_GAIN_REG1
1527 {0x5910,0x0025},//SENSOR_GAIN_REG1
1528 {0x5910,0x0026},//SENSOR_GAIN_REG1
1529 {0x5910,0x0027},//SENSOR_GAIN_REG1
1530 {0x5910,0x59B9},//SENSOR_GAIN_REG1
1531 {0x5910,0x700F},//SENSOR_GAIN_REG1
1532 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1533 {0x5910,0x700F},//SENSOR_GAIN_REG1
1534 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1535 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1536 {0x5910,0x0035},//SENSOR_GAIN_REG1
1537 {0x5910,0x0036},//SENSOR_GAIN_REG1
1538 {0x5910,0x0037},//SENSOR_GAIN_REG1
1539 {0x5910,0x99B9},//SENSOR_GAIN_REG1
1540 {0x5910,0x700F},//SENSOR_GAIN_REG1
1541 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1542 {0x5910,0x700F},//SENSOR_GAIN_REG1
1543 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1544 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1545 {0x5910,0x0045},//SENSOR_GAIN_REG1
1546 {0x5910,0x0046},//SENSOR_GAIN_REG1
1547 {0x5910,0x0047},//SENSOR_GAIN_REG1
1548 {0x5910,0xD9B9},//SENSOR_GAIN_REG1
1549 {0x5910,0x700F},//SENSOR_GAIN_REG1
1550 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1551 {0x5910,0x700F},//SENSOR_GAIN_REG1
1552 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1553 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
1554 {0x5910,0x0055},//SENSOR_GAIN_REG1
1555 {0x5910,0x0056},//SENSOR_GAIN_REG1
1556 {0x5910,0x0057},//SENSOR_GAIN_REG1
1557 {0x5910,0x9A85},//SENSOR_GAIN_REG1
1558 {0x5910,0x0654},//SENSOR_GAIN_REG1
1559 {0x5910,0x0654},//SENSOR_GAIN_REG1
1560 {0x5910,0x0684},//SENSOR_GAIN_REG1
1561 {0x5910,0x0654},//SENSOR_GAIN_REG1
1562 {0x5910,0x0654},//SENSOR_GAIN_REG1
1563 {0x5910,0x0065},//SENSOR_GAIN_REG1
1564 {0x5910,0x0066},//SENSOR_GAIN_REG1
1565 {0x5910,0x0067},//SENSOR_GAIN_REG1
1566 {0x5910,0x59BD},//SENSOR_GAIN_REG1
1567 {0x5910,0x1000},//SENSOR_GAIN_REG1
1568 {0x5910,0x0C00},//SENSOR_GAIN_REG1
1569 {0x5910,0x0F00},//SENSOR_GAIN_REG1
1570 {0x5910,0x1000},//SENSOR_GAIN_REG1
1571 {0x5910,0x10F0},//SENSOR_GAIN_REG1
1572 {0x5910,0x0075},//SENSOR_GAIN_REG1
1573 {0x5910,0x0076},//SENSOR_GAIN_REG1
1574 {0x5910,0x0077},//SENSOR_GAIN_REG1
1575 {0x5912,0x608A},//SENSOR_GAIN_REG2
1576 {0x5912,0x7091},//SENSOR_GAIN_REG2
1577 {0x5912,0x689C},//SENSOR_GAIN_REG2
1578 {0x5912,0x8885},//SENSOR_GAIN_REG2
1579 {0x5912,0x98AD},//SENSOR_GAIN_REG2
1580 {0x5912,0xA8A9},//SENSOR_GAIN_REG2
1581 {0x5912,0xC894},//SENSOR_GAIN_REG2
1582 {0x5912,0xC8D1},//SENSOR_GAIN_REG2
1583 {0x5912,0xC927},//SENSOR_GAIN_REG2
1584 {0x5912,0xC9A0},//SENSOR_GAIN_REG2
1585 {0x5912,0xCA4C},//SENSOR_GAIN_REG2
1586 {0x5912,0xCB3F},//SENSOR_GAIN_REG2
1587 {0x5912,0xCC97},//SENSOR_GAIN_REG2
1588 {0x5912,0xCE7C},//SENSOR_GAIN_REG2
1589 {0x5912,0xCFFF},//SENSOR_GAIN_REG2
1590 {0x5912,0x608A},//SENSOR_GAIN_REG2
1591 {0x5912,0xC8F0},//SENSOR_GAIN_REG2
1592 {0x5912,0xCA00},//SENSOR_GAIN_REG2
1593 {0x5912,0x0000},//SENSOR_GAIN_REG2
1594 {0x5912,0x0000},//SENSOR_GAIN_REG2
1595 {0x5912,0x0000},//SENSOR_GAIN_REG2
1596 {0x5912,0x0001},//SENSOR_GAIN_REG2
1597 {0x5912,0x0001},//SENSOR_GAIN_REG2
1598 {0x5912,0x0003},//SENSOR_GAIN_REG2
1599 {0x5912,0x0003},//SENSOR_GAIN_REG2
1600 {0x5912,0x0003},//SENSOR_GAIN_REG2
1601 {0x5912,0x0004},//SENSOR_GAIN_REG2
1602 {0x5912,0x0004},//SENSOR_GAIN_REG2
1603 {0x5912,0x0004},//SENSOR_GAIN_REG2
1604 {0x5912,0x0004},//SENSOR_GAIN_REG2
1605 {0x5912,0x0004},//SENSOR_GAIN_REG2
1606 {0x5912,0x0004},//SENSOR_GAIN_REG2
1607 {0x5912,0x0004},//SENSOR_GAIN_REG2
1608 {0x5912,0x0002},//SENSOR_GAIN_REG2
1609 {0x5912,0x0003},//SENSOR_GAIN_REG2
1610 {0x5912,0x0003},//SENSOR_GAIN_REG2
1611 {0x5912,0x5A8B},//SENSOR_GAIN_REG2
1612 {0x5912,0xFF04},//SENSOR_GAIN_REG2
1613 {0x5912,0xF704},//SENSOR_GAIN_REG2
1614 {0x5912,0xFF04},//SENSOR_GAIN_REG2
1615 {0x5912,0xF704},//SENSOR_GAIN_REG2
1616 {0x5912,0xF704},//SENSOR_GAIN_REG2
1617 {0x5912,0x0005},//SENSOR_GAIN_REG2
1618 {0x5912,0x0006},//SENSOR_GAIN_REG2
1619 {0x5912,0x0007},//SENSOR_GAIN_REG2
1620 {0x5912,0x9A8B},//SENSOR_GAIN_REG2
1621 {0x5912,0xFF04},//SENSOR_GAIN_REG2
1622 {0x5912,0xF704},//SENSOR_GAIN_REG2
1623 {0x5912,0xF704},//SENSOR_GAIN_REG2
1624 {0x5912,0xF704},//SENSOR_GAIN_REG2
1625 {0x5912,0xF704},//SENSOR_GAIN_REG2
1626 {0x5912,0x0015},//SENSOR_GAIN_REG2
1627 {0x5912,0x0016},//SENSOR_GAIN_REG2
1628 {0x5912,0x0017},//SENSOR_GAIN_REG2
1629 {0x5912,0xDA8B},//SENSOR_GAIN_REG2
1630 {0x5912,0xFF04},//SENSOR_GAIN_REG2
1631 {0x5912,0xF704},//SENSOR_GAIN_REG2
1632 {0x5912,0xF704},//SENSOR_GAIN_REG2
1633 {0x5912,0xF704},//SENSOR_GAIN_REG2
1634 {0x5912,0xF704},//SENSOR_GAIN_REG2
1635 {0x5912,0x0025},//SENSOR_GAIN_REG2
1636 {0x5912,0x0026},//SENSOR_GAIN_REG2
1637 {0x5912,0x0027},//SENSOR_GAIN_REG2
1638 {0x5912,0x59B9},//SENSOR_GAIN_REG2
1639 {0x5912,0x700F},//SENSOR_GAIN_REG2
1640 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1641 {0x5912,0x700F},//SENSOR_GAIN_REG2
1642 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1643 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1644 {0x5912,0x0035},//SENSOR_GAIN_REG2
1645 {0x5912,0x0036},//SENSOR_GAIN_REG2
1646 {0x5912,0x0037},//SENSOR_GAIN_REG2
1647 {0x5912,0x99B9},//SENSOR_GAIN_REG2
1648 {0x5912,0x700F},//SENSOR_GAIN_REG2
1649 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1650 {0x5912,0x700F},//SENSOR_GAIN_REG2
1651 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1652 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1653 {0x5912,0x0045},//SENSOR_GAIN_REG2
1654 {0x5912,0x0046},//SENSOR_GAIN_REG2
1655 {0x5912,0x0047},//SENSOR_GAIN_REG2
1656 {0x5912,0xD9B9},//SENSOR_GAIN_REG2
1657 {0x5912,0x700F},//SENSOR_GAIN_REG2
1658 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1659 {0x5912,0x700F},//SENSOR_GAIN_REG2
1660 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1661 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
1662 {0x5912,0x0055},//SENSOR_GAIN_REG2
1663 {0x5912,0x0056},//SENSOR_GAIN_REG2
1664 {0x5912,0x0057},//SENSOR_GAIN_REG2
1665 {0x5912,0x9A85},//SENSOR_GAIN_REG2
1666 {0x5912,0x0654},//SENSOR_GAIN_REG2
1667 {0x5912,0x0654},//SENSOR_GAIN_REG2
1668 {0x5912,0x0684},//SENSOR_GAIN_REG2
1669 {0x5912,0x0654},//SENSOR_GAIN_REG2
1670 {0x5912,0x0654},//SENSOR_GAIN_REG2
1671 {0x5912,0x0065},//SENSOR_GAIN_REG2
1672 {0x5912,0x0066},//SENSOR_GAIN_REG2
1673 {0x5912,0x0067},//SENSOR_GAIN_REG2
1674 {0x5912,0x59BD},//SENSOR_GAIN_REG2
1675 {0x5912,0x1000},//SENSOR_GAIN_REG2
1676 {0x5912,0x0C00},//SENSOR_GAIN_REG2
1677 {0x5912,0x0F00},//SENSOR_GAIN_REG2
1678 {0x5912,0x1000},//SENSOR_GAIN_REG2
1679 {0x5912,0x10F0},//SENSOR_GAIN_REG2
1680 {0x5912,0x0075},//SENSOR_GAIN_REG2
1681 {0x5912,0x0076},//SENSOR_GAIN_REG2
1682 {0x5912,0x0077},//SENSOR_GAIN_REG2
1683 {0x5914,0x4006},//SENSOR_GAIN_TABLE_SEL
1684 {0x5900,0x0020},//SENSOR_GAIN
1685 {0x5902,0x0000},//SENSOR_GAIN_T2
1686 {0x3110,0x0001},//HDR_CONTROL0
1687
1688 {REG_NULL, 0x00},
1689 };
1690 static const struct regval ar0822_hdr12bit_3840x2160_20fps_regs[] = {
1691 {REG_DELAY, 2000},
1692 {0x3030,0x0124},//PLL_MULTIPLIER
1693 {0x302E,0x0006},//PRE_PLL_CLK_DIV
1694 {0x302C,0x0002},//VT_SYS_CLK_DIV
1695 {0x302A,0x0004},//VT_PIX_CLK_DIV
1696 {0x3038,0x0002},//OP_SYS_CLK_DIV
1697 {0x3036,0x0006},//OP_WORD_CLK_DIV
1698 {0x31B0,0x0089},//FRAME_PREAMBLE
1699 {0x31B2,0x005C},//LINE_PREAMBLE
1700 {0x31B4,0x624A},//MIPI_TIMING_0
1701 {0x31B6,0x630B},//MIPI_TIMING_1
1702 {0x31B8,0x90CB},//MIPI_TIMING_2
1703 {0x31BA,0x038E},//MIPI_TIMING_3
1704 {0x31BC,0x508B},//MIPI_TIMING_4
1705 {0x3342,0x122C},//MIPI_F1_PDT_EDT
1706 {0x2512,0xA000},//SEQ_CTRL_PORT
1707 {0x2510,0x0720},//SEQ_DATA_PORT
1708 {0x2510,0xFFFF},//SEQ_DATA_PORT
1709 {0x2510,0xFFFF},//SEQ_DATA_PORT
1710 {0x2510,0xFFFF},//SEQ_DATA_PORT
1711 {0x2510,0xFFFF},//SEQ_DATA_PORT
1712 {0x2510,0xFFFF},//SEQ_DATA_PORT
1713 {0x2510,0xFFFF},//SEQ_DATA_PORT
1714 {0x2510,0xFFFF},//SEQ_DATA_PORT
1715 {0x2510,0x2122},//SEQ_DATA_PORT
1716 {0x2510,0xFFFF},//SEQ_DATA_PORT
1717 {0x2510,0xFFFF},//SEQ_DATA_PORT
1718 {0x2510,0xFFFF},//SEQ_DATA_PORT
1719 {0x2510,0x26FF},//SEQ_DATA_PORT
1720 {0x2510,0xFFFF},//SEQ_DATA_PORT
1721 {0x2510,0xFFFF},//SEQ_DATA_PORT
1722 {0x2510,0xFFFF},//SEQ_DATA_PORT
1723 {0x2510,0xFFFF},//SEQ_DATA_PORT
1724 {0x2510,0xFFFF},//SEQ_DATA_PORT
1725 {0x2510,0xFFFF},//SEQ_DATA_PORT
1726 {0x2510,0xFFFF},//SEQ_DATA_PORT
1727 {0x2510,0xFFFF},//SEQ_DATA_PORT
1728 {0x2510,0xFFFF},//SEQ_DATA_PORT
1729 {0x2510,0xFFFF},//SEQ_DATA_PORT
1730 {0x2510,0xFFFF},//SEQ_DATA_PORT
1731 {0x2510,0xFFFF},//SEQ_DATA_PORT
1732 {0x2510,0xFFFF},//SEQ_DATA_PORT
1733 {0x2510,0xFFFF},//SEQ_DATA_PORT
1734 {0x2510,0xFFFF},//SEQ_DATA_PORT
1735 {0x2510,0x20FF},//SEQ_DATA_PORT
1736 {0x2510,0x20FF},//SEQ_DATA_PORT
1737 {0x2510,0x20FF},//SEQ_DATA_PORT
1738 {0x2510,0x20FF},//SEQ_DATA_PORT
1739 {0x2510,0x20FF},//SEQ_DATA_PORT
1740 {0x2510,0x20FF},//SEQ_DATA_PORT
1741 {0x2510,0x20FF},//SEQ_DATA_PORT
1742 {0x2510,0x20FF},//SEQ_DATA_PORT
1743 {0x2510,0x20FF},//SEQ_DATA_PORT
1744 {0x2510,0x20FF},//SEQ_DATA_PORT
1745 {0x2510,0x20FF},//SEQ_DATA_PORT
1746 {0x2510,0x20FF},//SEQ_DATA_PORT
1747 {0x2510,0x20FF},//SEQ_DATA_PORT
1748 {0x2510,0x20FF},//SEQ_DATA_PORT
1749 {0x2510,0x20FF},//SEQ_DATA_PORT
1750 {0x2510,0x20FF},//SEQ_DATA_PORT
1751 {0x2510,0x20FF},//SEQ_DATA_PORT
1752 {0x2510,0x0F8C},//SEQ_DATA_PORT
1753 {0x2510,0x20FF},//SEQ_DATA_PORT
1754 {0x2510,0x20FF},//SEQ_DATA_PORT
1755 {0x2510,0x20FF},//SEQ_DATA_PORT
1756 {0x2510,0x20FF},//SEQ_DATA_PORT
1757 {0x2510,0x20FF},//SEQ_DATA_PORT
1758 {0x2510,0x20FF},//SEQ_DATA_PORT
1759 {0x2510,0x20FF},//SEQ_DATA_PORT
1760 {0x2510,0x20FF},//SEQ_DATA_PORT
1761 {0x2510,0x20FF},//SEQ_DATA_PORT
1762 {0x2510,0x20FF},//SEQ_DATA_PORT
1763 {0x2510,0x20FF},//SEQ_DATA_PORT
1764 {0x2510,0x20FF},//SEQ_DATA_PORT
1765 {0x2510,0x20FF},//SEQ_DATA_PORT
1766 {0x2510,0x20FF},//SEQ_DATA_PORT
1767 {0x2510,0x20FF},//SEQ_DATA_PORT
1768 {0x2510,0x20FF},//SEQ_DATA_PORT
1769 {0x2510,0x20FF},//SEQ_DATA_PORT
1770 {0x2510,0x20FF},//SEQ_DATA_PORT
1771 {0x2510,0x20FF},//SEQ_DATA_PORT
1772 {0x2510,0x20FF},//SEQ_DATA_PORT
1773 {0x2510,0x20FF},//SEQ_DATA_PORT
1774 {0x2510,0x20FF},//SEQ_DATA_PORT
1775 {0x2510,0x20FF},//SEQ_DATA_PORT
1776 {0x2510,0x20E0},//SEQ_DATA_PORT
1777 {0x2510,0x8055},//SEQ_DATA_PORT
1778 {0x2510,0xA0E1},//SEQ_DATA_PORT
1779 {0x2510,0x3041},//SEQ_DATA_PORT
1780 {0x2510,0x2000},//SEQ_DATA_PORT
1781 {0x2510,0x3088},//SEQ_DATA_PORT
1782 {0x2510,0x3282},//SEQ_DATA_PORT
1783 {0x2510,0xA681},//SEQ_DATA_PORT
1784 {0x2510,0x20FF},//SEQ_DATA_PORT
1785 {0x2510,0x20FF},//SEQ_DATA_PORT
1786 {0x2510,0x20FF},//SEQ_DATA_PORT
1787 {0x2510,0x20FF},//SEQ_DATA_PORT
1788 {0x2510,0x20FE},//SEQ_DATA_PORT
1789 {0x2510,0x9070},//SEQ_DATA_PORT
1790 {0x2510,0x891D},//SEQ_DATA_PORT
1791 {0x2510,0x867F},//SEQ_DATA_PORT
1792 {0x2510,0x20FF},//SEQ_DATA_PORT
1793 {0x2510,0x20FC},//SEQ_DATA_PORT
1794 {0x2510,0x893F},//SEQ_DATA_PORT
1795 {0x2510,0x0F92},//SEQ_DATA_PORT
1796 {0x2510,0x20E0},//SEQ_DATA_PORT
1797 {0x2510,0x0F8F},//SEQ_DATA_PORT
1798 {0x2510,0x20FF},//SEQ_DATA_PORT
1799 {0x2510,0x20FF},//SEQ_DATA_PORT
1800 {0x2510,0x20FF},//SEQ_DATA_PORT
1801 {0x2510,0x20FF},//SEQ_DATA_PORT
1802 {0x2510,0x20FF},//SEQ_DATA_PORT
1803 {0x2510,0x20E0},//SEQ_DATA_PORT
1804 {0x2510,0x9770},//SEQ_DATA_PORT
1805 {0x2510,0x20FC},//SEQ_DATA_PORT
1806 {0x2510,0x8054},//SEQ_DATA_PORT
1807 {0x2510,0x896C},//SEQ_DATA_PORT
1808 {0x2510,0x200A},//SEQ_DATA_PORT
1809 {0x2510,0x9030},//SEQ_DATA_PORT
1810 {0x2510,0x200A},//SEQ_DATA_PORT
1811 {0x2510,0x8040},//SEQ_DATA_PORT
1812 {0x2510,0x8948},//SEQ_DATA_PORT
1813 {0x2510,0x200A},//SEQ_DATA_PORT
1814 {0x2510,0x1597},//SEQ_DATA_PORT
1815 {0x2510,0x8808},//SEQ_DATA_PORT
1816 {0x2510,0x200A},//SEQ_DATA_PORT
1817 {0x2510,0x1F96},//SEQ_DATA_PORT
1818 {0x2510,0x20FF},//SEQ_DATA_PORT
1819 {0x2510,0x20E0},//SEQ_DATA_PORT
1820 {0x2510,0xA0C0},//SEQ_DATA_PORT
1821 {0x2510,0x200A},//SEQ_DATA_PORT
1822 {0x2510,0x3044},//SEQ_DATA_PORT
1823 {0x2510,0x3088},//SEQ_DATA_PORT
1824 {0x2510,0x3282},//SEQ_DATA_PORT
1825 {0x2510,0x2004},//SEQ_DATA_PORT
1826 {0x2510,0x1FAA},//SEQ_DATA_PORT
1827 {0x2510,0x20FF},//SEQ_DATA_PORT
1828 {0x2510,0x20FF},//SEQ_DATA_PORT
1829 {0x2510,0x20FF},//SEQ_DATA_PORT
1830 {0x2510,0x20FF},//SEQ_DATA_PORT
1831 {0x2510,0x20E0},//SEQ_DATA_PORT
1832 {0x2510,0x7FFF},//SEQ_DATA_PORT
1833 {0x2510,0x7FFF},//SEQ_DATA_PORT
1834 {0x2510,0x7FFF},//SEQ_DATA_PORT
1835 {0x2510,0x20FF},//SEQ_DATA_PORT
1836 {0x2510,0x7FFF},//SEQ_DATA_PORT
1837 {0x2510,0x7FFF},//SEQ_DATA_PORT
1838 {0x2510,0x7FFF},//SEQ_DATA_PORT
1839 {0x2510,0x3108},//SEQ_DATA_PORT
1840 {0x2510,0x2400},//SEQ_DATA_PORT
1841 {0x2510,0x3244},//SEQ_DATA_PORT
1842 {0x2510,0x7FFF},//SEQ_DATA_PORT
1843 {0x2510,0x3108},//SEQ_DATA_PORT
1844 {0x2510,0x2400},//SEQ_DATA_PORT
1845 {0x2510,0x2702},//SEQ_DATA_PORT
1846 {0x2510,0x3242},//SEQ_DATA_PORT
1847 {0x2510,0x3108},//SEQ_DATA_PORT
1848 {0x2510,0x2420},//SEQ_DATA_PORT
1849 {0x2510,0x2703},//SEQ_DATA_PORT
1850 {0x2510,0x3242},//SEQ_DATA_PORT
1851 {0x2510,0x3108},//SEQ_DATA_PORT
1852 {0x2510,0x2420},//SEQ_DATA_PORT
1853 {0x2510,0x2704},//SEQ_DATA_PORT
1854 {0x2510,0x3244},//SEQ_DATA_PORT
1855 {0x2510,0x7FFF},//SEQ_DATA_PORT
1856 {0x2510,0x7FFF},//SEQ_DATA_PORT
1857 {0x2510,0x7FFF},//SEQ_DATA_PORT
1858 {0x2510,0x7FFF},//SEQ_DATA_PORT
1859 {0x2510,0x8801},//SEQ_DATA_PORT
1860 {0x2510,0x000F},//SEQ_DATA_PORT
1861 {0x2510,0x109C},//SEQ_DATA_PORT
1862 {0x2510,0x8855},//SEQ_DATA_PORT
1863 {0x2510,0x3101},//SEQ_DATA_PORT
1864 {0x2510,0x3041},//SEQ_DATA_PORT
1865 {0x2510,0x2000},//SEQ_DATA_PORT
1866 {0x2510,0x3102},//SEQ_DATA_PORT
1867 {0x2510,0x3041},//SEQ_DATA_PORT
1868 {0x2510,0x2000},//SEQ_DATA_PORT
1869 {0x2510,0x3181},//SEQ_DATA_PORT
1870 {0x2510,0x3041},//SEQ_DATA_PORT
1871 {0x2510,0x2000},//SEQ_DATA_PORT
1872 {0x2510,0x3188},//SEQ_DATA_PORT
1873 {0x2510,0x3041},//SEQ_DATA_PORT
1874 {0x2510,0x2000},//SEQ_DATA_PORT
1875 {0x2510,0x3282},//SEQ_DATA_PORT
1876 {0x2510,0x3104},//SEQ_DATA_PORT
1877 {0x2510,0x2000},//SEQ_DATA_PORT
1878 {0x2510,0xB0E4},//SEQ_DATA_PORT
1879 {0x2510,0xAD92},//SEQ_DATA_PORT
1880 {0x2510,0xBC0C},//SEQ_DATA_PORT
1881 {0x2510,0x1028},//SEQ_DATA_PORT
1882 {0x2510,0x0022},//SEQ_DATA_PORT
1883 {0x2510,0xC020},//SEQ_DATA_PORT
1884 {0x2510,0x003E},//SEQ_DATA_PORT
1885 {0x2510,0x0045},//SEQ_DATA_PORT
1886 {0x2510,0x00B0},//SEQ_DATA_PORT
1887 {0x2510,0x0028},//SEQ_DATA_PORT
1888 {0x2510,0x30C1},//SEQ_DATA_PORT
1889 {0x2510,0x8015},//SEQ_DATA_PORT
1890 {0x2510,0xA038},//SEQ_DATA_PORT
1891 {0x2510,0x100F},//SEQ_DATA_PORT
1892 {0x2510,0x0507},//SEQ_DATA_PORT
1893 {0x2510,0xA220},//SEQ_DATA_PORT
1894 {0x2510,0x0010},//SEQ_DATA_PORT
1895 {0x2510,0x10C2},//SEQ_DATA_PORT
1896 {0x2510,0xB760},//SEQ_DATA_PORT
1897 {0x2510,0x0033},//SEQ_DATA_PORT
1898 {0x2510,0x1082},//SEQ_DATA_PORT
1899 {0x2510,0x100B},//SEQ_DATA_PORT
1900 {0x2510,0x1029},//SEQ_DATA_PORT
1901 {0x2510,0xA85A},//SEQ_DATA_PORT
1902 {0x2510,0x998D},//SEQ_DATA_PORT
1903 {0x2510,0xC810},//SEQ_DATA_PORT
1904 {0x2510,0x2004},//SEQ_DATA_PORT
1905 {0x2510,0x0ECE},//SEQ_DATA_PORT
1906 {0x2510,0x123B},//SEQ_DATA_PORT
1907 {0x2510,0xC000},//SEQ_DATA_PORT
1908 {0x2510,0x032F},//SEQ_DATA_PORT
1909 {0x2510,0x11D5},//SEQ_DATA_PORT
1910 {0x2510,0x162F},//SEQ_DATA_PORT
1911 {0x2510,0x9000},//SEQ_DATA_PORT
1912 {0x2510,0x2034},//SEQ_DATA_PORT
1913 {0x2510,0x0015},//SEQ_DATA_PORT
1914 {0x2510,0x04CB},//SEQ_DATA_PORT
1915 {0x2510,0x1022},//SEQ_DATA_PORT
1916 {0x2510,0x1031},//SEQ_DATA_PORT
1917 {0x2510,0x002D},//SEQ_DATA_PORT
1918 {0x2510,0x1015},//SEQ_DATA_PORT
1919 {0x2510,0x80B9},//SEQ_DATA_PORT
1920 {0x2510,0xA101},//SEQ_DATA_PORT
1921 {0x2510,0x001C},//SEQ_DATA_PORT
1922 {0x2510,0x008E},//SEQ_DATA_PORT
1923 {0x2510,0x124B},//SEQ_DATA_PORT
1924 {0x2510,0x01B5},//SEQ_DATA_PORT
1925 {0x2510,0x0B92},//SEQ_DATA_PORT
1926 {0x2510,0xA400},//SEQ_DATA_PORT
1927 {0x2510,0x8091},//SEQ_DATA_PORT
1928 {0x2510,0x0028},//SEQ_DATA_PORT
1929 {0x2510,0x3002},//SEQ_DATA_PORT
1930 {0x2510,0x2004},//SEQ_DATA_PORT
1931 {0x2510,0x1012},//SEQ_DATA_PORT
1932 {0x2510,0x100E},//SEQ_DATA_PORT
1933 {0x2510,0x10A8},//SEQ_DATA_PORT
1934 {0x2510,0x00A1},//SEQ_DATA_PORT
1935 {0x2510,0x132D},//SEQ_DATA_PORT
1936 {0x2510,0x09AF},//SEQ_DATA_PORT
1937 {0x2510,0x0159},//SEQ_DATA_PORT
1938 {0x2510,0x121D},//SEQ_DATA_PORT
1939 {0x2510,0x1259},//SEQ_DATA_PORT
1940 {0x2510,0x11AF},//SEQ_DATA_PORT
1941 {0x2510,0x18B5},//SEQ_DATA_PORT
1942 {0x2510,0x0395},//SEQ_DATA_PORT
1943 {0x2510,0x054B},//SEQ_DATA_PORT
1944 {0x2510,0x1021},//SEQ_DATA_PORT
1945 {0x2510,0x0020},//SEQ_DATA_PORT
1946 {0x2510,0x1015},//SEQ_DATA_PORT
1947 {0x2510,0x1030},//SEQ_DATA_PORT
1948 {0x2510,0x00CF},//SEQ_DATA_PORT
1949 {0x2510,0xB146},//SEQ_DATA_PORT
1950 {0x2510,0xC290},//SEQ_DATA_PORT
1951 {0x2510,0x103C},//SEQ_DATA_PORT
1952 {0x2510,0xA882},//SEQ_DATA_PORT
1953 {0x2510,0x8055},//SEQ_DATA_PORT
1954 {0x2510,0x00A9},//SEQ_DATA_PORT
1955 {0x2510,0x8801},//SEQ_DATA_PORT
1956 {0x2510,0xB700},//SEQ_DATA_PORT
1957 {0x2510,0x0001},//SEQ_DATA_PORT
1958 {0x2510,0x02A2},//SEQ_DATA_PORT
1959 {0x2510,0x000A},//SEQ_DATA_PORT
1960 {0x2510,0x98BB},//SEQ_DATA_PORT
1961 {0x2510,0x203F},//SEQ_DATA_PORT
1962 {0x2510,0x0036},//SEQ_DATA_PORT
1963 {0x2510,0x1001},//SEQ_DATA_PORT
1964 {0x2510,0x99BE},//SEQ_DATA_PORT
1965 {0x2510,0x0139},//SEQ_DATA_PORT
1966 {0x2510,0x100A},//SEQ_DATA_PORT
1967 {0x2510,0x0040},//SEQ_DATA_PORT
1968 {0x2510,0x1022},//SEQ_DATA_PORT
1969 {0x2510,0x124C},//SEQ_DATA_PORT
1970 {0x2510,0x109F},//SEQ_DATA_PORT
1971 {0x2510,0x15A3},//SEQ_DATA_PORT
1972 {0x2510,0x002A},//SEQ_DATA_PORT
1973 {0x2510,0x3081},//SEQ_DATA_PORT
1974 {0x2510,0x2001},//SEQ_DATA_PORT
1975 {0x2510,0x3044},//SEQ_DATA_PORT
1976 {0x2510,0x2000},//SEQ_DATA_PORT
1977 {0x2510,0x112A},//SEQ_DATA_PORT
1978 {0x2510,0x101D},//SEQ_DATA_PORT
1979 {0x2510,0x202B},//SEQ_DATA_PORT
1980 {0x2510,0x02B8},//SEQ_DATA_PORT
1981 {0x2510,0x10B8},//SEQ_DATA_PORT
1982 {0x2510,0x1136},//SEQ_DATA_PORT
1983 {0x2510,0x996B},//SEQ_DATA_PORT
1984 {0x2510,0x004C},//SEQ_DATA_PORT
1985 {0x2510,0x1039},//SEQ_DATA_PORT
1986 {0x2510,0x1040},//SEQ_DATA_PORT
1987 {0x2510,0x00B5},//SEQ_DATA_PORT
1988 {0x2510,0x03C4},//SEQ_DATA_PORT
1989 {0x2510,0x1144},//SEQ_DATA_PORT
1990 {0x2510,0x1245},//SEQ_DATA_PORT
1991 {0x2510,0x9A7B},//SEQ_DATA_PORT
1992 {0x2510,0x002B},//SEQ_DATA_PORT
1993 {0x2510,0x30D0},//SEQ_DATA_PORT
1994 {0x2510,0x3141},//SEQ_DATA_PORT
1995 {0x2510,0x3041},//SEQ_DATA_PORT
1996 {0x2510,0x2000},//SEQ_DATA_PORT
1997 {0x2510,0x3142},//SEQ_DATA_PORT
1998 {0x2510,0x3041},//SEQ_DATA_PORT
1999 {0x2510,0x2000},//SEQ_DATA_PORT
2000 {0x2510,0x3110},//SEQ_DATA_PORT
2001 {0x2510,0x3041},//SEQ_DATA_PORT
2002 {0x2510,0x2000},//SEQ_DATA_PORT
2003 {0x2510,0x3120},//SEQ_DATA_PORT
2004 {0x2510,0x3041},//SEQ_DATA_PORT
2005 {0x2510,0x2000},//SEQ_DATA_PORT
2006 {0x2510,0x3144},//SEQ_DATA_PORT
2007 {0x2510,0x3041},//SEQ_DATA_PORT
2008 {0x2510,0x2000},//SEQ_DATA_PORT
2009 {0x2510,0x3148},//SEQ_DATA_PORT
2010 {0x2510,0x3041},//SEQ_DATA_PORT
2011 {0x2510,0x2000},//SEQ_DATA_PORT
2012 {0x2510,0x3182},//SEQ_DATA_PORT
2013 {0x2510,0x3041},//SEQ_DATA_PORT
2014 {0x2510,0x2000},//SEQ_DATA_PORT
2015 {0x2510,0x3184},//SEQ_DATA_PORT
2016 {0x2510,0x2000},//SEQ_DATA_PORT
2017 {0x2510,0x3190},//SEQ_DATA_PORT
2018 {0x2510,0x3041},//SEQ_DATA_PORT
2019 {0x2510,0x2000},//SEQ_DATA_PORT
2020 {0x2510,0x31A0},//SEQ_DATA_PORT
2021 {0x2510,0x3088},//SEQ_DATA_PORT
2022 {0x2510,0x2201},//SEQ_DATA_PORT
2023 {0x2510,0x807D},//SEQ_DATA_PORT
2024 {0x2510,0x2206},//SEQ_DATA_PORT
2025 {0x2510,0x8815},//SEQ_DATA_PORT
2026 {0x2510,0x8877},//SEQ_DATA_PORT
2027 {0x2510,0x0092},//SEQ_DATA_PORT
2028 {0x2510,0x220E},//SEQ_DATA_PORT
2029 {0x2510,0x2211},//SEQ_DATA_PORT
2030 {0x2510,0x8055},//SEQ_DATA_PORT
2031 {0x2510,0x3001},//SEQ_DATA_PORT
2032 {0x2510,0x2000},//SEQ_DATA_PORT
2033 {0x2510,0x8A61},//SEQ_DATA_PORT
2034 {0x2510,0x8801},//SEQ_DATA_PORT
2035 {0x2510,0x1092},//SEQ_DATA_PORT
2036 {0x2510,0x181F},//SEQ_DATA_PORT
2037 {0x2510,0x0B1F},//SEQ_DATA_PORT
2038 {0x2510,0x101F},//SEQ_DATA_PORT
2039 {0x2510,0x00B6},//SEQ_DATA_PORT
2040 {0x2510,0x0023},//SEQ_DATA_PORT
2041 {0x2510,0x00B9},//SEQ_DATA_PORT
2042 {0x2510,0x104C},//SEQ_DATA_PORT
2043 {0x2510,0x996E},//SEQ_DATA_PORT
2044 {0x2510,0x0140},//SEQ_DATA_PORT
2045 {0x2510,0x0257},//SEQ_DATA_PORT
2046 {0x2510,0x1035},//SEQ_DATA_PORT
2047 {0x2510,0x9F26},//SEQ_DATA_PORT
2048 {0x2510,0x1423},//SEQ_DATA_PORT
2049 {0x2510,0x0048},//SEQ_DATA_PORT
2050 {0x2510,0xC878},//SEQ_DATA_PORT
2051 {0x2510,0x200A},//SEQ_DATA_PORT
2052 {0x2510,0x1548},//SEQ_DATA_PORT
2053 {0x2510,0x0C49},//SEQ_DATA_PORT
2054 {0x2510,0x1149},//SEQ_DATA_PORT
2055 {0x2510,0x002A},//SEQ_DATA_PORT
2056 {0x2510,0x1057},//SEQ_DATA_PORT
2057 {0x2510,0x3281},//SEQ_DATA_PORT
2058 {0x2510,0x2000},//SEQ_DATA_PORT
2059 {0x2510,0x3044},//SEQ_DATA_PORT
2060 {0x2510,0x2001},//SEQ_DATA_PORT
2061 {0x2510,0xA020},//SEQ_DATA_PORT
2062 {0x2510,0x000C},//SEQ_DATA_PORT
2063 {0x2510,0x9825},//SEQ_DATA_PORT
2064 {0x2510,0x1040},//SEQ_DATA_PORT
2065 {0x2510,0x1054},//SEQ_DATA_PORT
2066 {0x2510,0xB06D},//SEQ_DATA_PORT
2067 {0x2510,0x0035},//SEQ_DATA_PORT
2068 {0x2510,0x004D},//SEQ_DATA_PORT
2069 {0x2510,0x9905},//SEQ_DATA_PORT
2070 {0x2510,0xB064},//SEQ_DATA_PORT
2071 {0x2510,0x99C5},//SEQ_DATA_PORT
2072 {0x2510,0x0047},//SEQ_DATA_PORT
2073 {0x2510,0xB920},//SEQ_DATA_PORT
2074 {0x2510,0x1447},//SEQ_DATA_PORT
2075 {0x2510,0x7FFF},//SEQ_DATA_PORT
2076 {0x2510,0x7FFF},//SEQ_DATA_PORT
2077 {0x2510,0x7FFF},//SEQ_DATA_PORT
2078 {0x2510,0x7FFF},//SEQ_DATA_PORT
2079 {0x2510,0x7FFF},//SEQ_DATA_PORT
2080 {0x2510,0x7FFF},//SEQ_DATA_PORT
2081 {0x2510,0x7FFF},//SEQ_DATA_PORT
2082 {0x2510,0x7FFF},//SEQ_DATA_PORT
2083 {0x2510,0x7FFF},//SEQ_DATA_PORT
2084 {0x31F8,0x0008},//MIPI_CONFIG_2
2085 {0x3C70,0x6828},//CALIB_ROWS
2086 {0x3092,0x0826},//ROW_NOISE_CONTROL
2087 {0x3428,0x0209},//SEQUENCER_CONTROL
2088 {0x3516,0xFF04},//DAC_LD_22_23
2089 {0x3526,0x6480},//DAC_LD_38_39
2090 {0x3504,0x8AAA},//DAC_LD_4_5
2091 {0x353C,0x220C},//DAC_LD_60_61
2092 {0x3536,0x4C6E},//DAC_LD_54_55
2093 {0x3D2A,0x0FFF},//T1_END_DEC_TH
2094 {0x3364,0x00EC},//DCG_TRIM
2095 {0x3512,0x8888},//DAC_LD_18_19
2096 {0x3514,0x888F},//DAC_LD_20_21
2097 {0x3520,0xFBF0},//DAC_LD_32_33
2098 {0x3524,0xB2A1},//DAC_LD_36_37
2099 {0x3528,0xCC84},//DAC_LD_40_41
2100 {0x3532,0x4C8E},//DAC_LD_50_51
2101 {0x3534,0x4E64},//DAC_LD_52_53
2102 {0x351E,0x5856},//DAC_LD_30_31
2103 {0x353E,0x98F2},//DAC_LD_62_63
2104 {0x352E,0x6A8A},//DAC_LD_46_47
2105 {0x3370,0x0211},//DBLC_CONTROL
2106 {0x3372,0x700F},//DBLC_FS0_CONTROL
2107 {0x3540,0x3597},//DAC_LD_64_65
2108 {0x58E2,0x0BE3},//COL_COUNT_VALUES1
2109 {0x58E4,0x18B4},//COL_COUNT_VALUES2
2110 {0x3522,0x7C97},//DAC_LD_34_35
2111 {0x30BA,0x0024},//DIGITAL_CTRL
2112 {0x31D4,0x0042},//CLK_MEM_GATING_CTRL
2113 {0x352A,0x6F8F},//DAC_LD_42_43
2114 {0x3530,0x4A08},//DAC_LD_48_49
2115 {0x351A,0x5FFF},//DAC_LD_26_27
2116 {0x350E,0x39D9},//DAC_LD_14_15
2117 {0x3510,0x9988},//DAC_LD_16_17
2118 {0x3380,0x1FFF},//DBLC_OFFSET1
2119 {0x337A,0x1000},//DBLC_SCALE1
2120 {0x3092,0x0800},//ROW_NOISE_CONTROL
2121 {0x350A,0x0654},//DAC_LD_10_11
2122 {0x3364,0x00E0},//DCG_TRIM
2123 {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA
2124 {0x591E,0x722C},//ANALOG_GAIN_WR_DATA
2125 {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA
2126 {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA
2127 {0x591E,0xA447},//ANALOG_GAIN_WR_DATA
2128 {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA
2129 {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA
2130 {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA
2131 {0x3532,0x4C8A},//DAC_LD_50_51
2132 {0x3534,0x4E60},//DAC_LD_52_53
2133 {0x353E,0x90F2},//DAC_LD_62_63
2134 {0x351A,0x4FFF},//DAC_LD_26_27
2135 {0x591C,0x00D7},//DGR_AMP_GAIN
2136 {0x3522,0x6097},//DAC_LD_34_35
2137 {0x5002,0x37C3},//T1_PIX_DEF_ID2
2138 {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0
2139 {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1
2140 {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2
2141 {0x51D0,0x0001},//T1_NOISE_FLOOR0
2142 {0x51D2,0x0002},//T1_NOISE_FLOOR1
2143 {0x51D4,0x0003},//T1_NOISE_FLOOR2
2144 {0x51D6,0x0004},//T1_NOISE_FLOOR3
2145 {0x5202,0x37C3},//T2_PIX_DEF_ID2
2146 {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0
2147 {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1
2148 {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2
2149 {0x51EE,0x0001},//T2_NOISE_FLOOR0
2150 {0x51F0,0x0002},//T2_NOISE_FLOOR1
2151 {0x51F2,0x0003},//T2_NOISE_FLOOR2
2152 {0x51F4,0x0004},//T2_NOISE_FLOOR3
2153 {0x5402,0x37C3},//T4_PIX_DEF_ID2
2154 {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0
2155 {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1
2156 {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2
2157 {0x5564,0x0001},//T4_NOISE_FLOOR0
2158 {0x5566,0x0002},//T4_NOISE_FLOOR1
2159 {0x5568,0x0003},//T4_NOISE_FLOOR2
2160 {0x556A,0x0004},//T4_NOISE_FLOOR3
2161 {0x31E0,0x0001},//PIX_DEF_ID
2162 {0x5000,0x0080},//T1_PIX_DEF_ID
2163 {0x5000,0x0180},//T1_PIX_DEF_ID
2164 {0x5000,0x0180},//T1_PIX_DEF_ID
2165 {0x5200,0x0080},//T2_PIX_DEF_ID
2166 {0x5200,0x0180},//T2_PIX_DEF_ID
2167 {0x5200,0x0180},//T2_PIX_DEF_ID
2168 {0x5400,0x0080},//T4_PIX_DEF_ID
2169 {0x5400,0x0180},//T4_PIX_DEF_ID
2170 {0x5400,0x0180},//T4_PIX_DEF_ID
2171 {0x5000,0x0180},//T1_PIX_DEF_ID
2172 {0x5200,0x0180},//T2_PIX_DEF_ID
2173 {0x5400,0x0180},//T4_PIX_DEF_ID
2174 {0x50A2,0x3F2A},//BMT0
2175 {0x50A4,0x875A},//BMT1
2176 {0x50A6,0x030F},//SINGLEK_FACTOR0
2177 {0x50A6,0x0F0F},//SINGLEK_FACTOR0
2178 {0x50A8,0x030F},//SINGLEK_FACTOR1
2179 {0x50A8,0x0F0F},//SINGLEK_FACTOR1
2180 {0x50AA,0x030F},//SINGLEK_FACTOR2
2181 {0x50AA,0x050F},//SINGLEK_FACTOR2
2182 {0x50AC,0x0301},//CROSS_FACTOR0
2183 {0x50AC,0x0101},//CROSS_FACTOR0
2184 {0x50AE,0x0301},//CROSS_FACTOR1
2185 {0x50AE,0x0101},//CROSS_FACTOR1
2186 {0x50B0,0x0301},//CROSS_FACTOR2
2187 {0x50B0,0x0101},//CROSS_FACTOR2
2188 {0x50B2,0x03FF},//SINGLE_MAX_FACTOR
2189 {0x50B4,0x030F},//COUPLE_FACTOR0
2190 {0x50B4,0x0F0F},//COUPLE_FACTOR0
2191 {0x50B6,0x030F},//COUPLE_FACTOR1
2192 {0x50B6,0x0F0F},//COUPLE_FACTOR1
2193 {0x50B8,0x030F},//COUPLE_FACTOR2
2194 {0x50B8,0x050F},//COUPLE_FACTOR2
2195 {0x3D2A,0x0FFF},//T1_END_DEC_TH
2196 {0x3D34,0x9C40},//T2_STR_DEC_TH
2197 {0x3D36,0xFFFF},//T2_END_DEC_TH
2198 {0x3D02,0x5033},//MEC_CTRL2
2199 {0x3086,0x1A28},//PARK_ROW_ADDR
2200 {0x33E4,0x0040},//VERT_SHADING_CONTROL
2201 {0x3C70,0x6222},//CALIB_ROWS
2202 {0x3110,0x0011},//HDR_CONTROL0
2203 {0x30B0,0x0820},//DIGITAL_TEST
2204 {0x3280,0x0ED8},//T1_BARRIER_C0
2205 {0x3282,0x0ED8},//T1_BARRIER_C1
2206 {0x3284,0x0ED8},//T1_BARRIER_C2
2207 {0x3286,0x0ED8},//T1_BARRIER_C3
2208 {0x3288,0x0ED8},//T2_BARRIER_C0
2209 {0x328A,0x0ED8},//T2_BARRIER_C1
2210 {0x328C,0x0ED8},//T2_BARRIER_C2
2211 {0x328E,0x0ED8},//T2_BARRIER_C3
2212 {0x3290,0x0ED8},//T3_BARRIER_C0
2213 {0x3292,0x0ED8},//T3_BARRIER_C1
2214 {0x3294,0x0ED8},//T3_BARRIER_C2
2215 {0x3296,0x0ED8},//T3_BARRIER_C3
2216 {0x3100,0xC001},//DLO_CONTROL0
2217 {0x3102,0xBED8},//DLO_CONTROL1
2218 {0x3104,0xBED8},//DLO_CONTROL2
2219 {0x3106,0xBED8},//DLO_CONTROL3
2220 {0x3108,0x07D0},//DLO_CONTROL4
2221 {0x3116,0x2001},//HDR_CONTROL3
2222 {0x3124,0x006D},//HDR_MD_CONTROL0
2223 {0x3126,0x003C},//HDR_MD_CONTROL1
2224 {0x31AE,0x0204},//SERIAL_FORMAT
2225 {0x31AC,0x0C0C},//DATA_FORMAT_BITS
2226 {0x3082,0x0014},//OPERATION_MODE_CTRL
2227 {0x30BA,0x0135},//DIGITAL_CTRL
2228 {0x3238,0x0044},//EXPOSURE_RATIO
2229 {0x3012,0x0900},//COARSE_INTEGRATION_TIME_
2230 {0x3212,0x0090},//COARSE_INTEGRATION_TIME2
2231 {0x300C,0x0CE2},//LINE_LENGTH_PCK_
2232 {0x300A,0x09B8},//FRAME_LENGTH_LINES_
2233 {0x5914,0x4012},//SENSOR_GAIN_TABLE_SEL
2234 {REG_DELAY,100},
2235 {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL
2236 {0x5910,0x608A},//SENSOR_GAIN_REG1
2237 {0x5910,0x7091},//SENSOR_GAIN_REG1
2238 {0x5910,0x689C},//SENSOR_GAIN_REG1
2239 {0x5910,0x8885},//SENSOR_GAIN_REG1
2240 {0x5910,0x98AD},//SENSOR_GAIN_REG1
2241 {0x5910,0xA8A9},//SENSOR_GAIN_REG1
2242 {0x5910,0xC894},//SENSOR_GAIN_REG1
2243 {0x5910,0xC8D1},//SENSOR_GAIN_REG1
2244 {0x5910,0xD88A},//SENSOR_GAIN_REG1
2245 {0x5910,0xD8C3},//SENSOR_GAIN_REG1
2246 {0x5910,0xD915},//SENSOR_GAIN_REG1
2247 {0x5910,0xD988},//SENSOR_GAIN_REG1
2248 {0x5910,0xDA2A},//SENSOR_GAIN_REG1
2249 {0x5910,0xDB0E},//SENSOR_GAIN_REG1
2250 {0x5910,0xDC53},//SENSOR_GAIN_REG1
2251 {0x5910,0x608A},//SENSOR_GAIN_REG1
2252 {0x5910,0xC919},//SENSOR_GAIN_REG1
2253 {0x5910,0xCA00},//SENSOR_GAIN_REG1
2254 {0x5910,0x0000},//SENSOR_GAIN_REG1
2255 {0x5910,0x0000},//SENSOR_GAIN_REG1
2256 {0x5910,0x0000},//SENSOR_GAIN_REG1
2257 {0x5910,0x0001},//SENSOR_GAIN_REG1
2258 {0x5910,0x0001},//SENSOR_GAIN_REG1
2259 {0x5910,0x0003},//SENSOR_GAIN_REG1
2260 {0x5910,0x0003},//SENSOR_GAIN_REG1
2261 {0x5910,0x0003},//SENSOR_GAIN_REG1
2262 {0x5910,0x0004},//SENSOR_GAIN_REG1
2263 {0x5910,0x0004},//SENSOR_GAIN_REG1
2264 {0x5910,0x0004},//SENSOR_GAIN_REG1
2265 {0x5910,0x0004},//SENSOR_GAIN_REG1
2266 {0x5910,0x0004},//SENSOR_GAIN_REG1
2267 {0x5910,0x0004},//SENSOR_GAIN_REG1
2268 {0x5910,0x0004},//SENSOR_GAIN_REG1
2269 {0x5910,0x0002},//SENSOR_GAIN_REG1
2270 {0x5910,0x0003},//SENSOR_GAIN_REG1
2271 {0x5910,0x0003},//SENSOR_GAIN_REG1
2272 {0x5910,0x5A8B},//SENSOR_GAIN_REG1
2273 {0x5910,0xFF04},//SENSOR_GAIN_REG1
2274 {0x5910,0xF704},//SENSOR_GAIN_REG1
2275 {0x5910,0xFF04},//SENSOR_GAIN_REG1
2276 {0x5910,0xF704},//SENSOR_GAIN_REG1
2277 {0x5910,0xF704},//SENSOR_GAIN_REG1
2278 {0x5910,0x0005},//SENSOR_GAIN_REG1
2279 {0x5910,0x0006},//SENSOR_GAIN_REG1
2280 {0x5910,0x0007},//SENSOR_GAIN_REG1
2281 {0x5910,0x9A8B},//SENSOR_GAIN_REG1
2282 {0x5910,0xFF04},//SENSOR_GAIN_REG1
2283 {0x5910,0xF704},//SENSOR_GAIN_REG1
2284 {0x5910,0xF704},//SENSOR_GAIN_REG1
2285 {0x5910,0xF704},//SENSOR_GAIN_REG1
2286 {0x5910,0xF704},//SENSOR_GAIN_REG1
2287 {0x5910,0x0015},//SENSOR_GAIN_REG1
2288 {0x5910,0x0016},//SENSOR_GAIN_REG1
2289 {0x5910,0x0017},//SENSOR_GAIN_REG1
2290 {0x5910,0xDA8B},//SENSOR_GAIN_REG1
2291 {0x5910,0xFF04},//SENSOR_GAIN_REG1
2292 {0x5910,0xF704},//SENSOR_GAIN_REG1
2293 {0x5910,0xF704},//SENSOR_GAIN_REG1
2294 {0x5910,0xF704},//SENSOR_GAIN_REG1
2295 {0x5910,0xF704},//SENSOR_GAIN_REG1
2296 {0x5910,0x0025},//SENSOR_GAIN_REG1
2297 {0x5910,0x0026},//SENSOR_GAIN_REG1
2298 {0x5910,0x0027},//SENSOR_GAIN_REG1
2299 {0x5910,0x59B9},//SENSOR_GAIN_REG1
2300 {0x5910,0x700F},//SENSOR_GAIN_REG1
2301 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2302 {0x5910,0x700F},//SENSOR_GAIN_REG1
2303 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2304 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2305 {0x5910,0x0035},//SENSOR_GAIN_REG1
2306 {0x5910,0x0036},//SENSOR_GAIN_REG1
2307 {0x5910,0x0037},//SENSOR_GAIN_REG1
2308 {0x5910,0x99B9},//SENSOR_GAIN_REG1
2309 {0x5910,0x700F},//SENSOR_GAIN_REG1
2310 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2311 {0x5910,0x700F},//SENSOR_GAIN_REG1
2312 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2313 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2314 {0x5910,0x0045},//SENSOR_GAIN_REG1
2315 {0x5910,0x0046},//SENSOR_GAIN_REG1
2316 {0x5910,0x0047},//SENSOR_GAIN_REG1
2317 {0x5910,0xD9B9},//SENSOR_GAIN_REG1
2318 {0x5910,0x700F},//SENSOR_GAIN_REG1
2319 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2320 {0x5910,0x700F},//SENSOR_GAIN_REG1
2321 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2322 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
2323 {0x5910,0x0055},//SENSOR_GAIN_REG1
2324 {0x5910,0x0056},//SENSOR_GAIN_REG1
2325 {0x5910,0x0057},//SENSOR_GAIN_REG1
2326 {0x5910,0x9A85},//SENSOR_GAIN_REG1
2327 {0x5910,0x0654},//SENSOR_GAIN_REG1
2328 {0x5910,0x0654},//SENSOR_GAIN_REG1
2329 {0x5910,0x0684},//SENSOR_GAIN_REG1
2330 {0x5910,0x0654},//SENSOR_GAIN_REG1
2331 {0x5910,0x0654},//SENSOR_GAIN_REG1
2332 {0x5910,0x0065},//SENSOR_GAIN_REG1
2333 {0x5910,0x0066},//SENSOR_GAIN_REG1
2334 {0x5910,0x0067},//SENSOR_GAIN_REG1
2335 {0x5910,0x59BD},//SENSOR_GAIN_REG1
2336 {0x5910,0x1000},//SENSOR_GAIN_REG1
2337 {0x5910,0x0C00},//SENSOR_GAIN_REG1
2338 {0x5910,0x0F00},//SENSOR_GAIN_REG1
2339 {0x5910,0x1000},//SENSOR_GAIN_REG1
2340 {0x5910,0x10F0},//SENSOR_GAIN_REG1
2341 {0x5910,0x0075},//SENSOR_GAIN_REG1
2342 {0x5910,0x0076},//SENSOR_GAIN_REG1
2343 {0x5910,0x0077},//SENSOR_GAIN_REG1
2344 {0x5912,0x608A},//SENSOR_GAIN_REG2
2345 {0x5912,0x7091},//SENSOR_GAIN_REG2
2346 {0x5912,0x689C},//SENSOR_GAIN_REG2
2347 {0x5912,0x8885},//SENSOR_GAIN_REG2
2348 {0x5912,0x98AD},//SENSOR_GAIN_REG2
2349 {0x5912,0xA8A9},//SENSOR_GAIN_REG2
2350 {0x5912,0xC894},//SENSOR_GAIN_REG2
2351 {0x5912,0xC8D1},//SENSOR_GAIN_REG2
2352 {0x5912,0xC927},//SENSOR_GAIN_REG2
2353 {0x5912,0xC9A0},//SENSOR_GAIN_REG2
2354 {0x5912,0xCA4C},//SENSOR_GAIN_REG2
2355 {0x5912,0xCB3F},//SENSOR_GAIN_REG2
2356 {0x5912,0xCC97},//SENSOR_GAIN_REG2
2357 {0x5912,0xCE7C},//SENSOR_GAIN_REG2
2358 {0x5912,0xCFFF},//SENSOR_GAIN_REG2
2359 {0x5912,0x608A},//SENSOR_GAIN_REG2
2360 {0x5912,0xC8F0},//SENSOR_GAIN_REG2
2361 {0x5912,0xCA00},//SENSOR_GAIN_REG2
2362 {0x5912,0x0000},//SENSOR_GAIN_REG2
2363 {0x5912,0x0000},//SENSOR_GAIN_REG2
2364 {0x5912,0x0000},//SENSOR_GAIN_REG2
2365 {0x5912,0x0001},//SENSOR_GAIN_REG2
2366 {0x5912,0x0001},//SENSOR_GAIN_REG2
2367 {0x5912,0x0003},//SENSOR_GAIN_REG2
2368 {0x5912,0x0003},//SENSOR_GAIN_REG2
2369 {0x5912,0x0003},//SENSOR_GAIN_REG2
2370 {0x5912,0x0004},//SENSOR_GAIN_REG2
2371 {0x5912,0x0004},//SENSOR_GAIN_REG2
2372 {0x5912,0x0004},//SENSOR_GAIN_REG2
2373 {0x5912,0x0004},//SENSOR_GAIN_REG2
2374 {0x5912,0x0004},//SENSOR_GAIN_REG2
2375 {0x5912,0x0004},//SENSOR_GAIN_REG2
2376 {0x5912,0x0004},//SENSOR_GAIN_REG2
2377 {0x5912,0x0002},//SENSOR_GAIN_REG2
2378 {0x5912,0x0003},//SENSOR_GAIN_REG2
2379 {0x5912,0x0003},//SENSOR_GAIN_REG2
2380 {0x5912,0x5A8B},//SENSOR_GAIN_REG2
2381 {0x5912,0xFF04},//SENSOR_GAIN_REG2
2382 {0x5912,0xF704},//SENSOR_GAIN_REG2
2383 {0x5912,0xFF04},//SENSOR_GAIN_REG2
2384 {0x5912,0xF704},//SENSOR_GAIN_REG2
2385 {0x5912,0xF704},//SENSOR_GAIN_REG2
2386 {0x5912,0x0005},//SENSOR_GAIN_REG2
2387 {0x5912,0x0006},//SENSOR_GAIN_REG2
2388 {0x5912,0x0007},//SENSOR_GAIN_REG2
2389 {0x5912,0x9A8B},//SENSOR_GAIN_REG2
2390 {0x5912,0xFF04},//SENSOR_GAIN_REG2
2391 {0x5912,0xF704},//SENSOR_GAIN_REG2
2392 {0x5912,0xF704},//SENSOR_GAIN_REG2
2393 {0x5912,0xF704},//SENSOR_GAIN_REG2
2394 {0x5912,0xF704},//SENSOR_GAIN_REG2
2395 {0x5912,0x0015},//SENSOR_GAIN_REG2
2396 {0x5912,0x0016},//SENSOR_GAIN_REG2
2397 {0x5912,0x0017},//SENSOR_GAIN_REG2
2398 {0x5912,0xDA8B},//SENSOR_GAIN_REG2
2399 {0x5912,0xFF04},//SENSOR_GAIN_REG2
2400 {0x5912,0xF704},//SENSOR_GAIN_REG2
2401 {0x5912,0xF704},//SENSOR_GAIN_REG2
2402 {0x5912,0xF704},//SENSOR_GAIN_REG2
2403 {0x5912,0xF704},//SENSOR_GAIN_REG2
2404 {0x5912,0x0025},//SENSOR_GAIN_REG2
2405 {0x5912,0x0026},//SENSOR_GAIN_REG2
2406 {0x5912,0x0027},//SENSOR_GAIN_REG2
2407 {0x5912,0x59B9},//SENSOR_GAIN_REG2
2408 {0x5912,0x700F},//SENSOR_GAIN_REG2
2409 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2410 {0x5912,0x700F},//SENSOR_GAIN_REG2
2411 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2412 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2413 {0x5912,0x0035},//SENSOR_GAIN_REG2
2414 {0x5912,0x0036},//SENSOR_GAIN_REG2
2415 {0x5912,0x0037},//SENSOR_GAIN_REG2
2416 {0x5912,0x99B9},//SENSOR_GAIN_REG2
2417 {0x5912,0x700F},//SENSOR_GAIN_REG2
2418 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2419 {0x5912,0x700F},//SENSOR_GAIN_REG2
2420 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2421 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2422 {0x5912,0x0045},//SENSOR_GAIN_REG2
2423 {0x5912,0x0046},//SENSOR_GAIN_REG2
2424 {0x5912,0x0047},//SENSOR_GAIN_REG2
2425 {0x5912,0xD9B9},//SENSOR_GAIN_REG2
2426 {0x5912,0x700F},//SENSOR_GAIN_REG2
2427 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2428 {0x5912,0x700F},//SENSOR_GAIN_REG2
2429 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2430 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
2431 {0x5912,0x0055},//SENSOR_GAIN_REG2
2432 {0x5912,0x0056},//SENSOR_GAIN_REG2
2433 {0x5912,0x0057},//SENSOR_GAIN_REG2
2434 {0x5912,0x9A85},//SENSOR_GAIN_REG2
2435 {0x5912,0x0654},//SENSOR_GAIN_REG2
2436 {0x5912,0x0654},//SENSOR_GAIN_REG2
2437 {0x5912,0x0684},//SENSOR_GAIN_REG2
2438 {0x5912,0x0654},//SENSOR_GAIN_REG2
2439 {0x5912,0x0654},//SENSOR_GAIN_REG2
2440 {0x5912,0x0065},//SENSOR_GAIN_REG2
2441 {0x5912,0x0066},//SENSOR_GAIN_REG2
2442 {0x5912,0x0067},//SENSOR_GAIN_REG2
2443 {0x5912,0x59BD},//SENSOR_GAIN_REG2
2444 {0x5912,0x1000},//SENSOR_GAIN_REG2
2445 {0x5912,0x0C00},//SENSOR_GAIN_REG2
2446 {0x5912,0x0F00},//SENSOR_GAIN_REG2
2447 {0x5912,0x1000},//SENSOR_GAIN_REG2
2448 {0x5912,0x10F0},//SENSOR_GAIN_REG2
2449 {0x5912,0x0075},//SENSOR_GAIN_REG2
2450 {0x5912,0x0076},//SENSOR_GAIN_REG2
2451 {0x5912,0x0077},//SENSOR_GAIN_REG2
2452 {0x5914,0x4006},//SENSOR_GAIN_TABLE_SEL
2453 {0x5900,0x0020},//SENSOR_GAIN
2454 {0x5902,0x0000},//SENSOR_GAIN_T2
2455 {0x3110,0x0001},//HDR_CONTROL0
2456
2457 {REG_NULL, 0x00},
2458 };
2459 static const struct regval ar0822_hdr12bit_3840x2160_30fps_regs[] = {
2460 {REG_DELAY, 2000},
2461 {0x3030,0x0092},//PLL_MULTIPLIER
2462 {0x302E,0x0002},//PRE_PLL_CLK_DIV
2463 {0x302C,0x0002},//VT_SYS_CLK_DIV
2464 {0x302A,0x0006},//VT_PIX_CLK_DIV
2465 {0x3038,0x0002},//OP_SYS_CLK_DIV
2466 {0x3036,0x0006},//OP_WORD_CLK_DIV
2467 {0x31B0,0x00BF},//FRAME_PREAMBLE
2468 {0x31B2,0x007D},//LINE_PREAMBLE
2469 {0x31B4,0x834E},//MIPI_TIMING_0
2470 {0x31B6,0x8491},//MIPI_TIMING_1
2471 {0x31B8,0xD0CF},//MIPI_TIMING_2
2472 {0x31BA,0x0515},//MIPI_TIMING_3
2473 {0x31BC,0x1911},//MIPI_TIMING_4
2474 {0x3342,0x122C},//MIPI_F1_PDT_EDT
2475 {0x2510,0x0720},//SEQ_DATA_PORT
2476 {0x2510,0xFFFF},//SEQ_DATA_PORT
2477 {0x2510,0xFFFF},//SEQ_DATA_PORT
2478 {0x2510,0xFFFF},//SEQ_DATA_PORT
2479 {0x2510,0xFFFF},//SEQ_DATA_PORT
2480 {0x2510,0xFFFF},//SEQ_DATA_PORT
2481 {0x2510,0xFFFF},//SEQ_DATA_PORT
2482 {0x2510,0xFFFF},//SEQ_DATA_PORT
2483 {0x2510,0x2122},//SEQ_DATA_PORT
2484 {0x2510,0xFFFF},//SEQ_DATA_PORT
2485 {0x2510,0xFFFF},//SEQ_DATA_PORT
2486 {0x2510,0xFFFF},//SEQ_DATA_PORT
2487 {0x2510,0x26FF},//SEQ_DATA_PORT
2488 {0x2510,0xFFFF},//SEQ_DATA_PORT
2489 {0x2510,0xFFFF},//SEQ_DATA_PORT
2490 {0x2510,0xFFFF},//SEQ_DATA_PORT
2491 {0x2510,0xFFFF},//SEQ_DATA_PORT
2492 {0x2510,0xFFFF},//SEQ_DATA_PORT
2493 {0x2510,0xFFFF},//SEQ_DATA_PORT
2494 {0x2510,0xFFFF},//SEQ_DATA_PORT
2495 {0x2510,0xFFFF},//SEQ_DATA_PORT
2496 {0x2510,0xFFFF},//SEQ_DATA_PORT
2497 {0x2510,0xFFFF},//SEQ_DATA_PORT
2498 {0x2510,0xFFFF},//SEQ_DATA_PORT
2499 {0x2510,0xFFFF},//SEQ_DATA_PORT
2500 {0x2510,0xFFFF},//SEQ_DATA_PORT
2501 {0x2510,0xFFFF},//SEQ_DATA_PORT
2502 {0x2510,0xFFFF},//SEQ_DATA_PORT
2503 {0x2510,0x20FF},//SEQ_DATA_PORT
2504 {0x2510,0x20FF},//SEQ_DATA_PORT
2505 {0x2510,0x20FF},//SEQ_DATA_PORT
2506 {0x2510,0x20FF},//SEQ_DATA_PORT
2507 {0x2510,0x20FF},//SEQ_DATA_PORT
2508 {0x2510,0x20FF},//SEQ_DATA_PORT
2509 {0x2510,0x20FF},//SEQ_DATA_PORT
2510 {0x2510,0x20FF},//SEQ_DATA_PORT
2511 {0x2510,0x20FF},//SEQ_DATA_PORT
2512 {0x2510,0x20FF},//SEQ_DATA_PORT
2513 {0x2510,0x20FF},//SEQ_DATA_PORT
2514 {0x2510,0x20FF},//SEQ_DATA_PORT
2515 {0x2510,0x20FF},//SEQ_DATA_PORT
2516 {0x2510,0x20FF},//SEQ_DATA_PORT
2517 {0x2510,0x20FF},//SEQ_DATA_PORT
2518 {0x2510,0x20FF},//SEQ_DATA_PORT
2519 {0x2510,0x20FF},//SEQ_DATA_PORT
2520 {0x2510,0x0F8C},//SEQ_DATA_PORT
2521 {0x2510,0x20FF},//SEQ_DATA_PORT
2522 {0x2510,0x20FF},//SEQ_DATA_PORT
2523 {0x2510,0x20FF},//SEQ_DATA_PORT
2524 {0x2510,0x20FF},//SEQ_DATA_PORT
2525 {0x2510,0x20FF},//SEQ_DATA_PORT
2526 {0x2510,0x20FF},//SEQ_DATA_PORT
2527 {0x2510,0x20FF},//SEQ_DATA_PORT
2528 {0x2510,0x20FF},//SEQ_DATA_PORT
2529 {0x2510,0x20FF},//SEQ_DATA_PORT
2530 {0x2510,0x20FF},//SEQ_DATA_PORT
2531 {0x2510,0x20FF},//SEQ_DATA_PORT
2532 {0x2510,0x20FF},//SEQ_DATA_PORT
2533 {0x2510,0x20FF},//SEQ_DATA_PORT
2534 {0x2510,0x20FF},//SEQ_DATA_PORT
2535 {0x2510,0x20FF},//SEQ_DATA_PORT
2536 {0x2510,0x20FF},//SEQ_DATA_PORT
2537 {0x2510,0x20FF},//SEQ_DATA_PORT
2538 {0x2510,0x20FF},//SEQ_DATA_PORT
2539 {0x2510,0x20FF},//SEQ_DATA_PORT
2540 {0x2510,0x20FF},//SEQ_DATA_PORT
2541 {0x2510,0x20FF},//SEQ_DATA_PORT
2542 {0x2510,0x20FF},//SEQ_DATA_PORT
2543 {0x2510,0x20FF},//SEQ_DATA_PORT
2544 {0x2510,0x20E0},//SEQ_DATA_PORT
2545 {0x2510,0x8055},//SEQ_DATA_PORT
2546 {0x2510,0xA0E1},//SEQ_DATA_PORT
2547 {0x2510,0x3041},//SEQ_DATA_PORT
2548 {0x2510,0x2000},//SEQ_DATA_PORT
2549 {0x2510,0x3088},//SEQ_DATA_PORT
2550 {0x2510,0x3282},//SEQ_DATA_PORT
2551 {0x2510,0xA681},//SEQ_DATA_PORT
2552 {0x2510,0x20FF},//SEQ_DATA_PORT
2553 {0x2510,0x20FF},//SEQ_DATA_PORT
2554 {0x2510,0x20FF},//SEQ_DATA_PORT
2555 {0x2510,0x20FF},//SEQ_DATA_PORT
2556 {0x2510,0x20FE},//SEQ_DATA_PORT
2557 {0x2510,0x9070},//SEQ_DATA_PORT
2558 {0x2510,0x891D},//SEQ_DATA_PORT
2559 {0x2510,0x867F},//SEQ_DATA_PORT
2560 {0x2510,0x20FF},//SEQ_DATA_PORT
2561 {0x2510,0x20FC},//SEQ_DATA_PORT
2562 {0x2510,0x893F},//SEQ_DATA_PORT
2563 {0x2510,0x0F92},//SEQ_DATA_PORT
2564 {0x2510,0x20E0},//SEQ_DATA_PORT
2565 {0x2510,0x0F8F},//SEQ_DATA_PORT
2566 {0x2510,0x20FF},//SEQ_DATA_PORT
2567 {0x2510,0x20FF},//SEQ_DATA_PORT
2568 {0x2510,0x20FF},//SEQ_DATA_PORT
2569 {0x2510,0x20FF},//SEQ_DATA_PORT
2570 {0x2510,0x20FF},//SEQ_DATA_PORT
2571 {0x2510,0x20E0},//SEQ_DATA_PORT
2572 {0x2510,0x9770},//SEQ_DATA_PORT
2573 {0x2510,0x20FC},//SEQ_DATA_PORT
2574 {0x2510,0x8054},//SEQ_DATA_PORT
2575 {0x2510,0x896C},//SEQ_DATA_PORT
2576 {0x2510,0x200A},//SEQ_DATA_PORT
2577 {0x2510,0x9030},//SEQ_DATA_PORT
2578 {0x2510,0x200A},//SEQ_DATA_PORT
2579 {0x2510,0x8040},//SEQ_DATA_PORT
2580 {0x2510,0x8948},//SEQ_DATA_PORT
2581 {0x2510,0x200A},//SEQ_DATA_PORT
2582 {0x2510,0x1597},//SEQ_DATA_PORT
2583 {0x2510,0x8808},//SEQ_DATA_PORT
2584 {0x2510,0x200A},//SEQ_DATA_PORT
2585 {0x2510,0x1F96},//SEQ_DATA_PORT
2586 {0x2510,0x20FF},//SEQ_DATA_PORT
2587 {0x2510,0x20E0},//SEQ_DATA_PORT
2588 {0x2510,0xA0C0},//SEQ_DATA_PORT
2589 {0x2510,0x200A},//SEQ_DATA_PORT
2590 {0x2510,0x3044},//SEQ_DATA_PORT
2591 {0x2510,0x3088},//SEQ_DATA_PORT
2592 {0x2510,0x3282},//SEQ_DATA_PORT
2593 {0x2510,0x2004},//SEQ_DATA_PORT
2594 {0x2510,0x1FAA},//SEQ_DATA_PORT
2595 {0x2510,0x20FF},//SEQ_DATA_PORT
2596 {0x2510,0x20FF},//SEQ_DATA_PORT
2597 {0x2510,0x20FF},//SEQ_DATA_PORT
2598 {0x2510,0x20FF},//SEQ_DATA_PORT
2599 {0x2510,0x20E0},//SEQ_DATA_PORT
2600 {0x2510,0x7FFF},//SEQ_DATA_PORT
2601 {0x2510,0x7FFF},//SEQ_DATA_PORT
2602 {0x2510,0x7FFF},//SEQ_DATA_PORT
2603 {0x2510,0x20FF},//SEQ_DATA_PORT
2604 {0x2510,0x7FFF},//SEQ_DATA_PORT
2605 {0x2510,0x7FFF},//SEQ_DATA_PORT
2606 {0x2510,0x7FFF},//SEQ_DATA_PORT
2607 {0x2510,0x3108},//SEQ_DATA_PORT
2608 {0x2510,0x2400},//SEQ_DATA_PORT
2609 {0x2510,0x3244},//SEQ_DATA_PORT
2610 {0x2510,0x7FFF},//SEQ_DATA_PORT
2611 {0x2510,0x3108},//SEQ_DATA_PORT
2612 {0x2510,0x2400},//SEQ_DATA_PORT
2613 {0x2510,0x2702},//SEQ_DATA_PORT
2614 {0x2510,0x3242},//SEQ_DATA_PORT
2615 {0x2510,0x3108},//SEQ_DATA_PORT
2616 {0x2510,0x2420},//SEQ_DATA_PORT
2617 {0x2510,0x2703},//SEQ_DATA_PORT
2618 {0x2510,0x3242},//SEQ_DATA_PORT
2619 {0x2510,0x3108},//SEQ_DATA_PORT
2620 {0x2510,0x2420},//SEQ_DATA_PORT
2621 {0x2510,0x2704},//SEQ_DATA_PORT
2622 {0x2510,0x3244},//SEQ_DATA_PORT
2623 {0x2510,0x7FFF},//SEQ_DATA_PORT
2624 {0x2510,0x7FFF},//SEQ_DATA_PORT
2625 {0x2510,0x7FFF},//SEQ_DATA_PORT
2626 {0x2510,0x7FFF},//SEQ_DATA_PORT
2627 {0x2510,0x8801},//SEQ_DATA_PORT
2628 {0x2510,0x010F},//SEQ_DATA_PORT
2629 {0x2510,0x8855},//SEQ_DATA_PORT
2630 {0x2510,0x3101},//SEQ_DATA_PORT
2631 {0x2510,0x3041},//SEQ_DATA_PORT
2632 {0x2510,0x2000},//SEQ_DATA_PORT
2633 {0x2510,0x3102},//SEQ_DATA_PORT
2634 {0x2510,0x3041},//SEQ_DATA_PORT
2635 {0x2510,0x2000},//SEQ_DATA_PORT
2636 {0x2510,0x3181},//SEQ_DATA_PORT
2637 {0x2510,0x3041},//SEQ_DATA_PORT
2638 {0x2510,0x2000},//SEQ_DATA_PORT
2639 {0x2510,0x3188},//SEQ_DATA_PORT
2640 {0x2510,0x3041},//SEQ_DATA_PORT
2641 {0x2510,0x2000},//SEQ_DATA_PORT
2642 {0x2510,0x3282},//SEQ_DATA_PORT
2643 {0x2510,0x3104},//SEQ_DATA_PORT
2644 {0x2510,0x2000},//SEQ_DATA_PORT
2645 {0x2510,0xB0E4},//SEQ_DATA_PORT
2646 {0x2510,0xAD92},//SEQ_DATA_PORT
2647 {0x2510,0xBC0C},//SEQ_DATA_PORT
2648 {0x2510,0x1028},//SEQ_DATA_PORT
2649 {0x2510,0x0022},//SEQ_DATA_PORT
2650 {0x2510,0xC020},//SEQ_DATA_PORT
2651 {0x2510,0x003E},//SEQ_DATA_PORT
2652 {0x2510,0x0045},//SEQ_DATA_PORT
2653 {0x2510,0x00B0},//SEQ_DATA_PORT
2654 {0x2510,0x0028},//SEQ_DATA_PORT
2655 {0x2510,0x30C1},//SEQ_DATA_PORT
2656 {0x2510,0x8015},//SEQ_DATA_PORT
2657 {0x2510,0xA038},//SEQ_DATA_PORT
2658 {0x2510,0x100F},//SEQ_DATA_PORT
2659 {0x2510,0x0507},//SEQ_DATA_PORT
2660 {0x2510,0xA220},//SEQ_DATA_PORT
2661 {0x2510,0x0010},//SEQ_DATA_PORT
2662 {0x2510,0x10C2},//SEQ_DATA_PORT
2663 {0x2510,0xB760},//SEQ_DATA_PORT
2664 {0x2510,0x0033},//SEQ_DATA_PORT
2665 {0x2510,0x1082},//SEQ_DATA_PORT
2666 {0x2510,0x100B},//SEQ_DATA_PORT
2667 {0x2510,0x1029},//SEQ_DATA_PORT
2668 {0x2510,0xA85A},//SEQ_DATA_PORT
2669 {0x2510,0x998D},//SEQ_DATA_PORT
2670 {0x2510,0xC810},//SEQ_DATA_PORT
2671 {0x2510,0x2004},//SEQ_DATA_PORT
2672 {0x2510,0x0CCE},//SEQ_DATA_PORT
2673 {0x2510,0x113B},//SEQ_DATA_PORT
2674 {0x2510,0x1055},//SEQ_DATA_PORT
2675 {0x2510,0x101D},//SEQ_DATA_PORT
2676 {0x2510,0xC000},//SEQ_DATA_PORT
2677 {0x2510,0x052F},//SEQ_DATA_PORT
2678 {0x2510,0x162F},//SEQ_DATA_PORT
2679 {0x2510,0x9000},//SEQ_DATA_PORT
2680 {0x2510,0x2034},//SEQ_DATA_PORT
2681 {0x2510,0x0015},//SEQ_DATA_PORT
2682 {0x2510,0x04CB},//SEQ_DATA_PORT
2683 {0x2510,0x1022},//SEQ_DATA_PORT
2684 {0x2510,0x1031},//SEQ_DATA_PORT
2685 {0x2510,0x002D},//SEQ_DATA_PORT
2686 {0x2510,0x1015},//SEQ_DATA_PORT
2687 {0x2510,0x80B9},//SEQ_DATA_PORT
2688 {0x2510,0xA301},//SEQ_DATA_PORT
2689 {0x2510,0x008E},//SEQ_DATA_PORT
2690 {0x2510,0x124B},//SEQ_DATA_PORT
2691 {0x2510,0x01B5},//SEQ_DATA_PORT
2692 {0x2510,0x0B92},//SEQ_DATA_PORT
2693 {0x2510,0xA400},//SEQ_DATA_PORT
2694 {0x2510,0x8091},//SEQ_DATA_PORT
2695 {0x2510,0x0028},//SEQ_DATA_PORT
2696 {0x2510,0x3002},//SEQ_DATA_PORT
2697 {0x2510,0x2004},//SEQ_DATA_PORT
2698 {0x2510,0x1012},//SEQ_DATA_PORT
2699 {0x2510,0x100E},//SEQ_DATA_PORT
2700 {0x2510,0x10A8},//SEQ_DATA_PORT
2701 {0x2510,0x00A1},//SEQ_DATA_PORT
2702 {0x2510,0x132D},//SEQ_DATA_PORT
2703 {0x2510,0x09AF},//SEQ_DATA_PORT
2704 {0x2510,0x03D9},//SEQ_DATA_PORT
2705 {0x2510,0x1259},//SEQ_DATA_PORT
2706 {0x2510,0x11AF},//SEQ_DATA_PORT
2707 {0x2510,0x18B5},//SEQ_DATA_PORT
2708 {0x2510,0x0395},//SEQ_DATA_PORT
2709 {0x2510,0x05CB},//SEQ_DATA_PORT
2710 {0x2510,0x1021},//SEQ_DATA_PORT
2711 {0x2510,0x1015},//SEQ_DATA_PORT
2712 {0x2510,0x1030},//SEQ_DATA_PORT
2713 {0x2510,0x004F},//SEQ_DATA_PORT
2714 {0x2510,0x001C},//SEQ_DATA_PORT
2715 {0x2510,0xB146},//SEQ_DATA_PORT
2716 {0x2510,0xC090},//SEQ_DATA_PORT
2717 {0x2510,0x0020},//SEQ_DATA_PORT
2718 {0x2510,0x103C},//SEQ_DATA_PORT
2719 {0x2510,0xA882},//SEQ_DATA_PORT
2720 {0x2510,0x8055},//SEQ_DATA_PORT
2721 {0x2510,0x00A9},//SEQ_DATA_PORT
2722 {0x2510,0x8801},//SEQ_DATA_PORT
2723 {0x2510,0xB700},//SEQ_DATA_PORT
2724 {0x2510,0x0001},//SEQ_DATA_PORT
2725 {0x2510,0x00A2},//SEQ_DATA_PORT
2726 {0x2510,0x11AE},//SEQ_DATA_PORT
2727 {0x2510,0x000A},//SEQ_DATA_PORT
2728 {0x2510,0x98BB},//SEQ_DATA_PORT
2729 {0x2510,0x2047},//SEQ_DATA_PORT
2730 {0x2510,0x0036},//SEQ_DATA_PORT
2731 {0x2510,0x1001},//SEQ_DATA_PORT
2732 {0x2510,0x9FBE},//SEQ_DATA_PORT
2733 {0x2510,0x108A},//SEQ_DATA_PORT
2734 {0x2510,0x1022},//SEQ_DATA_PORT
2735 {0x2510,0x0039},//SEQ_DATA_PORT
2736 {0x2510,0x01C0},//SEQ_DATA_PORT
2737 {0x2510,0x109F},//SEQ_DATA_PORT
2738 {0x2510,0x1023},//SEQ_DATA_PORT
2739 {0x2510,0x052E},//SEQ_DATA_PORT
2740 {0x2510,0x002A},//SEQ_DATA_PORT
2741 {0x2510,0x3081},//SEQ_DATA_PORT
2742 {0x2510,0x2001},//SEQ_DATA_PORT
2743 {0x2510,0x3044},//SEQ_DATA_PORT
2744 {0x2510,0x2000},//SEQ_DATA_PORT
2745 {0x2510,0x112A},//SEQ_DATA_PORT
2746 {0x2510,0x101D},//SEQ_DATA_PORT
2747 {0x2510,0x2020},//SEQ_DATA_PORT
2748 {0x2510,0x02B8},//SEQ_DATA_PORT
2749 {0x2510,0x10B8},//SEQ_DATA_PORT
2750 {0x2510,0x1136},//SEQ_DATA_PORT
2751 {0x2510,0x9B6B},//SEQ_DATA_PORT
2752 {0x2510,0x1039},//SEQ_DATA_PORT
2753 {0x2510,0x1040},//SEQ_DATA_PORT
2754 {0x2510,0xAB80},//SEQ_DATA_PORT
2755 {0x2510,0x03C4},//SEQ_DATA_PORT
2756 {0x2510,0x10C4},//SEQ_DATA_PORT
2757 {0x2510,0x1023},//SEQ_DATA_PORT
2758 {0x2510,0x1245},//SEQ_DATA_PORT
2759 {0x2510,0x009F},//SEQ_DATA_PORT
2760 {0x2510,0x002B},//SEQ_DATA_PORT
2761 {0x2510,0x30D0},//SEQ_DATA_PORT
2762 {0x2510,0x3141},//SEQ_DATA_PORT
2763 {0x2510,0x3041},//SEQ_DATA_PORT
2764 {0x2510,0x2000},//SEQ_DATA_PORT
2765 {0x2510,0x3142},//SEQ_DATA_PORT
2766 {0x2510,0x3041},//SEQ_DATA_PORT
2767 {0x2510,0x2000},//SEQ_DATA_PORT
2768 {0x2510,0x3110},//SEQ_DATA_PORT
2769 {0x2510,0x3041},//SEQ_DATA_PORT
2770 {0x2510,0x2000},//SEQ_DATA_PORT
2771 {0x2510,0x3120},//SEQ_DATA_PORT
2772 {0x2510,0x3041},//SEQ_DATA_PORT
2773 {0x2510,0x2000},//SEQ_DATA_PORT
2774 {0x2510,0x3144},//SEQ_DATA_PORT
2775 {0x2510,0x3041},//SEQ_DATA_PORT
2776 {0x2510,0x2000},//SEQ_DATA_PORT
2777 {0x2510,0x3148},//SEQ_DATA_PORT
2778 {0x2510,0x3041},//SEQ_DATA_PORT
2779 {0x2510,0x2000},//SEQ_DATA_PORT
2780 {0x2510,0x3182},//SEQ_DATA_PORT
2781 {0x2510,0x3041},//SEQ_DATA_PORT
2782 {0x2510,0x2000},//SEQ_DATA_PORT
2783 {0x2510,0x3184},//SEQ_DATA_PORT
2784 {0x2510,0x2000},//SEQ_DATA_PORT
2785 {0x2510,0x3190},//SEQ_DATA_PORT
2786 {0x2510,0x3041},//SEQ_DATA_PORT
2787 {0x2510,0x2000},//SEQ_DATA_PORT
2788 {0x2510,0x31A0},//SEQ_DATA_PORT
2789 {0x2510,0x3088},//SEQ_DATA_PORT
2790 {0x2510,0x2201},//SEQ_DATA_PORT
2791 {0x2510,0x807D},//SEQ_DATA_PORT
2792 {0x2510,0x2206},//SEQ_DATA_PORT
2793 {0x2510,0x8815},//SEQ_DATA_PORT
2794 {0x2510,0x8877},//SEQ_DATA_PORT
2795 {0x2510,0x0092},//SEQ_DATA_PORT
2796 {0x2510,0x220E},//SEQ_DATA_PORT
2797 {0x2510,0x2211},//SEQ_DATA_PORT
2798 {0x2510,0x8055},//SEQ_DATA_PORT
2799 {0x2510,0x3001},//SEQ_DATA_PORT
2800 {0x2510,0x2004},//SEQ_DATA_PORT
2801 {0x2510,0x8C61},//SEQ_DATA_PORT
2802 {0x2510,0x8801},//SEQ_DATA_PORT
2803 {0x2510,0x1012},//SEQ_DATA_PORT
2804 {0x2510,0x1D1F},//SEQ_DATA_PORT
2805 {0x2510,0x0D9F},//SEQ_DATA_PORT
2806 {0x2510,0x101F},//SEQ_DATA_PORT
2807 {0x2510,0x0036},//SEQ_DATA_PORT
2808 {0x2510,0x0040},//SEQ_DATA_PORT
2809 {0x2510,0x0023},//SEQ_DATA_PORT
2810 {0x2510,0x996E},//SEQ_DATA_PORT
2811 {0x2510,0x0257},//SEQ_DATA_PORT
2812 {0x2510,0x1035},//SEQ_DATA_PORT
2813 {0x2510,0x9926},//SEQ_DATA_PORT
2814 {0x2510,0x0039},//SEQ_DATA_PORT
2815 {0x2510,0x00AE},//SEQ_DATA_PORT
2816 {0x2510,0x11A3},//SEQ_DATA_PORT
2817 {0x2510,0x0048},//SEQ_DATA_PORT
2818 {0x2510,0xC878},//SEQ_DATA_PORT
2819 {0x2510,0x200A},//SEQ_DATA_PORT
2820 {0x2510,0x1548},//SEQ_DATA_PORT
2821 {0x2510,0x0C49},//SEQ_DATA_PORT
2822 {0x2510,0x1149},//SEQ_DATA_PORT
2823 {0x2510,0x002A},//SEQ_DATA_PORT
2824 {0x2510,0x1057},//SEQ_DATA_PORT
2825 {0x2510,0x3281},//SEQ_DATA_PORT
2826 {0x2510,0x2000},//SEQ_DATA_PORT
2827 {0x2510,0x3044},//SEQ_DATA_PORT
2828 {0x2510,0x2001},//SEQ_DATA_PORT
2829 {0x2510,0xA020},//SEQ_DATA_PORT
2830 {0x2510,0x000C},//SEQ_DATA_PORT
2831 {0x2510,0x9825},//SEQ_DATA_PORT
2832 {0x2510,0x1040},//SEQ_DATA_PORT
2833 {0x2510,0x1054},//SEQ_DATA_PORT
2834 {0x2510,0xB06D},//SEQ_DATA_PORT
2835 {0x2510,0x0035},//SEQ_DATA_PORT
2836 {0x2510,0x004D},//SEQ_DATA_PORT
2837 {0x2510,0x1020},//SEQ_DATA_PORT
2838 {0x2510,0xB064},//SEQ_DATA_PORT
2839 {0x2510,0x99C5},//SEQ_DATA_PORT
2840 {0x2510,0x0047},//SEQ_DATA_PORT
2841 {0x2510,0xB920},//SEQ_DATA_PORT
2842 {0x2510,0x1447},//SEQ_DATA_PORT
2843 {0x2510,0x7FFF},//SEQ_DATA_PORT
2844 {0x2510,0x7FFF},//SEQ_DATA_PORT
2845 {0x2510,0x7FFF},//SEQ_DATA_PORT
2846 {0x2510,0x7FFF},//SEQ_DATA_PORT
2847 {0x2510,0x7FFF},//SEQ_DATA_PORT
2848 {0x2510,0x7FFF},//SEQ_DATA_PORT
2849 {0x2510,0x7FFF},//SEQ_DATA_PORT
2850 {0x31F8,0x0008},//MIPI_CONFIG_2
2851 {0x3C70,0x6828},//CALIB_ROWS
2852 {0x3092,0x0826},//ROW_NOISE_CONTROL
2853 {0x3428,0x0209},//SEQUENCER_CONTROL
2854 {0x3516,0xFF04},//DAC_LD_22_23
2855 {0x3526,0x6480},//DAC_LD_38_39
2856 {0x3504,0x8AAA},//DAC_LD_4_5
2857 {0x353C,0x220C},//DAC_LD_60_61
2858 {0x3536,0x4C6E},//DAC_LD_54_55
2859 {0x3D2A,0x0FFF},//T1_END_DEC_TH
2860 {0x3364,0x00EC},//DCG_TRIM
2861 {0x3512,0x8888},//DAC_LD_18_19
2862 {0x3514,0x888F},//DAC_LD_20_21
2863 {0x3520,0xFBF0},//DAC_LD_32_33
2864 {0x3524,0xB2A1},//DAC_LD_36_37
2865 {0x3528,0xCC84},//DAC_LD_40_41
2866 {0x3532,0x4C8E},//DAC_LD_50_51
2867 {0x3534,0x4E64},//DAC_LD_52_53
2868 {0x351E,0x5856},//DAC_LD_30_31
2869 {0x353E,0x98F2},//DAC_LD_62_63
2870 {0x352E,0x6A8A},//DAC_LD_46_47
2871 {0x3370,0x0211},//DBLC_CONTROL
2872 {0x3372,0x700F},//DBLC_FS0_CONTROL
2873 {0x3540,0x3597},//DAC_LD_64_65
2874 {0x58E2,0x0BE3},//COL_COUNT_VALUES1
2875 {0x58E4,0x18B4},//COL_COUNT_VALUES2
2876 {0x3522,0x7C97},//DAC_LD_34_35
2877 {0x30BA,0x0024},//DIGITAL_CTRL
2878 {0x31D4,0x0042},//CLK_MEM_GATING_CTRL
2879 {0x352A,0x6F8F},//DAC_LD_42_43
2880 {0x3530,0x4A08},//DAC_LD_48_49
2881 {0x351A,0x5FFF},//DAC_LD_26_27
2882 {0x350E,0x39D9},//DAC_LD_14_15
2883 {0x3510,0x9988},//DAC_LD_16_17
2884 {0x3380,0x1FFF},//DBLC_OFFSET1
2885 {0x337A,0x1000},//DBLC_SCALE1
2886 {0x3092,0x0800},//ROW_NOISE_CONTROL
2887 {0x350A,0x0654},//DAC_LD_10_11
2888 {0x3364,0x00E0},//DCG_TRIM
2889 {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA
2890 {0x591E,0x722C},//ANALOG_GAIN_WR_DATA
2891 {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA
2892 {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA
2893 {0x591E,0xA447},//ANALOG_GAIN_WR_DATA
2894 {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA
2895 {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA
2896 {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA
2897 {0x3532,0x4C8A},//DAC_LD_50_51
2898 {0x3534,0x4E60},//DAC_LD_52_53
2899 {0x353E,0x90F2},//DAC_LD_62_63
2900 {0x351A,0x4FFF},//DAC_LD_26_27
2901 {0x591C,0x00D7},//DGR_AMP_GAIN
2902 {0x5002,0x37C3},//T1_PIX_DEF_ID2
2903 {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0
2904 {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1
2905 {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2
2906 {0x51D0,0x0001},//T1_NOISE_FLOOR0
2907 {0x51D2,0x0002},//T1_NOISE_FLOOR1
2908 {0x51D4,0x0003},//T1_NOISE_FLOOR2
2909 {0x51D6,0x0004},//T1_NOISE_FLOOR3
2910 {0x5202,0x37C3},//T2_PIX_DEF_ID2
2911 {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0
2912 {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1
2913 {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2
2914 {0x51EE,0x0001},//T2_NOISE_FLOOR0
2915 {0x51F0,0x0002},//T2_NOISE_FLOOR1
2916 {0x51F2,0x0003},//T2_NOISE_FLOOR2
2917 {0x51F4,0x0004},//T2_NOISE_FLOOR3
2918 {0x5402,0x37C3},//T4_PIX_DEF_ID2
2919 {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0
2920 {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1
2921 {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2
2922 {0x5564,0x0001},//T4_NOISE_FLOOR0
2923 {0x5566,0x0002},//T4_NOISE_FLOOR1
2924 {0x5568,0x0003},//T4_NOISE_FLOOR2
2925 {0x556A,0x0004},//T4_NOISE_FLOOR3
2926 {0x31E0,0x0001},//PIX_DEF_ID
2927 {0x5000,0x0080},//T1_PIX_DEF_ID
2928 {0x5000,0x0180},//T1_PIX_DEF_ID
2929 {0x5000,0x0180},//T1_PIX_DEF_ID
2930 {0x5200,0x0080},//T2_PIX_DEF_ID
2931 {0x5200,0x0180},//T2_PIX_DEF_ID
2932 {0x5200,0x0180},//T2_PIX_DEF_ID
2933 {0x5400,0x0080},//T4_PIX_DEF_ID
2934 {0x5400,0x0180},//T4_PIX_DEF_ID
2935 {0x5400,0x0180},//T4_PIX_DEF_ID
2936 {0x5000,0x0180},//T1_PIX_DEF_ID
2937 {0x5200,0x0180},//T2_PIX_DEF_ID
2938 {0x5400,0x0180},//T4_PIX_DEF_ID
2939 {0x50A2,0x3F2A},//BMT0
2940 {0x50A4,0x875A},//BMT1
2941 {0x50A6,0x030F},//SINGLEK_FACTOR0
2942 {0x50A6,0x0F0F},//SINGLEK_FACTOR0
2943 {0x50A8,0x030F},//SINGLEK_FACTOR1
2944 {0x50A8,0x0F0F},//SINGLEK_FACTOR1
2945 {0x50AA,0x030F},//SINGLEK_FACTOR2
2946 {0x50AA,0x050F},//SINGLEK_FACTOR2
2947 {0x50AC,0x0301},//CROSS_FACTOR0
2948 {0x50AC,0x0101},//CROSS_FACTOR0
2949 {0x50AE,0x0301},//CROSS_FACTOR1
2950 {0x50AE,0x0101},//CROSS_FACTOR1
2951 {0x50B0,0x0301},//CROSS_FACTOR2
2952 {0x50B0,0x0101},//CROSS_FACTOR2
2953 {0x50B2,0x03FF},//SINGLE_MAX_FACTOR
2954 {0x50B4,0x030F},//COUPLE_FACTOR0
2955 {0x50B4,0x0F0F},//COUPLE_FACTOR0
2956 {0x50B6,0x030F},//COUPLE_FACTOR1
2957 {0x50B6,0x0F0F},//COUPLE_FACTOR1
2958 {0x50B8,0x030F},//COUPLE_FACTOR2
2959 {0x50B8,0x050F},//COUPLE_FACTOR2
2960 {0x3D2A,0x0FFF},//T1_END_DEC_TH
2961 {0x3D34,0x9C40},//T2_STR_DEC_TH
2962 {0x3D36,0xFFFF},//T2_END_DEC_TH
2963 {0x3D02,0x5033},//MEC_CTRL2
2964 {0x3D00,0x600F},//MEC_CTRL1
2965 {0x3086,0x1A28},//PARK_ROW_ADDR
2966 {0x33E4,0x0040},//VERT_SHADING_CONTROL
2967 {0x3C70,0x6222},//CALIB_ROWS
2968 {0x3110,0x0011},//HDR_CONTROL0
2969 {0x30B0,0x0820},//DIGITAL_TEST
2970 {0x3280,0x0ED8},//T1_BARRIER_C0
2971 {0x3282,0x0ED8},//T1_BARRIER_C1
2972 {0x3284,0x0ED8},//T1_BARRIER_C2
2973 {0x3286,0x0ED8},//T1_BARRIER_C3
2974 {0x3288,0x0ED8},//T2_BARRIER_C0
2975 {0x328A,0x0ED8},//T2_BARRIER_C1
2976 {0x328C,0x0ED8},//T2_BARRIER_C2
2977 {0x328E,0x0ED8},//T2_BARRIER_C3
2978 {0x3290,0x0ED8},//T3_BARRIER_C0
2979 {0x3292,0x0ED8},//T3_BARRIER_C1
2980 {0x3294,0x0ED8},//T3_BARRIER_C2
2981 {0x3296,0x0ED8},//T3_BARRIER_C3
2982 {0x3100,0xC001},//DLO_CONTROL0
2983 {0x3102,0xBED8},//DLO_CONTROL1
2984 {0x3104,0xBED8},//DLO_CONTROL2
2985 {0x3106,0xBED8},//DLO_CONTROL3
2986 {0x3108,0x07D0},//DLO_CONTROL4
2987 {0x3116,0x4001},//HDR_CONTROL3
2988 {0x3124,0x006D},//HDR_MD_CONTROL0
2989 {0x3126,0x003C},//HDR_MD_CONTROL1
2990 {0x31AE,0x0204},//SERIAL_FORMAT
2991 {0x31AC,0x0C0C},//DATA_FORMAT_BITS
2992 {0x3082,0x0014},//OPERATION_MODE_CTRL
2993 {0x30BA,0x0135},//DIGITAL_CTRL
2994 {0x3238,0x0044},//EXPOSURE_RATIO
2995 {0x3012,0x0700},//COARSE_INTEGRATION_TIME_
2996 {0x3212,0x0070},//COARSE_INTEGRATION_TIME2
2997 {0x300C,0x10CC},//LINE_LENGTH_PCK_
2998 {0x300A,0x09F3},//FRAME_LENGTH_LINES_
2999 {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL
3000 {0x5910,0x608A},//SENSOR_GAIN_REG1
3001 {0x5910,0x7091},//SENSOR_GAIN_REG1
3002 {0x5910,0x689C},//SENSOR_GAIN_REG1
3003 {0x5910,0x8885},//SENSOR_GAIN_REG1
3004 {0x5910,0x98AD},//SENSOR_GAIN_REG1
3005 {0x5910,0xA8A9},//SENSOR_GAIN_REG1
3006 {0x5910,0xC894},//SENSOR_GAIN_REG1
3007 {0x5910,0xC8D1},//SENSOR_GAIN_REG1
3008 {0x5910,0xD88A},//SENSOR_GAIN_REG1
3009 {0x5910,0xD8C3},//SENSOR_GAIN_REG1
3010 {0x5910,0xD915},//SENSOR_GAIN_REG1
3011 {0x5910,0xD988},//SENSOR_GAIN_REG1
3012 {0x5910,0xDA2A},//SENSOR_GAIN_REG1
3013 {0x5910,0xDB0E},//SENSOR_GAIN_REG1
3014 {0x5910,0xDC53},//SENSOR_GAIN_REG1
3015 {0x5910,0x608A},//SENSOR_GAIN_REG1
3016 {0x5910,0xC919},//SENSOR_GAIN_REG1
3017 {0x5910,0xCA00},//SENSOR_GAIN_REG1
3018 {0x5910,0x0000},//SENSOR_GAIN_REG1
3019 {0x5910,0x0000},//SENSOR_GAIN_REG1
3020 {0x5910,0x0000},//SENSOR_GAIN_REG1
3021 {0x5910,0x0001},//SENSOR_GAIN_REG1
3022 {0x5910,0x0001},//SENSOR_GAIN_REG1
3023 {0x5910,0x0003},//SENSOR_GAIN_REG1
3024 {0x5910,0x0003},//SENSOR_GAIN_REG1
3025 {0x5910,0x0003},//SENSOR_GAIN_REG1
3026 {0x5910,0x0004},//SENSOR_GAIN_REG1
3027 {0x5910,0x0004},//SENSOR_GAIN_REG1
3028 {0x5910,0x0004},//SENSOR_GAIN_REG1
3029 {0x5910,0x0004},//SENSOR_GAIN_REG1
3030 {0x5910,0x0004},//SENSOR_GAIN_REG1
3031 {0x5910,0x0004},//SENSOR_GAIN_REG1
3032 {0x5910,0x0004},//SENSOR_GAIN_REG1
3033 {0x5910,0x0002},//SENSOR_GAIN_REG1
3034 {0x5910,0x0003},//SENSOR_GAIN_REG1
3035 {0x5910,0x0003},//SENSOR_GAIN_REG1
3036 {0x5910,0x5A8B},//SENSOR_GAIN_REG1
3037 {0x5910,0xFF04},//SENSOR_GAIN_REG1
3038 {0x5910,0xF704},//SENSOR_GAIN_REG1
3039 {0x5910,0xFF04},//SENSOR_GAIN_REG1
3040 {0x5910,0xF704},//SENSOR_GAIN_REG1
3041 {0x5910,0xF704},//SENSOR_GAIN_REG1
3042 {0x5910,0x0005},//SENSOR_GAIN_REG1
3043 {0x5910,0x0006},//SENSOR_GAIN_REG1
3044 {0x5910,0x0007},//SENSOR_GAIN_REG1
3045 {0x5910,0x9A8B},//SENSOR_GAIN_REG1
3046 {0x5910,0xFF04},//SENSOR_GAIN_REG1
3047 {0x5910,0xF704},//SENSOR_GAIN_REG1
3048 {0x5910,0xF704},//SENSOR_GAIN_REG1
3049 {0x5910,0xF704},//SENSOR_GAIN_REG1
3050 {0x5910,0xF704},//SENSOR_GAIN_REG1
3051 {0x5910,0x0015},//SENSOR_GAIN_REG1
3052 {0x5910,0x0016},//SENSOR_GAIN_REG1
3053 {0x5910,0x0017},//SENSOR_GAIN_REG1
3054 {0x5910,0xDA8B},//SENSOR_GAIN_REG1
3055 {0x5910,0xFF04},//SENSOR_GAIN_REG1
3056 {0x5910,0xF704},//SENSOR_GAIN_REG1
3057 {0x5910,0xF704},//SENSOR_GAIN_REG1
3058 {0x5910,0xF704},//SENSOR_GAIN_REG1
3059 {0x5910,0xF704},//SENSOR_GAIN_REG1
3060 {0x5910,0x0025},//SENSOR_GAIN_REG1
3061 {0x5910,0x0026},//SENSOR_GAIN_REG1
3062 {0x5910,0x0027},//SENSOR_GAIN_REG1
3063 {0x5910,0x59B9},//SENSOR_GAIN_REG1
3064 {0x5910,0x700F},//SENSOR_GAIN_REG1
3065 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3066 {0x5910,0x700F},//SENSOR_GAIN_REG1
3067 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3068 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3069 {0x5910,0x0035},//SENSOR_GAIN_REG1
3070 {0x5910,0x0036},//SENSOR_GAIN_REG1
3071 {0x5910,0x0037},//SENSOR_GAIN_REG1
3072 {0x5910,0x99B9},//SENSOR_GAIN_REG1
3073 {0x5910,0x700F},//SENSOR_GAIN_REG1
3074 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3075 {0x5910,0x700F},//SENSOR_GAIN_REG1
3076 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3077 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3078 {0x5910,0x0045},//SENSOR_GAIN_REG1
3079 {0x5910,0x0046},//SENSOR_GAIN_REG1
3080 {0x5910,0x0047},//SENSOR_GAIN_REG1
3081 {0x5910,0xD9B9},//SENSOR_GAIN_REG1
3082 {0x5910,0x700F},//SENSOR_GAIN_REG1
3083 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3084 {0x5910,0x700F},//SENSOR_GAIN_REG1
3085 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3086 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3087 {0x5910,0x0055},//SENSOR_GAIN_REG1
3088 {0x5910,0x0056},//SENSOR_GAIN_REG1
3089 {0x5910,0x0057},//SENSOR_GAIN_REG1
3090 {0x5910,0x9A85},//SENSOR_GAIN_REG1
3091 {0x5910,0x0654},//SENSOR_GAIN_REG1
3092 {0x5910,0x0654},//SENSOR_GAIN_REG1
3093 {0x5910,0x0684},//SENSOR_GAIN_REG1
3094 {0x5910,0x0654},//SENSOR_GAIN_REG1
3095 {0x5910,0x0654},//SENSOR_GAIN_REG1
3096 {0x5910,0x0065},//SENSOR_GAIN_REG1
3097 {0x5910,0x0066},//SENSOR_GAIN_REG1
3098 {0x5910,0x0067},//SENSOR_GAIN_REG1
3099 {0x5910,0x59BD},//SENSOR_GAIN_REG1
3100 {0x5910,0x1000},//SENSOR_GAIN_REG1
3101 {0x5910,0x0C00},//SENSOR_GAIN_REG1
3102 {0x5910,0x0F00},//SENSOR_GAIN_REG1
3103 {0x5910,0x1000},//SENSOR_GAIN_REG1
3104 {0x5910,0x10F0},//SENSOR_GAIN_REG1
3105 {0x5910,0x0075},//SENSOR_GAIN_REG1
3106 {0x5910,0x0076},//SENSOR_GAIN_REG1
3107 {0x5910,0x0077},//SENSOR_GAIN_REG1
3108 {0x5912,0x608A},//SENSOR_GAIN_REG2
3109 {0x5912,0x7091},//SENSOR_GAIN_REG2
3110 {0x5912,0x689C},//SENSOR_GAIN_REG2
3111 {0x5912,0x8885},//SENSOR_GAIN_REG2
3112 {0x5912,0x98AD},//SENSOR_GAIN_REG2
3113 {0x5912,0xA8A9},//SENSOR_GAIN_REG2
3114 {0x5912,0xC894},//SENSOR_GAIN_REG2
3115 {0x5912,0xC8D1},//SENSOR_GAIN_REG2
3116 {0x5912,0xC927},//SENSOR_GAIN_REG2
3117 {0x5912,0xC9A0},//SENSOR_GAIN_REG2
3118 {0x5912,0xCA4C},//SENSOR_GAIN_REG2
3119 {0x5912,0xCB3F},//SENSOR_GAIN_REG2
3120 {0x5912,0xCC97},//SENSOR_GAIN_REG2
3121 {0x5912,0xCE7C},//SENSOR_GAIN_REG2
3122 {0x5912,0xCFFF},//SENSOR_GAIN_REG2
3123 {0x5912,0x608A},//SENSOR_GAIN_REG2
3124 {0x5912,0xC919},//SENSOR_GAIN_REG2
3125 {0x5912,0xCA00},//SENSOR_GAIN_REG2
3126 {0x5912,0x0000},//SENSOR_GAIN_REG2
3127 {0x5912,0x0000},//SENSOR_GAIN_REG2
3128 {0x5912,0x0000},//SENSOR_GAIN_REG2
3129 {0x5912,0x0001},//SENSOR_GAIN_REG2
3130 {0x5912,0x0001},//SENSOR_GAIN_REG2
3131 {0x5912,0x0003},//SENSOR_GAIN_REG2
3132 {0x5912,0x0003},//SENSOR_GAIN_REG2
3133 {0x5912,0x0003},//SENSOR_GAIN_REG2
3134 {0x5912,0x0004},//SENSOR_GAIN_REG2
3135 {0x5912,0x0004},//SENSOR_GAIN_REG2
3136 {0x5912,0x0004},//SENSOR_GAIN_REG2
3137 {0x5912,0x0004},//SENSOR_GAIN_REG2
3138 {0x5912,0x0004},//SENSOR_GAIN_REG2
3139 {0x5912,0x0004},//SENSOR_GAIN_REG2
3140 {0x5912,0x0004},//SENSOR_GAIN_REG2
3141 {0x5912,0x0002},//SENSOR_GAIN_REG2
3142 {0x5912,0x0003},//SENSOR_GAIN_REG2
3143 {0x5912,0x0003},//SENSOR_GAIN_REG2
3144 {0x5912,0x5A8B},//SENSOR_GAIN_REG2
3145 {0x5912,0xFF04},//SENSOR_GAIN_REG2
3146 {0x5912,0xF704},//SENSOR_GAIN_REG2
3147 {0x5912,0xFF04},//SENSOR_GAIN_REG2
3148 {0x5912,0xF704},//SENSOR_GAIN_REG2
3149 {0x5912,0xF704},//SENSOR_GAIN_REG2
3150 {0x5912,0x0005},//SENSOR_GAIN_REG2
3151 {0x5912,0x0006},//SENSOR_GAIN_REG2
3152 {0x5912,0x0007},//SENSOR_GAIN_REG2
3153 {0x5912,0x9A8B},//SENSOR_GAIN_REG2
3154 {0x5912,0xFF04},//SENSOR_GAIN_REG2
3155 {0x5912,0xF704},//SENSOR_GAIN_REG2
3156 {0x5912,0xF704},//SENSOR_GAIN_REG2
3157 {0x5912,0xF704},//SENSOR_GAIN_REG2
3158 {0x5912,0xF704},//SENSOR_GAIN_REG2
3159 {0x5912,0x0015},//SENSOR_GAIN_REG2
3160 {0x5912,0x0016},//SENSOR_GAIN_REG2
3161 {0x5912,0x0017},//SENSOR_GAIN_REG2
3162 {0x5912,0xDA8B},//SENSOR_GAIN_REG2
3163 {0x5912,0xFF04},//SENSOR_GAIN_REG2
3164 {0x5912,0xF704},//SENSOR_GAIN_REG2
3165 {0x5912,0xF704},//SENSOR_GAIN_REG2
3166 {0x5912,0xF704},//SENSOR_GAIN_REG2
3167 {0x5912,0xF704},//SENSOR_GAIN_REG2
3168 {0x5912,0x0025},//SENSOR_GAIN_REG2
3169 {0x5912,0x0026},//SENSOR_GAIN_REG2
3170 {0x5912,0x0027},//SENSOR_GAIN_REG2
3171 {0x5912,0x59B9},//SENSOR_GAIN_REG2
3172 {0x5912,0x700F},//SENSOR_GAIN_REG2
3173 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3174 {0x5912,0x700F},//SENSOR_GAIN_REG2
3175 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3176 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3177 {0x5912,0x0035},//SENSOR_GAIN_REG2
3178 {0x5912,0x0036},//SENSOR_GAIN_REG2
3179 {0x5912,0x0037},//SENSOR_GAIN_REG2
3180 {0x5912,0x99B9},//SENSOR_GAIN_REG2
3181 {0x5912,0x700F},//SENSOR_GAIN_REG2
3182 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3183 {0x5912,0x700F},//SENSOR_GAIN_REG2
3184 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3185 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3186 {0x5912,0x0045},//SENSOR_GAIN_REG2
3187 {0x5912,0x0046},//SENSOR_GAIN_REG2
3188 {0x5912,0x0047},//SENSOR_GAIN_REG2
3189 {0x5912,0xD9B9},//SENSOR_GAIN_REG2
3190 {0x5912,0x700F},//SENSOR_GAIN_REG2
3191 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3192 {0x5912,0x700F},//SENSOR_GAIN_REG2
3193 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3194 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3195 {0x5912,0x0055},//SENSOR_GAIN_REG2
3196 {0x5912,0x0056},//SENSOR_GAIN_REG2
3197 {0x5912,0x0057},//SENSOR_GAIN_REG2
3198 {0x5912,0x9A85},//SENSOR_GAIN_REG2
3199 {0x5912,0x0654},//SENSOR_GAIN_REG2
3200 {0x5912,0x0654},//SENSOR_GAIN_REG2
3201 {0x5912,0x0684},//SENSOR_GAIN_REG2
3202 {0x5912,0x0654},//SENSOR_GAIN_REG2
3203 {0x5912,0x0654},//SENSOR_GAIN_REG2
3204 {0x5912,0x0065},//SENSOR_GAIN_REG2
3205 {0x5912,0x0066},//SENSOR_GAIN_REG2
3206 {0x5912,0x0067},//SENSOR_GAIN_REG2
3207 {0x5912,0x59BD},//SENSOR_GAIN_REG2
3208 {0x5912,0x1000},//SENSOR_GAIN_REG2
3209 {0x5912,0x0C00},//SENSOR_GAIN_REG2
3210 {0x5912,0x0F00},//SENSOR_GAIN_REG2
3211 {0x5912,0x1000},//SENSOR_GAIN_REG2
3212 {0x5912,0x10F0},//SENSOR_GAIN_REG2
3213 {0x5912,0x0075},//SENSOR_GAIN_REG2
3214 {0x5912,0x0076},//SENSOR_GAIN_REG2
3215 {0x5912,0x0077},//SENSOR_GAIN_REG2
3216 {0x5914,0x4006},//SENSOR_GAIN_TABLE_SEL
3217 {0x5900,0x0020},//SENSOR_GAIN
3218 {0x5902,0x0000},//SENSOR_GAIN_T2
3219 {0x3110,0x0001},//HDR_CONTROL0
3220
3221 {REG_NULL, 0x00},
3222 };
3223
3224 static const struct regval ar0822_linear_60fps_regs[] = {
3225 {REG_DELAY, 2000},
3226 {0x3030,0x0092},//PLL_MULTIPLIER
3227 {0x302E,0x0002},//PRE_PLL_CLK_DIV
3228 {0x302C,0x0002},//VT_SYS_CLK_DIV
3229 {0x302A,0x0006},//VT_PIX_CLK_DIV
3230 {0x3038,0x0002},//OP_SYS_CLK_DIV
3231 {0x3036,0x0006},//OP_WORD_CLK_DIV
3232 {0x31B0,0x00BF},//FRAME_PREAMBLE
3233 {0x31B2,0x007D},//LINE_PREAMBLE
3234 {0x31B4,0x834E},//MIPI_TIMING_0
3235 {0x31B6,0x8491},//MIPI_TIMING_1
3236 {0x31B8,0xD0CF},//MIPI_TIMING_2
3237 {0x31BA,0x0515},//MIPI_TIMING_3
3238 {0x31BC,0x1911},//MIPI_TIMING_4
3239 {0x3342,0x122C},//MIPI_F1_PDT_EDT
3240 {0x31BC,0x5911},//MIPI_TIMING_4
3241 {0x31DE,0x0004},//MIPI_HISPI_TRIM
3242 {0x31C6,0xC000},//HISPI_CONTROL
3243 {0x31C8,0x0B28},//MIPI_DESKEW_PAT_WIDTH
3244 {0x2512,0xA000},//SEQ_CTRL_PORT
3245 {0x2510,0x0720},//SEQ_DATA_PORT
3246 {0x2510,0xFFFF},//SEQ_DATA_PORT
3247 {0x2510,0xFFFF},//SEQ_DATA_PORT
3248 {0x2510,0xFFFF},//SEQ_DATA_PORT
3249 {0x2510,0xFFFF},//SEQ_DATA_PORT
3250 {0x2510,0xFFFF},//SEQ_DATA_PORT
3251 {0x2510,0xFFFF},//SEQ_DATA_PORT
3252 {0x2510,0xFFFF},//SEQ_DATA_PORT
3253 {0x2510,0x2122},//SEQ_DATA_PORT
3254 {0x2510,0xFFFF},//SEQ_DATA_PORT
3255 {0x2510,0xFFFF},//SEQ_DATA_PORT
3256 {0x2510,0xFFFF},//SEQ_DATA_PORT
3257 {0x2510,0x26FF},//SEQ_DATA_PORT
3258 {0x2510,0xFFFF},//SEQ_DATA_PORT
3259 {0x2510,0xFFFF},//SEQ_DATA_PORT
3260 {0x2510,0xFFFF},//SEQ_DATA_PORT
3261 {0x2510,0xFFFF},//SEQ_DATA_PORT
3262 {0x2510,0xFFFF},//SEQ_DATA_PORT
3263 {0x2510,0xFFFF},//SEQ_DATA_PORT
3264 {0x2510,0xFFFF},//SEQ_DATA_PORT
3265 {0x2510,0xFFFF},//SEQ_DATA_PORT
3266 {0x2510,0xFFFF},//SEQ_DATA_PORT
3267 {0x2510,0xFFFF},//SEQ_DATA_PORT
3268 {0x2510,0xFFFF},//SEQ_DATA_PORT
3269 {0x2510,0xFFFF},//SEQ_DATA_PORT
3270 {0x2510,0xFFFF},//SEQ_DATA_PORT
3271 {0x2510,0xFFFF},//SEQ_DATA_PORT
3272 {0x2510,0xFFFF},//SEQ_DATA_PORT
3273 {0x2510,0x20FF},//SEQ_DATA_PORT
3274 {0x2510,0x20FF},//SEQ_DATA_PORT
3275 {0x2510,0x20FF},//SEQ_DATA_PORT
3276 {0x2510,0x20FF},//SEQ_DATA_PORT
3277 {0x2510,0x20FF},//SEQ_DATA_PORT
3278 {0x2510,0x20FF},//SEQ_DATA_PORT
3279 {0x2510,0x20FF},//SEQ_DATA_PORT
3280 {0x2510,0x20FF},//SEQ_DATA_PORT
3281 {0x2510,0x20FF},//SEQ_DATA_PORT
3282 {0x2510,0x20FF},//SEQ_DATA_PORT
3283 {0x2510,0x20FF},//SEQ_DATA_PORT
3284 {0x2510,0x20FF},//SEQ_DATA_PORT
3285 {0x2510,0x20FF},//SEQ_DATA_PORT
3286 {0x2510,0x20FF},//SEQ_DATA_PORT
3287 {0x2510,0x20FF},//SEQ_DATA_PORT
3288 {0x2510,0x20FF},//SEQ_DATA_PORT
3289 {0x2510,0x20FF},//SEQ_DATA_PORT
3290 {0x2510,0x0F8C},//SEQ_DATA_PORT
3291 {0x2510,0x20FF},//SEQ_DATA_PORT
3292 {0x2510,0x20FF},//SEQ_DATA_PORT
3293 {0x2510,0x20FF},//SEQ_DATA_PORT
3294 {0x2510,0x20FF},//SEQ_DATA_PORT
3295 {0x2510,0x20FF},//SEQ_DATA_PORT
3296 {0x2510,0x20FF},//SEQ_DATA_PORT
3297 {0x2510,0x20FF},//SEQ_DATA_PORT
3298 {0x2510,0x20FF},//SEQ_DATA_PORT
3299 {0x2510,0x20FF},//SEQ_DATA_PORT
3300 {0x2510,0x20FF},//SEQ_DATA_PORT
3301 {0x2510,0x20FF},//SEQ_DATA_PORT
3302 {0x2510,0x20FF},//SEQ_DATA_PORT
3303 {0x2510,0x20FF},//SEQ_DATA_PORT
3304 {0x2510,0x20FF},//SEQ_DATA_PORT
3305 {0x2510,0x20FF},//SEQ_DATA_PORT
3306 {0x2510,0x20FF},//SEQ_DATA_PORT
3307 {0x2510,0x20FF},//SEQ_DATA_PORT
3308 {0x2510,0x20FF},//SEQ_DATA_PORT
3309 {0x2510,0x20FF},//SEQ_DATA_PORT
3310 {0x2510,0x20FF},//SEQ_DATA_PORT
3311 {0x2510,0x20FF},//SEQ_DATA_PORT
3312 {0x2510,0x20FF},//SEQ_DATA_PORT
3313 {0x2510,0x20FF},//SEQ_DATA_PORT
3314 {0x2510,0x20E0},//SEQ_DATA_PORT
3315 {0x2510,0x8055},//SEQ_DATA_PORT
3316 {0x2510,0xA0E1},//SEQ_DATA_PORT
3317 {0x2510,0x3041},//SEQ_DATA_PORT
3318 {0x2510,0x2000},//SEQ_DATA_PORT
3319 {0x2510,0x3088},//SEQ_DATA_PORT
3320 {0x2510,0x3282},//SEQ_DATA_PORT
3321 {0x2510,0xA681},//SEQ_DATA_PORT
3322 {0x2510,0x20FF},//SEQ_DATA_PORT
3323 {0x2510,0x20FF},//SEQ_DATA_PORT
3324 {0x2510,0x20FF},//SEQ_DATA_PORT
3325 {0x2510,0x20FF},//SEQ_DATA_PORT
3326 {0x2510,0x20FE},//SEQ_DATA_PORT
3327 {0x2510,0x9070},//SEQ_DATA_PORT
3328 {0x2510,0x891D},//SEQ_DATA_PORT
3329 {0x2510,0x867F},//SEQ_DATA_PORT
3330 {0x2510,0x20FF},//SEQ_DATA_PORT
3331 {0x2510,0x20FC},//SEQ_DATA_PORT
3332 {0x2510,0x893F},//SEQ_DATA_PORT
3333 {0x2510,0x0F92},//SEQ_DATA_PORT
3334 {0x2510,0x20E0},//SEQ_DATA_PORT
3335 {0x2510,0x0F8F},//SEQ_DATA_PORT
3336 {0x2510,0x20FF},//SEQ_DATA_PORT
3337 {0x2510,0x20FF},//SEQ_DATA_PORT
3338 {0x2510,0x20FF},//SEQ_DATA_PORT
3339 {0x2510,0x20FF},//SEQ_DATA_PORT
3340 {0x2510,0x20FF},//SEQ_DATA_PORT
3341 {0x2510,0x20E0},//SEQ_DATA_PORT
3342 {0x2510,0x9770},//SEQ_DATA_PORT
3343 {0x2510,0x20FC},//SEQ_DATA_PORT
3344 {0x2510,0x8054},//SEQ_DATA_PORT
3345 {0x2510,0x896C},//SEQ_DATA_PORT
3346 {0x2510,0x200A},//SEQ_DATA_PORT
3347 {0x2510,0x9030},//SEQ_DATA_PORT
3348 {0x2510,0x200A},//SEQ_DATA_PORT
3349 {0x2510,0x8040},//SEQ_DATA_PORT
3350 {0x2510,0x8948},//SEQ_DATA_PORT
3351 {0x2510,0x200A},//SEQ_DATA_PORT
3352 {0x2510,0x1597},//SEQ_DATA_PORT
3353 {0x2510,0x8808},//SEQ_DATA_PORT
3354 {0x2510,0x200A},//SEQ_DATA_PORT
3355 {0x2510,0x1F96},//SEQ_DATA_PORT
3356 {0x2510,0x20FF},//SEQ_DATA_PORT
3357 {0x2510,0x20E0},//SEQ_DATA_PORT
3358 {0x2510,0xA0C0},//SEQ_DATA_PORT
3359 {0x2510,0x200A},//SEQ_DATA_PORT
3360 {0x2510,0x3044},//SEQ_DATA_PORT
3361 {0x2510,0x3088},//SEQ_DATA_PORT
3362 {0x2510,0x3282},//SEQ_DATA_PORT
3363 {0x2510,0x2004},//SEQ_DATA_PORT
3364 {0x2510,0x1FAA},//SEQ_DATA_PORT
3365 {0x2510,0x20FF},//SEQ_DATA_PORT
3366 {0x2510,0x20FF},//SEQ_DATA_PORT
3367 {0x2510,0x20FF},//SEQ_DATA_PORT
3368 {0x2510,0x20FF},//SEQ_DATA_PORT
3369 {0x2510,0x20E0},//SEQ_DATA_PORT
3370 {0x2510,0x7FFF},//SEQ_DATA_PORT
3371 {0x2510,0x7FFF},//SEQ_DATA_PORT
3372 {0x2510,0x7FFF},//SEQ_DATA_PORT
3373 {0x2510,0x20FF},//SEQ_DATA_PORT
3374 {0x2510,0x7FFF},//SEQ_DATA_PORT
3375 {0x2510,0x7FFF},//SEQ_DATA_PORT
3376 {0x2510,0x7FFF},//SEQ_DATA_PORT
3377 {0x2510,0x3108},//SEQ_DATA_PORT
3378 {0x2510,0x2400},//SEQ_DATA_PORT
3379 {0x2510,0x3244},//SEQ_DATA_PORT
3380 {0x2510,0x7FFF},//SEQ_DATA_PORT
3381 {0x2510,0x3108},//SEQ_DATA_PORT
3382 {0x2510,0x2400},//SEQ_DATA_PORT
3383 {0x2510,0x2702},//SEQ_DATA_PORT
3384 {0x2510,0x3242},//SEQ_DATA_PORT
3385 {0x2510,0x3108},//SEQ_DATA_PORT
3386 {0x2510,0x2420},//SEQ_DATA_PORT
3387 {0x2510,0x2703},//SEQ_DATA_PORT
3388 {0x2510,0x3242},//SEQ_DATA_PORT
3389 {0x2510,0x3108},//SEQ_DATA_PORT
3390 {0x2510,0x2420},//SEQ_DATA_PORT
3391 {0x2510,0x2704},//SEQ_DATA_PORT
3392 {0x2510,0x3244},//SEQ_DATA_PORT
3393 {0x2510,0x7FFF},//SEQ_DATA_PORT
3394 {0x2510,0x7FFF},//SEQ_DATA_PORT
3395 {0x2510,0x7FFF},//SEQ_DATA_PORT
3396 {0x2510,0x7FFF},//SEQ_DATA_PORT
3397 {0x2510,0x8801},//SEQ_DATA_PORT
3398 {0x2510,0x000F},//SEQ_DATA_PORT
3399 {0x2510,0x109C},//SEQ_DATA_PORT
3400 {0x2510,0x8855},//SEQ_DATA_PORT
3401 {0x2510,0x3101},//SEQ_DATA_PORT
3402 {0x2510,0x3041},//SEQ_DATA_PORT
3403 {0x2510,0x2000},//SEQ_DATA_PORT
3404 {0x2510,0x3102},//SEQ_DATA_PORT
3405 {0x2510,0x3041},//SEQ_DATA_PORT
3406 {0x2510,0x2000},//SEQ_DATA_PORT
3407 {0x2510,0x3181},//SEQ_DATA_PORT
3408 {0x2510,0x3041},//SEQ_DATA_PORT
3409 {0x2510,0x2000},//SEQ_DATA_PORT
3410 {0x2510,0x3188},//SEQ_DATA_PORT
3411 {0x2510,0x3041},//SEQ_DATA_PORT
3412 {0x2510,0x2000},//SEQ_DATA_PORT
3413 {0x2510,0x3282},//SEQ_DATA_PORT
3414 {0x2510,0x3104},//SEQ_DATA_PORT
3415 {0x2510,0x2000},//SEQ_DATA_PORT
3416 {0x2510,0xB0E4},//SEQ_DATA_PORT
3417 {0x2510,0xAD92},//SEQ_DATA_PORT
3418 {0x2510,0xBC0C},//SEQ_DATA_PORT
3419 {0x2510,0x1028},//SEQ_DATA_PORT
3420 {0x2510,0x0022},//SEQ_DATA_PORT
3421 {0x2510,0xC020},//SEQ_DATA_PORT
3422 {0x2510,0x003E},//SEQ_DATA_PORT
3423 {0x2510,0x0045},//SEQ_DATA_PORT
3424 {0x2510,0x00B0},//SEQ_DATA_PORT
3425 {0x2510,0x0028},//SEQ_DATA_PORT
3426 {0x2510,0x30C1},//SEQ_DATA_PORT
3427 {0x2510,0x8015},//SEQ_DATA_PORT
3428 {0x2510,0xA038},//SEQ_DATA_PORT
3429 {0x2510,0x100F},//SEQ_DATA_PORT
3430 {0x2510,0x0507},//SEQ_DATA_PORT
3431 {0x2510,0xA220},//SEQ_DATA_PORT
3432 {0x2510,0x0010},//SEQ_DATA_PORT
3433 {0x2510,0x10C2},//SEQ_DATA_PORT
3434 {0x2510,0xB760},//SEQ_DATA_PORT
3435 {0x2510,0x0033},//SEQ_DATA_PORT
3436 {0x2510,0x1082},//SEQ_DATA_PORT
3437 {0x2510,0x100B},//SEQ_DATA_PORT
3438 {0x2510,0x1029},//SEQ_DATA_PORT
3439 {0x2510,0xA85A},//SEQ_DATA_PORT
3440 {0x2510,0x998D},//SEQ_DATA_PORT
3441 {0x2510,0xC810},//SEQ_DATA_PORT
3442 {0x2510,0x2004},//SEQ_DATA_PORT
3443 {0x2510,0x0ECE},//SEQ_DATA_PORT
3444 {0x2510,0x123B},//SEQ_DATA_PORT
3445 {0x2510,0xC000},//SEQ_DATA_PORT
3446 {0x2510,0x032F},//SEQ_DATA_PORT
3447 {0x2510,0x11D5},//SEQ_DATA_PORT
3448 {0x2510,0x162F},//SEQ_DATA_PORT
3449 {0x2510,0x9000},//SEQ_DATA_PORT
3450 {0x2510,0x2034},//SEQ_DATA_PORT
3451 {0x2510,0x0015},//SEQ_DATA_PORT
3452 {0x2510,0x04CB},//SEQ_DATA_PORT
3453 {0x2510,0x1022},//SEQ_DATA_PORT
3454 {0x2510,0x1031},//SEQ_DATA_PORT
3455 {0x2510,0x002D},//SEQ_DATA_PORT
3456 {0x2510,0x1015},//SEQ_DATA_PORT
3457 {0x2510,0x80B9},//SEQ_DATA_PORT
3458 {0x2510,0xA101},//SEQ_DATA_PORT
3459 {0x2510,0x001C},//SEQ_DATA_PORT
3460 {0x2510,0x008E},//SEQ_DATA_PORT
3461 {0x2510,0x124B},//SEQ_DATA_PORT
3462 {0x2510,0x01B5},//SEQ_DATA_PORT
3463 {0x2510,0x0B92},//SEQ_DATA_PORT
3464 {0x2510,0xA400},//SEQ_DATA_PORT
3465 {0x2510,0x8091},//SEQ_DATA_PORT
3466 {0x2510,0x0028},//SEQ_DATA_PORT
3467 {0x2510,0x3002},//SEQ_DATA_PORT
3468 {0x2510,0x2004},//SEQ_DATA_PORT
3469 {0x2510,0x1012},//SEQ_DATA_PORT
3470 {0x2510,0x100E},//SEQ_DATA_PORT
3471 {0x2510,0x10A8},//SEQ_DATA_PORT
3472 {0x2510,0x00A1},//SEQ_DATA_PORT
3473 {0x2510,0x132D},//SEQ_DATA_PORT
3474 {0x2510,0x09AF},//SEQ_DATA_PORT
3475 {0x2510,0x0159},//SEQ_DATA_PORT
3476 {0x2510,0x121D},//SEQ_DATA_PORT
3477 {0x2510,0x1259},//SEQ_DATA_PORT
3478 {0x2510,0x11AF},//SEQ_DATA_PORT
3479 {0x2510,0x18B5},//SEQ_DATA_PORT
3480 {0x2510,0x0395},//SEQ_DATA_PORT
3481 {0x2510,0x054B},//SEQ_DATA_PORT
3482 {0x2510,0x1021},//SEQ_DATA_PORT
3483 {0x2510,0x0020},//SEQ_DATA_PORT
3484 {0x2510,0x1015},//SEQ_DATA_PORT
3485 {0x2510,0x1030},//SEQ_DATA_PORT
3486 {0x2510,0x00CF},//SEQ_DATA_PORT
3487 {0x2510,0xB146},//SEQ_DATA_PORT
3488 {0x2510,0xC290},//SEQ_DATA_PORT
3489 {0x2510,0x103C},//SEQ_DATA_PORT
3490 {0x2510,0xA882},//SEQ_DATA_PORT
3491 {0x2510,0x8055},//SEQ_DATA_PORT
3492 {0x2510,0x00A9},//SEQ_DATA_PORT
3493 {0x2510,0x8801},//SEQ_DATA_PORT
3494 {0x2510,0xB700},//SEQ_DATA_PORT
3495 {0x2510,0x0001},//SEQ_DATA_PORT
3496 {0x2510,0x02A2},//SEQ_DATA_PORT
3497 {0x2510,0x000A},//SEQ_DATA_PORT
3498 {0x2510,0x98BB},//SEQ_DATA_PORT
3499 {0x2510,0x203F},//SEQ_DATA_PORT
3500 {0x2510,0x0036},//SEQ_DATA_PORT
3501 {0x2510,0x1001},//SEQ_DATA_PORT
3502 {0x2510,0x99BE},//SEQ_DATA_PORT
3503 {0x2510,0x0139},//SEQ_DATA_PORT
3504 {0x2510,0x100A},//SEQ_DATA_PORT
3505 {0x2510,0x0040},//SEQ_DATA_PORT
3506 {0x2510,0x1022},//SEQ_DATA_PORT
3507 {0x2510,0x124C},//SEQ_DATA_PORT
3508 {0x2510,0x109F},//SEQ_DATA_PORT
3509 {0x2510,0x15A3},//SEQ_DATA_PORT
3510 {0x2510,0x002A},//SEQ_DATA_PORT
3511 {0x2510,0x3081},//SEQ_DATA_PORT
3512 {0x2510,0x2001},//SEQ_DATA_PORT
3513 {0x2510,0x3044},//SEQ_DATA_PORT
3514 {0x2510,0x2000},//SEQ_DATA_PORT
3515 {0x2510,0x112A},//SEQ_DATA_PORT
3516 {0x2510,0x101D},//SEQ_DATA_PORT
3517 {0x2510,0x202B},//SEQ_DATA_PORT
3518 {0x2510,0x02B8},//SEQ_DATA_PORT
3519 {0x2510,0x10B8},//SEQ_DATA_PORT
3520 {0x2510,0x1136},//SEQ_DATA_PORT
3521 {0x2510,0x996B},//SEQ_DATA_PORT
3522 {0x2510,0x004C},//SEQ_DATA_PORT
3523 {0x2510,0x1039},//SEQ_DATA_PORT
3524 {0x2510,0x1040},//SEQ_DATA_PORT
3525 {0x2510,0x00B5},//SEQ_DATA_PORT
3526 {0x2510,0x03C4},//SEQ_DATA_PORT
3527 {0x2510,0x1144},//SEQ_DATA_PORT
3528 {0x2510,0x1245},//SEQ_DATA_PORT
3529 {0x2510,0x9A7B},//SEQ_DATA_PORT
3530 {0x2510,0x002B},//SEQ_DATA_PORT
3531 {0x2510,0x30D0},//SEQ_DATA_PORT
3532 {0x2510,0x3141},//SEQ_DATA_PORT
3533 {0x2510,0x3041},//SEQ_DATA_PORT
3534 {0x2510,0x2000},//SEQ_DATA_PORT
3535 {0x2510,0x3142},//SEQ_DATA_PORT
3536 {0x2510,0x3041},//SEQ_DATA_PORT
3537 {0x2510,0x2000},//SEQ_DATA_PORT
3538 {0x2510,0x3110},//SEQ_DATA_PORT
3539 {0x2510,0x3041},//SEQ_DATA_PORT
3540 {0x2510,0x2000},//SEQ_DATA_PORT
3541 {0x2510,0x3120},//SEQ_DATA_PORT
3542 {0x2510,0x3041},//SEQ_DATA_PORT
3543 {0x2510,0x2000},//SEQ_DATA_PORT
3544 {0x2510,0x3144},//SEQ_DATA_PORT
3545 {0x2510,0x3041},//SEQ_DATA_PORT
3546 {0x2510,0x2000},//SEQ_DATA_PORT
3547 {0x2510,0x3148},//SEQ_DATA_PORT
3548 {0x2510,0x3041},//SEQ_DATA_PORT
3549 {0x2510,0x2000},//SEQ_DATA_PORT
3550 {0x2510,0x3182},//SEQ_DATA_PORT
3551 {0x2510,0x3041},//SEQ_DATA_PORT
3552 {0x2510,0x2000},//SEQ_DATA_PORT
3553 {0x2510,0x3184},//SEQ_DATA_PORT
3554 {0x2510,0x2000},//SEQ_DATA_PORT
3555 {0x2510,0x3190},//SEQ_DATA_PORT
3556 {0x2510,0x3041},//SEQ_DATA_PORT
3557 {0x2510,0x2000},//SEQ_DATA_PORT
3558 {0x2510,0x31A0},//SEQ_DATA_PORT
3559 {0x2510,0x3088},//SEQ_DATA_PORT
3560 {0x2510,0x2201},//SEQ_DATA_PORT
3561 {0x2510,0x807D},//SEQ_DATA_PORT
3562 {0x2510,0x2206},//SEQ_DATA_PORT
3563 {0x2510,0x8815},//SEQ_DATA_PORT
3564 {0x2510,0x8877},//SEQ_DATA_PORT
3565 {0x2510,0x0092},//SEQ_DATA_PORT
3566 {0x2510,0x220E},//SEQ_DATA_PORT
3567 {0x2510,0x2211},//SEQ_DATA_PORT
3568 {0x2510,0x8055},//SEQ_DATA_PORT
3569 {0x2510,0x3001},//SEQ_DATA_PORT
3570 {0x2510,0x2000},//SEQ_DATA_PORT
3571 {0x2510,0x8A61},//SEQ_DATA_PORT
3572 {0x2510,0x8801},//SEQ_DATA_PORT
3573 {0x2510,0x1092},//SEQ_DATA_PORT
3574 {0x2510,0x181F},//SEQ_DATA_PORT
3575 {0x2510,0x0B1F},//SEQ_DATA_PORT
3576 {0x2510,0x101F},//SEQ_DATA_PORT
3577 {0x2510,0x00B6},//SEQ_DATA_PORT
3578 {0x2510,0x0023},//SEQ_DATA_PORT
3579 {0x2510,0x00B9},//SEQ_DATA_PORT
3580 {0x2510,0x104C},//SEQ_DATA_PORT
3581 {0x2510,0x996E},//SEQ_DATA_PORT
3582 {0x2510,0x0140},//SEQ_DATA_PORT
3583 {0x2510,0x0257},//SEQ_DATA_PORT
3584 {0x2510,0x1035},//SEQ_DATA_PORT
3585 {0x2510,0x9F26},//SEQ_DATA_PORT
3586 {0x2510,0x1423},//SEQ_DATA_PORT
3587 {0x2510,0x0048},//SEQ_DATA_PORT
3588 {0x2510,0xC878},//SEQ_DATA_PORT
3589 {0x2510,0x200A},//SEQ_DATA_PORT
3590 {0x2510,0x1548},//SEQ_DATA_PORT
3591 {0x2510,0x0C49},//SEQ_DATA_PORT
3592 {0x2510,0x1149},//SEQ_DATA_PORT
3593 {0x2510,0x002A},//SEQ_DATA_PORT
3594 {0x2510,0x1057},//SEQ_DATA_PORT
3595 {0x2510,0x3281},//SEQ_DATA_PORT
3596 {0x2510,0x2000},//SEQ_DATA_PORT
3597 {0x2510,0x3044},//SEQ_DATA_PORT
3598 {0x2510,0x2001},//SEQ_DATA_PORT
3599 {0x2510,0xA020},//SEQ_DATA_PORT
3600 {0x2510,0x000C},//SEQ_DATA_PORT
3601 {0x2510,0x9825},//SEQ_DATA_PORT
3602 {0x2510,0x1040},//SEQ_DATA_PORT
3603 {0x2510,0x1054},//SEQ_DATA_PORT
3604 {0x2510,0xB06D},//SEQ_DATA_PORT
3605 {0x2510,0x0035},//SEQ_DATA_PORT
3606 {0x2510,0x004D},//SEQ_DATA_PORT
3607 {0x2510,0x9905},//SEQ_DATA_PORT
3608 {0x2510,0xB064},//SEQ_DATA_PORT
3609 {0x2510,0x99C5},//SEQ_DATA_PORT
3610 {0x2510,0x0047},//SEQ_DATA_PORT
3611 {0x2510,0xB920},//SEQ_DATA_PORT
3612 {0x2510,0x1447},//SEQ_DATA_PORT
3613 {0x2510,0x7FFF},//SEQ_DATA_PORT
3614 {0x2510,0x7FFF},//SEQ_DATA_PORT
3615 {0x2510,0x7FFF},//SEQ_DATA_PORT
3616 {0x2510,0x7FFF},//SEQ_DATA_PORT
3617 {0x2510,0x7FFF},//SEQ_DATA_PORT
3618 {0x2510,0x7FFF},//SEQ_DATA_PORT
3619 {0x2510,0x7FFF},//SEQ_DATA_PORT
3620 {0x2510,0x7FFF},//SEQ_DATA_PORT
3621 {0x2510,0x7FFF},//SEQ_DATA_PORT
3622 {0x31F8,0x0008},//MIPI_CONFIG_2
3623 {0x3C70,0x6828},//CALIB_ROWS
3624 {0x3092,0x0826},//ROW_NOISE_CONTROL
3625 {0x3428,0x0209},//SEQUENCER_CONTROL
3626 {0x3516,0xFF04},//DAC_LD_22_23
3627 {0x3526,0x6480},//DAC_LD_38_39
3628 {0x3504,0x8AAA},//DAC_LD_4_5
3629 {0x353C,0x220C},//DAC_LD_60_61
3630 {0x3536,0x4C6E},//DAC_LD_54_55
3631 {0x3D2A,0x0FFF},//T1_END_DEC_TH
3632 {0x3364,0x00EC},//DCG_TRIM
3633 {0x3512,0x8888},//DAC_LD_18_19
3634 {0x3514,0x888F},//DAC_LD_20_21
3635 {0x3520,0xFBF0},//DAC_LD_32_33
3636 {0x3524,0xB2A1},//DAC_LD_36_37
3637 {0x3528,0xCC84},//DAC_LD_40_41
3638 {0x3532,0x4C8E},//DAC_LD_50_51
3639 {0x3534,0x4E64},//DAC_LD_52_53
3640 {0x351E,0x5856},//DAC_LD_30_31
3641 {0x353E,0x98F2},//DAC_LD_62_63
3642 {0x352E,0x6A8A},//DAC_LD_46_47
3643 {0x3370,0x0211},//DBLC_CONTROL
3644 {0x3372,0x700F},//DBLC_FS0_CONTROL
3645 {0x3540,0x3597},//DAC_LD_64_65
3646 {0x58E2,0x0BE3},//COL_COUNT_VALUES1
3647 {0x58E4,0x18B4},//COL_COUNT_VALUES2
3648 {0x3522,0x7C97},//DAC_LD_34_35
3649 {0x30BA,0x0024},//DIGITAL_CTRL
3650 {0x31D4,0x0042},//CLK_MEM_GATING_CTRL
3651 {0x352A,0x6F8F},//DAC_LD_42_43
3652 {0x3530,0x4A08},//DAC_LD_48_49
3653 {0x351A,0x5FFF},//DAC_LD_26_27
3654 {0x350E,0x39D9},//DAC_LD_14_15
3655 {0x3510,0x9988},//DAC_LD_16_17
3656 {0x3380,0x1FFF},//DBLC_OFFSET1
3657 {0x337A,0x1000},//DBLC_SCALE1
3658 {0x3092,0x0800},//ROW_NOISE_CONTROL
3659 {0x350A,0x0654},//DAC_LD_10_11
3660 {0x3364,0x00E0},//DCG_TRIM
3661 {0x591E,0x61AE},//ANALOG_GAIN_WR_DATA
3662 {0x591E,0x722C},//ANALOG_GAIN_WR_DATA
3663 {0x591E,0x82B8},//ANALOG_GAIN_WR_DATA
3664 {0x591E,0x92F6},//ANALOG_GAIN_WR_DATA
3665 {0x591E,0xA447},//ANALOG_GAIN_WR_DATA
3666 {0x591E,0xB66D},//ANALOG_GAIN_WR_DATA
3667 {0x591E,0xC6EA},//ANALOG_GAIN_WR_DATA
3668 {0x591E,0xDECD},//ANALOG_GAIN_WR_DATA
3669 {0x3532,0x4C8A},//DAC_LD_50_51
3670 {0x3534,0x4E60},//DAC_LD_52_53
3671 {0x353E,0x90F2},//DAC_LD_62_63
3672 {0x351A,0x4FFF},//DAC_LD_26_27
3673 {0x591C,0x00D7},//DGR_AMP_GAIN
3674 {0x3522,0x6097},//DAC_LD_34_35
3675 {0x5002,0x37C3},//T1_PIX_DEF_ID2
3676 {0x51CC,0x0149},//T1_NOISE_GAIN_THRESHOLD0
3677 {0x51D8,0x044D},//T1_NOISE_GAIN_THRESHOLD1
3678 {0x51CE,0x0700},//T1_NOISE_GAIN_THRESHOLD2
3679 {0x51D0,0x0001},//T1_NOISE_FLOOR0
3680 {0x51D2,0x0002},//T1_NOISE_FLOOR1
3681 {0x51D4,0x0003},//T1_NOISE_FLOOR2
3682 {0x51D6,0x0004},//T1_NOISE_FLOOR3
3683 {0x5202,0x37C3},//T2_PIX_DEF_ID2
3684 {0x51EA,0x0149},//T2_NOISE_GAIN_THRESHOLD0
3685 {0x51FC,0x044D},//T2_NOISE_GAIN_THRESHOLD1
3686 {0x51EC,0x0700},//T2_NOISE_GAIN_THRESHOLD2
3687 {0x51EE,0x0001},//T2_NOISE_FLOOR0
3688 {0x51F0,0x0002},//T2_NOISE_FLOOR1
3689 {0x51F2,0x0003},//T2_NOISE_FLOOR2
3690 {0x51F4,0x0004},//T2_NOISE_FLOOR3
3691 {0x5402,0x37C3},//T4_PIX_DEF_ID2
3692 {0x5560,0x0149},//T4_NOISE_GAIN_THRESHOLD0
3693 {0x556C,0x044D},//T4_NOISE_GAIN_THRESHOLD1
3694 {0x5562,0x0700},//T4_NOISE_GAIN_THRESHOLD2
3695 {0x5564,0x0001},//T4_NOISE_FLOOR0
3696 {0x5566,0x0002},//T4_NOISE_FLOOR1
3697 {0x5568,0x0003},//T4_NOISE_FLOOR2
3698 {0x556A,0x0004},//T4_NOISE_FLOOR3
3699 {0x31E0,0x0001},//PIX_DEF_ID
3700 {0x5000,0x0080},//T1_PIX_DEF_ID
3701 {0x5000,0x0180},//T1_PIX_DEF_ID
3702 {0x5000,0x0180},//T1_PIX_DEF_ID
3703 {0x5200,0x0080},//T2_PIX_DEF_ID
3704 {0x5200,0x0180},//T2_PIX_DEF_ID
3705 {0x5200,0x0180},//T2_PIX_DEF_ID
3706 {0x5400,0x0080},//T4_PIX_DEF_ID
3707 {0x5400,0x0180},//T4_PIX_DEF_ID
3708 {0x5400,0x0180},//T4_PIX_DEF_ID
3709 {0x5000,0x1180},//T1_PIX_DEF_ID
3710 {0x50A2,0x2553},//BMT0
3711 {0x50A4,0xDFD4},//BMT1
3712 {0x50A6,0x030F},//SINGLEK_FACTOR0
3713 {0x50A6,0x0F0F},//SINGLEK_FACTOR0
3714 {0x50A8,0x030F},//SINGLEK_FACTOR1
3715 {0x50A8,0x0F0F},//SINGLEK_FACTOR1
3716 {0x50AA,0x030F},//SINGLEK_FACTOR2
3717 {0x50AA,0x050F},//SINGLEK_FACTOR2
3718 {0x50AC,0x0301},//CROSS_FACTOR0
3719 {0x50AC,0x0101},//CROSS_FACTOR0
3720 {0x50AE,0x0301},//CROSS_FACTOR1
3721 {0x50AE,0x0101},//CROSS_FACTOR1
3722 {0x50B0,0x0301},//CROSS_FACTOR2
3723 {0x50B0,0x0101},//CROSS_FACTOR2
3724 {0x50B2,0x03FF},//SINGLE_MAX_FACTOR
3725 {0x50B4,0x030F},//COUPLE_FACTOR0
3726 {0x50B4,0x0F0F},//COUPLE_FACTOR0
3727 {0x50B6,0x030F},//COUPLE_FACTOR1
3728 {0x50B6,0x0F0F},//COUPLE_FACTOR1
3729 {0x50B8,0x030F},//COUPLE_FACTOR2
3730 {0x50B8,0x050F},//COUPLE_FACTOR2
3731 {0x31AE,0x0204},//SERIAL_FORMAT
3732 {0x31AC,0x0C0C},//DATA_FORMAT_BITS
3733 {0x3082,0x0001},//OPERATION_MODE_CTRL
3734 {0x30BA,0x0024},//DIGITAL_CTRL
3735 {0x31AE,0x0204},//SERIAL_FORMAT
3736 {0x31AC,0x0C0C},//DATA_FORMAT_BITS
3737 {0x300C,0x0482},//LINE_LENGTH_PCK_
3738 {0x300A,0x0944},//FRAME_LENGTH_LINES_
3739 {0x3012,0x093E},//COARSE_INTEGRATION_TIME_
3740 {0x5914,0x4012},//SENSOR_GAIN_TABLE_SEL
3741 {REG_DELAY,100},
3742 {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL
3743 {0x5910,0x608A},//SENSOR_GAIN_REG1
3744 {0x5910,0x7091},//SENSOR_GAIN_REG1
3745 {0x5910,0x689C},//SENSOR_GAIN_REG1
3746 {0x5910,0x8885},//SENSOR_GAIN_REG1
3747 {0x5910,0x98AD},//SENSOR_GAIN_REG1
3748 {0x5910,0xA8A9},//SENSOR_GAIN_REG1
3749 {0x5910,0xC894},//SENSOR_GAIN_REG1
3750 {0x5910,0xC8D1},//SENSOR_GAIN_REG1
3751 {0x5910,0xD88A},//SENSOR_GAIN_REG1
3752 {0x5910,0xD8C3},//SENSOR_GAIN_REG1
3753 {0x5910,0xD915},//SENSOR_GAIN_REG1
3754 {0x5910,0xD988},//SENSOR_GAIN_REG1
3755 {0x5910,0xDA2A},//SENSOR_GAIN_REG1
3756 {0x5910,0xDB0E},//SENSOR_GAIN_REG1
3757 {0x5910,0xDC53},//SENSOR_GAIN_REG1
3758 {0x5910,0x608A},//SENSOR_GAIN_REG1
3759 {0x5910,0xC919},//SENSOR_GAIN_REG1
3760 {0x5910,0xCA00},//SENSOR_GAIN_REG1
3761 {0x5910,0x0000},//SENSOR_GAIN_REG1
3762 {0x5910,0x0000},//SENSOR_GAIN_REG1
3763 {0x5910,0x0000},//SENSOR_GAIN_REG1
3764 {0x5910,0x0001},//SENSOR_GAIN_REG1
3765 {0x5910,0x0001},//SENSOR_GAIN_REG1
3766 {0x5910,0x0003},//SENSOR_GAIN_REG1
3767 {0x5910,0x0003},//SENSOR_GAIN_REG1
3768 {0x5910,0x0003},//SENSOR_GAIN_REG1
3769 {0x5910,0x0004},//SENSOR_GAIN_REG1
3770 {0x5910,0x0004},//SENSOR_GAIN_REG1
3771 {0x5910,0x0004},//SENSOR_GAIN_REG1
3772 {0x5910,0x0004},//SENSOR_GAIN_REG1
3773 {0x5910,0x0004},//SENSOR_GAIN_REG1
3774 {0x5910,0x0004},//SENSOR_GAIN_REG1
3775 {0x5910,0x0004},//SENSOR_GAIN_REG1
3776 {0x5910,0x0002},//SENSOR_GAIN_REG1
3777 {0x5910,0x0003},//SENSOR_GAIN_REG1
3778 {0x5910,0x0003},//SENSOR_GAIN_REG1
3779 {0x5910,0x5A8B},//SENSOR_GAIN_REG1
3780 {0x5910,0xFF04},//SENSOR_GAIN_REG1
3781 {0x5910,0xF704},//SENSOR_GAIN_REG1
3782 {0x5910,0xFF04},//SENSOR_GAIN_REG1
3783 {0x5910,0xF704},//SENSOR_GAIN_REG1
3784 {0x5910,0xF704},//SENSOR_GAIN_REG1
3785 {0x5910,0x0005},//SENSOR_GAIN_REG1
3786 {0x5910,0x0006},//SENSOR_GAIN_REG1
3787 {0x5910,0x0007},//SENSOR_GAIN_REG1
3788 {0x5910,0x9A8B},//SENSOR_GAIN_REG1
3789 {0x5910,0xFF04},//SENSOR_GAIN_REG1
3790 {0x5910,0xF704},//SENSOR_GAIN_REG1
3791 {0x5910,0xF704},//SENSOR_GAIN_REG1
3792 {0x5910,0xF704},//SENSOR_GAIN_REG1
3793 {0x5910,0xF704},//SENSOR_GAIN_REG1
3794 {0x5910,0x0015},//SENSOR_GAIN_REG1
3795 {0x5910,0x0016},//SENSOR_GAIN_REG1
3796 {0x5910,0x0017},//SENSOR_GAIN_REG1
3797 {0x5910,0xDA8B},//SENSOR_GAIN_REG1
3798 {0x5910,0xFF04},//SENSOR_GAIN_REG1
3799 {0x5910,0xF704},//SENSOR_GAIN_REG1
3800 {0x5910,0xF704},//SENSOR_GAIN_REG1
3801 {0x5910,0xF704},//SENSOR_GAIN_REG1
3802 {0x5910,0xF704},//SENSOR_GAIN_REG1
3803 {0x5910,0x0025},//SENSOR_GAIN_REG1
3804 {0x5910,0x0026},//SENSOR_GAIN_REG1
3805 {0x5910,0x0027},//SENSOR_GAIN_REG1
3806 {0x5910,0x59B9},//SENSOR_GAIN_REG1
3807 {0x5910,0x700F},//SENSOR_GAIN_REG1
3808 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3809 {0x5910,0x700F},//SENSOR_GAIN_REG1
3810 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3811 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3812 {0x5910,0x0035},//SENSOR_GAIN_REG1
3813 {0x5910,0x0036},//SENSOR_GAIN_REG1
3814 {0x5910,0x0037},//SENSOR_GAIN_REG1
3815 {0x5910,0x99B9},//SENSOR_GAIN_REG1
3816 {0x5910,0x700F},//SENSOR_GAIN_REG1
3817 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3818 {0x5910,0x700F},//SENSOR_GAIN_REG1
3819 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3820 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3821 {0x5910,0x0045},//SENSOR_GAIN_REG1
3822 {0x5910,0x0046},//SENSOR_GAIN_REG1
3823 {0x5910,0x0047},//SENSOR_GAIN_REG1
3824 {0x5910,0xD9B9},//SENSOR_GAIN_REG1
3825 {0x5910,0x700F},//SENSOR_GAIN_REG1
3826 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3827 {0x5910,0x700F},//SENSOR_GAIN_REG1
3828 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3829 {0x5910,0x7F0F},//SENSOR_GAIN_REG1
3830 {0x5910,0x0055},//SENSOR_GAIN_REG1
3831 {0x5910,0x0056},//SENSOR_GAIN_REG1
3832 {0x5910,0x0057},//SENSOR_GAIN_REG1
3833 {0x5910,0x9A85},//SENSOR_GAIN_REG1
3834 {0x5910,0x0654},//SENSOR_GAIN_REG1
3835 {0x5910,0x0654},//SENSOR_GAIN_REG1
3836 {0x5910,0x0684},//SENSOR_GAIN_REG1
3837 {0x5910,0x0654},//SENSOR_GAIN_REG1
3838 {0x5910,0x0654},//SENSOR_GAIN_REG1
3839 {0x5910,0x0065},//SENSOR_GAIN_REG1
3840 {0x5910,0x0066},//SENSOR_GAIN_REG1
3841 {0x5910,0x0067},//SENSOR_GAIN_REG1
3842 {0x5910,0x59BD},//SENSOR_GAIN_REG1
3843 {0x5910,0x1000},//SENSOR_GAIN_REG1
3844 {0x5910,0x0C00},//SENSOR_GAIN_REG1
3845 {0x5910,0x0F00},//SENSOR_GAIN_REG1
3846 {0x5910,0x1000},//SENSOR_GAIN_REG1
3847 {0x5910,0x10F0},//SENSOR_GAIN_REG1
3848 {0x5910,0x0075},//SENSOR_GAIN_REG1
3849 {0x5910,0x0076},//SENSOR_GAIN_REG1
3850 {0x5910,0x0077},//SENSOR_GAIN_REG1
3851 {0x5912,0x608A},//SENSOR_GAIN_REG2
3852 {0x5912,0x7091},//SENSOR_GAIN_REG2
3853 {0x5912,0x689C},//SENSOR_GAIN_REG2
3854 {0x5912,0x8885},//SENSOR_GAIN_REG2
3855 {0x5912,0x98AD},//SENSOR_GAIN_REG2
3856 {0x5912,0xA8A9},//SENSOR_GAIN_REG2
3857 {0x5912,0xC894},//SENSOR_GAIN_REG2
3858 {0x5912,0xC8D1},//SENSOR_GAIN_REG2
3859 {0x5912,0xC927},//SENSOR_GAIN_REG2
3860 {0x5912,0xC9A0},//SENSOR_GAIN_REG2
3861 {0x5912,0xCA4C},//SENSOR_GAIN_REG2
3862 {0x5912,0xCB3F},//SENSOR_GAIN_REG2
3863 {0x5912,0xCC97},//SENSOR_GAIN_REG2
3864 {0x5912,0xCE7C},//SENSOR_GAIN_REG2
3865 {0x5912,0xCFFF},//SENSOR_GAIN_REG2
3866 {0x5912,0x608A},//SENSOR_GAIN_REG2
3867 {0x5912,0xC8F0},//SENSOR_GAIN_REG2
3868 {0x5912,0xCA00},//SENSOR_GAIN_REG2
3869 {0x5912,0x0000},//SENSOR_GAIN_REG2
3870 {0x5912,0x0000},//SENSOR_GAIN_REG2
3871 {0x5912,0x0000},//SENSOR_GAIN_REG2
3872 {0x5912,0x0001},//SENSOR_GAIN_REG2
3873 {0x5912,0x0001},//SENSOR_GAIN_REG2
3874 {0x5912,0x0003},//SENSOR_GAIN_REG2
3875 {0x5912,0x0003},//SENSOR_GAIN_REG2
3876 {0x5912,0x0003},//SENSOR_GAIN_REG2
3877 {0x5912,0x0004},//SENSOR_GAIN_REG2
3878 {0x5912,0x0004},//SENSOR_GAIN_REG2
3879 {0x5912,0x0004},//SENSOR_GAIN_REG2
3880 {0x5912,0x0004},//SENSOR_GAIN_REG2
3881 {0x5912,0x0004},//SENSOR_GAIN_REG2
3882 {0x5912,0x0004},//SENSOR_GAIN_REG2
3883 {0x5912,0x0004},//SENSOR_GAIN_REG2
3884 {0x5912,0x0002},//SENSOR_GAIN_REG2
3885 {0x5912,0x0003},//SENSOR_GAIN_REG2
3886 {0x5912,0x0003},//SENSOR_GAIN_REG2
3887 {0x5912,0x5A8B},//SENSOR_GAIN_REG2
3888 {0x5912,0xFF04},//SENSOR_GAIN_REG2
3889 {0x5912,0xF704},//SENSOR_GAIN_REG2
3890 {0x5912,0xFF04},//SENSOR_GAIN_REG2
3891 {0x5912,0xF704},//SENSOR_GAIN_REG2
3892 {0x5912,0xF704},//SENSOR_GAIN_REG2
3893 {0x5912,0x0005},//SENSOR_GAIN_REG2
3894 {0x5912,0x0006},//SENSOR_GAIN_REG2
3895 {0x5912,0x0007},//SENSOR_GAIN_REG2
3896 {0x5912,0x9A8B},//SENSOR_GAIN_REG2
3897 {0x5912,0xFF04},//SENSOR_GAIN_REG2
3898 {0x5912,0xF704},//SENSOR_GAIN_REG2
3899 {0x5912,0xF704},//SENSOR_GAIN_REG2
3900 {0x5912,0xF704},//SENSOR_GAIN_REG2
3901 {0x5912,0xF704},//SENSOR_GAIN_REG2
3902 {0x5912,0x0015},//SENSOR_GAIN_REG2
3903 {0x5912,0x0016},//SENSOR_GAIN_REG2
3904 {0x5912,0x0017},//SENSOR_GAIN_REG2
3905 {0x5912,0xDA8B},//SENSOR_GAIN_REG2
3906 {0x5912,0xFF04},//SENSOR_GAIN_REG2
3907 {0x5912,0xF704},//SENSOR_GAIN_REG2
3908 {0x5912,0xF704},//SENSOR_GAIN_REG2
3909 {0x5912,0xF704},//SENSOR_GAIN_REG2
3910 {0x5912,0xF704},//SENSOR_GAIN_REG2
3911 {0x5912,0x0025},//SENSOR_GAIN_REG2
3912 {0x5912,0x0026},//SENSOR_GAIN_REG2
3913 {0x5912,0x0027},//SENSOR_GAIN_REG2
3914 {0x5912,0x59B9},//SENSOR_GAIN_REG2
3915 {0x5912,0x700F},//SENSOR_GAIN_REG2
3916 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3917 {0x5912,0x700F},//SENSOR_GAIN_REG2
3918 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3919 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3920 {0x5912,0x0035},//SENSOR_GAIN_REG2
3921 {0x5912,0x0036},//SENSOR_GAIN_REG2
3922 {0x5912,0x0037},//SENSOR_GAIN_REG2
3923 {0x5912,0x99B9},//SENSOR_GAIN_REG2
3924 {0x5912,0x700F},//SENSOR_GAIN_REG2
3925 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3926 {0x5912,0x700F},//SENSOR_GAIN_REG2
3927 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3928 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3929 {0x5912,0x0045},//SENSOR_GAIN_REG2
3930 {0x5912,0x0046},//SENSOR_GAIN_REG2
3931 {0x5912,0x0047},//SENSOR_GAIN_REG2
3932 {0x5912,0xD9B9},//SENSOR_GAIN_REG2
3933 {0x5912,0x700F},//SENSOR_GAIN_REG2
3934 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3935 {0x5912,0x700F},//SENSOR_GAIN_REG2
3936 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3937 {0x5912,0x7F0F},//SENSOR_GAIN_REG2
3938 {0x5912,0x0055},//SENSOR_GAIN_REG2
3939 {0x5912,0x0056},//SENSOR_GAIN_REG2
3940 {0x5912,0x0057},//SENSOR_GAIN_REG2
3941 {0x5912,0x9A85},//SENSOR_GAIN_REG2
3942 {0x5912,0x0654},//SENSOR_GAIN_REG2
3943 {0x5912,0x0654},//SENSOR_GAIN_REG2
3944 {0x5912,0x0684},//SENSOR_GAIN_REG2
3945 {0x5912,0x0654},//SENSOR_GAIN_REG2
3946 {0x5912,0x0654},//SENSOR_GAIN_REG2
3947 {0x5912,0x0065},//SENSOR_GAIN_REG2
3948 {0x5912,0x0066},//SENSOR_GAIN_REG2
3949 {0x5912,0x0067},//SENSOR_GAIN_REG2
3950 {0x5912,0x59BD},//SENSOR_GAIN_REG2
3951 {0x5912,0x1000},//SENSOR_GAIN_REG2
3952 {0x5912,0x0C00},//SENSOR_GAIN_REG2
3953 {0x5912,0x0F00},//SENSOR_GAIN_REG2
3954 {0x5912,0x1000},//SENSOR_GAIN_REG2
3955 {0x5912,0x10F0},//SENSOR_GAIN_REG2
3956 {0x5912,0x0075},//SENSOR_GAIN_REG2
3957 {0x5912,0x0076},//SENSOR_GAIN_REG2
3958 {0x5912,0x0077},//SENSOR_GAIN_REG2
3959 {0x5914,0x4002},//SENSOR_GAIN_TABLE_SEL
3960 {0x5900,0x0000},//SENSOR_GAIN
3961
3962 {REG_NULL, 0x00},
3963 };
3964 static const s64 link_freq_menu_items[] = {
3965 MIPI_FREQ_492M,
3966 MIPI_FREQ_657M,
3967 MIPI_FREQ_823M,
3968 MIPI_FREQ_986M,
3969 };
3970 #define MIPI_FREQ_492M_INDEX 0
3971 #define MIPI_FREQ_657M_INDEX 1
3972 #define MIPI_FREQ_823M_INDEX 2
3973 #define MIPI_FREQ_986M_INDEX 3
3974 #define MIPI_FREQ_MAX_INDEX 4
3975 /*
3976 * The width and height must be configured to be
3977 * the same as the current output resolution of the sensor.
3978 * The input width of the isp needs to be 16 aligned.
3979 * The input height of the isp needs to be 8 aligned.
3980 * If the width or height does not meet the alignment rules,
3981 * you can configure the cropping parameters with the following function to
3982 * crop out the appropriate resolution.
3983 * struct v4l2_subdev_pad_ops {
3984 * .get_selection
3985 * }
3986 */
3987
3988 /* Config resolution ,LLPCLK, FLL, exposure time,fps, MIPI channel config, HDR mode , open.k */
3989 static const struct ar0822_mode supported_modes[] = {
3990 /* {
3991 .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12,
3992 .width = 3840,
3993 .height = 2160,
3994 .max_fps = {
3995 .numerator = 10000,
3996 .denominator = 600000,
3997 },
3998 .exp_def = 0x0240,
3999 .hts_def = 0x4330,//for linear mode, hblank is 4*LINE_LENGTH_PCK_-WIDTH,so hts is 4*LINE_LENGTH_PCK_. not used param by RK.
4000 .vts_def = 0x0944,//used by AEC, should set correctly.
4001 .reg_list = ar0822_linear_60fps_regs,
4002 .hdr_mode = NO_HDR,
4003 .mipi_freq = MIPI_FREQ_986M_INDEX,
4004 .mipi_rate = MIPI_FREQ_986M/AR0822_BPP12*2*AR0822_LANES,
4005 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
4006 },*/
4007 {
4008 .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12,
4009 .width = 3840,
4010 .height = 2160,
4011 .max_fps = {
4012 .numerator = 10000,
4013 .denominator = 300000,
4014 },
4015 .exp_def = 0x0240,
4016 .hts_def = 0x4330,//for linear mode, hblank is 4*LINE_LENGTH_PCK_-WIDTH,so hts is 4*LINE_LENGTH_PCK_. not used param by RK.
4017 .vts_def = 0x09F3,//used by AEC, should set correctly.
4018 .reg_list = ar0822_linear_global_regs,
4019 .hdr_mode = NO_HDR,
4020 .mipi_freq = MIPI_FREQ_492M_INDEX,
4021 .mipi_rate = MIPI_FREQ_492M / AR0822_BPP12 * 2 * AR0822_LANES,
4022 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
4023 },
4024
4025 {
4026 .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12,
4027 .width = 3840,
4028 .height = 2160,
4029 .max_fps = {
4030 .numerator = 10000,
4031 .denominator = 200000,
4032 },
4033 .exp_def = 0x0240,
4034 .hts_def = 0x0E7C*2,//
4035 .vts_def = 0x9b8,//0x0888,//
4036 .reg_list = ar0822_hdr12bit_3840x2160_20fps_regs,
4037 .hdr_mode = HDR_X2,
4038 .mipi_freq = MIPI_FREQ_657M_INDEX,
4039 .mipi_rate = MIPI_FREQ_657M / AR0822_BPP12 * 2 *AR0822_LANES,
4040 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
4041 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
4042 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
4043 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
4044 },
4045
4046 {
4047 .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12,
4048 .width = 3840,
4049 .height = 2160,
4050 .max_fps = {
4051 .numerator = 10000,
4052 .denominator = 250000,
4053 },
4054 .exp_def = 0x0080,
4055 .hts_def = 0x0B98*4-3840,//
4056 .vts_def = 0x0980,//0x0888,//
4057 .reg_list = ar0822_hdr12bit_3840x2160_25fps_regs,
4058 .hdr_mode = HDR_X2,
4059 .mipi_freq = MIPI_FREQ_823M_INDEX,
4060 .mipi_rate = MIPI_FREQ_823M / AR0822_BPP12 * 2 * AR0822_LANES,
4061 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
4062 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,
4063 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
4064 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
4065 },
4066
4067 {
4068 .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12,
4069 .width = 3840,
4070 .height = 2160,
4071 .max_fps = {
4072 .numerator = 10000,
4073 .denominator = 300000,
4074 },
4075 .exp_def = 0x0240,
4076 .hts_def = 0x3430,//for HDR, hblank is 4*LINE_LENGTH_PCK_-WIDTH*2, so hts is 4*LINE_LENGTH_PCK_-WIDTH. param not used by RK.
4077 .vts_def = 0x9F3,//should be set correctly,
4078 .reg_list = ar0822_hdr12bit_3840x2160_30fps_regs,
4079 .hdr_mode = HDR_X2,
4080 .mipi_freq = MIPI_FREQ_986M_INDEX,
4081 .mipi_rate = MIPI_FREQ_986M / AR0822_BPP12 * 2 * AR0822_LANES,
4082 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,
4083 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
4084 },
4085
4086
4087 };
4088
4089
4090 /* use ar0822_enable_test_pattern to config test pattern mode here, open.k */
4091 static const char * const ar0822_test_pattern_menu[] = {
4092 "Disabled",
4093 "Vertical Color Bar Type 1",
4094 "Vertical Color Bar Type 2",
4095 "Vertical Color Bar Type 3",
4096 "Vertical Color Bar Type 4"
4097 };
4098
4099 static int __ar0822_power_on(struct ar0822 *ar0822);
4100
4101 /* Write registers up to 4 at a time */
ar0822_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)4102 static int ar0822_write_reg(struct i2c_client *client, u16 reg,
4103 u32 len, u32 val)
4104 {
4105 u32 buf_i, val_i;
4106 u8 buf[6];
4107 u8 *val_p;
4108 __be32 val_be;
4109
4110 if (len > 4)
4111 return -EINVAL;
4112
4113 buf[0] = reg >> 8;
4114 buf[1] = reg & 0xff;
4115
4116 val_be = cpu_to_be32(val);
4117 val_p = (u8 *)&val_be;
4118 buf_i = 2;
4119 val_i = 4 - len;
4120
4121 while (val_i < 4)
4122 buf[buf_i++] = val_p[val_i++];
4123
4124 if (i2c_master_send(client, buf, len + 2) != len + 2)
4125 return -EIO;
4126
4127 return 0;
4128 }
4129
ar0822_write_array(struct i2c_client * client,const struct regval * regs)4130 static int ar0822_write_array(struct i2c_client *client,
4131 const struct regval *regs)
4132 {
4133 u32 i;
4134 int ret = 0;
4135
4136 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
4137 if (unlikely(regs[i].addr == REG_DELAY))
4138 usleep_range(regs[i].val, regs[i].val * 2);
4139 else
4140 ret |= ar0822_write_reg(client, regs[i].addr,
4141 AR0822_REG_VALUE_16BIT, regs[i].val);
4142 }
4143 return ret;
4144 }
4145
4146 /* Read registers up to 4 at a time */
ar0822_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)4147 static int ar0822_read_reg(struct i2c_client *client,
4148 u16 reg,
4149 unsigned int len,
4150 u32 *val)
4151 {
4152 struct i2c_msg msgs[2];
4153 u8 *data_be_p;
4154 __be32 data_be = 0;
4155 __be16 reg_addr_be = cpu_to_be16(reg);
4156 int ret;
4157
4158 if (len > 4 || !len)
4159 return -EINVAL;
4160
4161 data_be_p = (u8 *)&data_be;
4162 /* Write register address */
4163 msgs[0].addr = client->addr;
4164 msgs[0].flags = 0;
4165 msgs[0].len = 2;
4166 msgs[0].buf = (u8 *)®_addr_be;
4167
4168 /* Read data from register */
4169 msgs[1].addr = client->addr;
4170 msgs[1].flags = I2C_M_RD;
4171 msgs[1].len = len;
4172 msgs[1].buf = &data_be_p[4 - len];
4173
4174 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
4175 if (ret != ARRAY_SIZE(msgs))
4176 return -EIO;
4177
4178 *val = be32_to_cpu(data_be);
4179
4180 return 0;
4181 }
4182
ar0822_get_reso_dist(const struct ar0822_mode * mode,struct v4l2_mbus_framefmt * framefmt)4183 static int ar0822_get_reso_dist(const struct ar0822_mode *mode,
4184 struct v4l2_mbus_framefmt *framefmt)
4185 {
4186 return abs(mode->width - framefmt->width) +
4187 abs(mode->height - framefmt->height);
4188 }
4189
4190 static const struct ar0822_mode *
ar0822_find_best_fit(struct ar0822 * ar0822,struct v4l2_subdev_format * fmt)4191 ar0822_find_best_fit(struct ar0822 *ar0822, struct v4l2_subdev_format *fmt)
4192 {
4193 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
4194 int dist;
4195 int cur_best_fit = 0;
4196 int cur_best_fit_dist = -1;
4197 unsigned int i;
4198
4199 for (i = 0; i < ar0822->cfg_num; i++) {
4200 dist = ar0822_get_reso_dist(&supported_modes[i], framefmt);
4201 if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
4202 (supported_modes[i].bus_fmt == framefmt->code)) {
4203 cur_best_fit_dist = dist;
4204 cur_best_fit = i;
4205 }
4206 }
4207
4208 return &supported_modes[cur_best_fit];
4209 }
ar0822_set_rates(struct ar0822 * ar0822)4210 static int ar0822_set_rates(struct ar0822 *ar0822)
4211 {
4212 const struct ar0822_mode *mode = ar0822->cur_mode;
4213 s64 h_blank, vblank_def;
4214 int ret = 0;
4215
4216 h_blank = mode->hts_def - mode->width;
4217 dev_err(&ar0822->client->dev,
4218 "set format hblank is (%lld), mipi freq: %d, rate: %d\n",
4219 h_blank, mode->mipi_freq,mode->mipi_rate);
4220 __v4l2_ctrl_modify_range(ar0822->hblank, h_blank,
4221 h_blank, 1, h_blank);
4222 vblank_def = mode->vts_def - mode->height;
4223 __v4l2_ctrl_modify_range(ar0822->vblank, vblank_def,
4224 AR0822_VTS_MAX - mode->height,
4225 1, vblank_def);
4226
4227 __v4l2_ctrl_s_ctrl_int64(ar0822->pixel_rate,
4228 mode->mipi_rate);
4229 __v4l2_ctrl_s_ctrl(ar0822->link_freq,
4230 mode->mipi_freq);
4231
4232 return ret;
4233 }
4234 /* setup sensor work format to determine the MIPI speed, open.k */
ar0822_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)4235 static int ar0822_set_fmt(struct v4l2_subdev *sd,
4236 struct v4l2_subdev_pad_config *cfg,
4237 struct v4l2_subdev_format *fmt)
4238 {
4239 struct ar0822 *ar0822 = to_ar0822(sd);
4240 const struct ar0822_mode *mode;
4241
4242 mutex_lock(&ar0822->mutex);
4243
4244 mode = ar0822_find_best_fit(ar0822, fmt);
4245 fmt->format.code = mode->bus_fmt;
4246 fmt->format.width = mode->width;
4247 fmt->format.height = mode->height;
4248 fmt->format.field = V4L2_FIELD_NONE;
4249 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
4250 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
4251 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
4252 #else
4253 mutex_unlock(&ar0822->mutex);
4254 return -ENOTTY;
4255 #endif
4256 } else {
4257 ar0822->cur_mode = mode;
4258 ar0822_set_rates(ar0822);
4259 }
4260
4261 mutex_unlock(&ar0822->mutex);
4262
4263 return 0;
4264 }
4265
ar0822_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)4266 static int ar0822_get_fmt(struct v4l2_subdev *sd,
4267 struct v4l2_subdev_pad_config *cfg,
4268 struct v4l2_subdev_format *fmt)
4269 {
4270 struct ar0822 *ar0822 = to_ar0822(sd);
4271 const struct ar0822_mode *mode = ar0822->cur_mode;
4272
4273 mutex_lock(&ar0822->mutex);
4274 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
4275 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
4276 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
4277 #else
4278 mutex_unlock(&ar0822->mutex);
4279 return -ENOTTY;
4280 #endif
4281 } else {
4282 fmt->format.width = mode->width;
4283 fmt->format.height = mode->height;
4284 fmt->format.code = mode->bus_fmt;
4285 fmt->format.field = V4L2_FIELD_NONE;
4286 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
4287 fmt->reserved[0] = mode->vc[fmt->pad];
4288 else
4289 fmt->reserved[0] = mode->vc[PAD0];
4290 }
4291 mutex_unlock(&ar0822->mutex);
4292
4293 return 0;
4294 }
4295
ar0822_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)4296 static int ar0822_enum_mbus_code(struct v4l2_subdev *sd,
4297 struct v4l2_subdev_pad_config *cfg,
4298 struct v4l2_subdev_mbus_code_enum *code)
4299 {
4300 struct ar0822 *ar0822 = to_ar0822(sd);
4301
4302 if (code->index >= ar0822->cfg_num)
4303 return -EINVAL;
4304 code->code = supported_modes[code->index].bus_fmt;
4305
4306 return 0;
4307 }
4308
ar0822_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)4309 static int ar0822_enum_frame_sizes(struct v4l2_subdev *sd,
4310 struct v4l2_subdev_pad_config *cfg,
4311 struct v4l2_subdev_frame_size_enum *fse)
4312 {
4313 struct ar0822 *ar0822 = to_ar0822(sd);
4314
4315 if (fse->index >= ar0822->cfg_num)
4316 return -EINVAL;
4317
4318 if (fse->code != supported_modes[fse->index].bus_fmt)
4319 return -EINVAL;
4320
4321 fse->min_width = supported_modes[fse->index].width;
4322 fse->max_width = supported_modes[fse->index].width;
4323 fse->max_height = supported_modes[fse->index].height;
4324 fse->min_height = supported_modes[fse->index].height;
4325
4326 return 0;
4327 }
4328 /* use ar0822_enable_test_pattern to config test pattern mode here, open.k */
ar0822_enable_test_pattern(struct ar0822 * ar0822,u32 pattern)4329 static int ar0822_enable_test_pattern(struct ar0822 *ar0822, u32 pattern)
4330 {
4331 int ret = 0;
4332
4333 return ret;
4334 }
4335
ar0822_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)4336 static int ar0822_g_frame_interval(struct v4l2_subdev *sd,
4337 struct v4l2_subdev_frame_interval *fi)
4338 {
4339 struct ar0822 *ar0822 = to_ar0822(sd);
4340 const struct ar0822_mode *mode = ar0822->cur_mode;
4341
4342 mutex_lock(&ar0822->mutex);
4343 fi->interval = mode->max_fps;
4344 mutex_unlock(&ar0822->mutex);
4345
4346 return 0;
4347 }
4348
ar0822_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)4349 static int ar0822_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
4350 struct v4l2_mbus_config *config)
4351 {
4352 struct ar0822 *ar0822 = to_ar0822(sd);
4353 const struct ar0822_mode *mode = ar0822->cur_mode;
4354 u32 val = 0;
4355
4356 val = 1 << (AR0822_LANES - 1) |
4357 V4L2_MBUS_CSI2_CHANNEL_0 |
4358 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
4359 if (mode->hdr_mode != NO_HDR)
4360 val |= V4L2_MBUS_CSI2_CHANNEL_1;
4361 if (mode->hdr_mode == HDR_X3)
4362 val |= V4L2_MBUS_CSI2_CHANNEL_2;
4363
4364 config->type = V4L2_MBUS_CSI2_DPHY;
4365 config->flags = val;
4366
4367 return 0;
4368 }
4369
4370
ar0822_get_module_inf(struct ar0822 * ar0822,struct rkmodule_inf * inf)4371 static void ar0822_get_module_inf(struct ar0822 *ar0822,
4372 struct rkmodule_inf *inf)
4373 {
4374 memset(inf, 0, sizeof(*inf));
4375 strlcpy(inf->base.sensor, AR0822_NAME, sizeof(inf->base.sensor));
4376 strlcpy(inf->base.module, ar0822->module_name,
4377 sizeof(inf->base.module));
4378 strlcpy(inf->base.lens, ar0822->len_name, sizeof(inf->base.lens));
4379 }
4380
ar0822_set_hdrae(struct ar0822 * ar0822,struct preisp_hdrae_exp_s * ae)4381 static int ar0822_set_hdrae(struct ar0822 *ar0822,
4382 struct preisp_hdrae_exp_s *ae)
4383 {
4384 u32 l_exp_time, m_exp_time, s_exp_time;
4385 u32 l_a_gain, m_a_gain, s_a_gain;
4386 int ret = 0;
4387 u8 l_cg_mode = 0;
4388 u8 m_cg_mode = 0;
4389 u8 s_cg_mode = 0;
4390 u32 gain_val = 0;
4391
4392 if (!ar0822->has_init_exp && !ar0822->streaming) {
4393 ar0822->init_hdrae_exp = *ae;
4394 ar0822->has_init_exp = true;
4395 dev_err(&ar0822->client->dev, "ar0822 don't stream, record exp for hdr!\n");
4396 return ret;
4397 }
4398 l_exp_time = ae->long_exp_reg;
4399 m_exp_time = ae->middle_exp_reg;
4400 s_exp_time = ae->short_exp_reg;
4401 l_a_gain = ae->long_gain_reg;
4402 m_a_gain = ae->middle_gain_reg;
4403 s_a_gain = ae->short_gain_reg;
4404 l_cg_mode = ae->long_cg_mode;
4405 m_cg_mode = ae->middle_cg_mode;
4406 s_cg_mode = ae->short_cg_mode;
4407 dev_dbg(&ar0822->client->dev,
4408 "Li-HDR irev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
4409 l_exp_time, l_a_gain,
4410 m_exp_time, m_a_gain,
4411 s_exp_time, s_a_gain);
4412
4413 if (ar0822->cur_mode->hdr_mode == HDR_X2) {
4414 //2 stagger
4415 l_a_gain = m_a_gain;
4416 l_exp_time = m_exp_time;
4417 l_cg_mode = m_cg_mode;
4418 m_a_gain = s_a_gain;
4419 m_exp_time = s_exp_time;
4420 m_cg_mode = s_cg_mode;
4421 }
4422
4423 l_a_gain = (l_a_gain > AR0822_GAIN_MAX) ? AR0822_GAIN_MAX:l_a_gain;
4424 m_a_gain = (m_a_gain > AR0822_GAIN_MAX) ? AR0822_GAIN_MAX:m_a_gain;
4425 s_a_gain = (s_a_gain > AR0822_GAIN_MAX) ? AR0822_GAIN_MAX:s_a_gain;
4426 l_a_gain = (l_a_gain < AR0822_GAIN_MIN) ? AR0822_GAIN_MIN:l_a_gain;
4427 m_a_gain = (m_a_gain < AR0822_GAIN_MIN) ? AR0822_GAIN_MIN:m_a_gain;
4428 s_a_gain = (s_a_gain < AR0822_GAIN_MIN) ? AR0822_GAIN_MIN:s_a_gain;
4429
4430 gain_val = l_a_gain;
4431 ret |= ar0822_write_reg(ar0822->client,
4432 AR0822_GROUP_UPDATE_ADDRESS,
4433 AR0822_REG_VALUE_16BIT,
4434 AR0822_GROUP_UPDATE_START_DATA);
4435
4436 ret |= ar0822_write_reg(ar0822->client,
4437 AR0822_REG_GAIN,
4438 AR0822_REG_VALUE_16BIT, gain_val);
4439
4440 gain_val = m_a_gain;
4441 ret |= ar0822_write_reg(ar0822->client,
4442 AR0822_REG_GAIN2,
4443 AR0822_REG_VALUE_16BIT, gain_val);
4444
4445 if (ar0822->cur_mode->hdr_mode == HDR_X3) {
4446 gain_val = s_a_gain;
4447 ret |= ar0822_write_reg(ar0822->client,
4448 AR0822_REG_GAIN3,
4449 AR0822_REG_VALUE_16BIT, gain_val);
4450 }
4451 ret |= ar0822_write_reg(ar0822->client,
4452 AR0822_REG_EXP,
4453 AR0822_REG_VALUE_16BIT,
4454 l_exp_time);//fixed ratio 1/16 is used here, T2 and T3 is from ratio* T1 or ratio^2* T1.
4455
4456 ret |= ar0822_write_reg(ar0822->client,
4457 AR0822_GROUP_UPDATE_ADDRESS,
4458 AR0822_REG_VALUE_16BIT,
4459 AR0822_GROUP_UPDATE_END_DATA);
4460
4461 dev_dbg(&ar0822->client->dev, "ar0822_set_hdrae exp 0x%x\n",l_exp_time);
4462
4463 return ret;
4464 }
4465
ar0822_set_conversion_gain(struct ar0822 * ar0822,u32 * cg)4466 static int ar0822_set_conversion_gain(struct ar0822 *ar0822, u32 *cg)
4467 {
4468 int ret = 0;
4469 return ret;
4470 }
4471
4472 #ifdef USED_SYS_DEBUG
4473 //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0036-1/cam_s_cg
set_conversion_gain_status(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)4474 static ssize_t set_conversion_gain_status(struct device *dev,
4475 struct device_attribute *attr,
4476 const char *buf,
4477 size_t count)
4478 {
4479 struct i2c_client *client = to_i2c_client(dev);
4480 struct v4l2_subdev *sd = i2c_get_clientdata(client);
4481 struct ar0822 *ar0822 = to_ar0822(sd);
4482 int status = 0;
4483 int ret = 0;
4484
4485 ret = kstrtoint(buf, 0, &status);
4486 if (!ret && status >= 0 && status < 2)
4487 ar0822_set_conversion_gain(ar0822, &status);
4488 else
4489 dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
4490 return count;
4491 }
4492
4493 static struct device_attribute attributes[] = {
4494 __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
4495 };
4496
add_sysfs_interfaces(struct device * dev)4497 static int add_sysfs_interfaces(struct device *dev)
4498 {
4499 int i;
4500
4501 for (i = 0; i < ARRAY_SIZE(attributes); i++)
4502 if (device_create_file(dev, attributes + i))
4503 goto undo;
4504 return 0;
4505 undo:
4506 for (i--; i >= 0 ; i--)
4507 device_remove_file(dev, attributes + i);
4508 dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
4509 return -ENODEV;
4510 }
4511 #endif
4512
ar0822_get_channel_info(struct ar0822 * ar0822,struct rkmodule_channel_info * ch_info)4513 static int ar0822_get_channel_info(struct ar0822 *ar0822, struct rkmodule_channel_info *ch_info)
4514 {
4515 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
4516 return -EINVAL;
4517 ch_info->vc = ar0822->cur_mode->vc[ch_info->index];
4518 ch_info->width = ar0822->cur_mode->width;
4519 ch_info->height = ar0822->cur_mode->height;
4520 ch_info->bus_fmt = ar0822->cur_mode->bus_fmt;
4521 return 0;
4522 }
4523
ar0822_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)4524 static long ar0822_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
4525 {
4526 struct ar0822 *ar0822 = to_ar0822(sd);
4527 struct rkmodule_hdr_cfg *hdr_cfg;
4528 struct rkmodule_channel_info *ch_info;
4529 long ret = 0;
4530 u32 i, h, w;
4531 u32 stream = 0;
4532
4533 switch (cmd) {
4534 case PREISP_CMD_SET_HDRAE_EXP:
4535 ar0822_set_hdrae(ar0822, arg);
4536 break;
4537 case RKMODULE_SET_HDR_CFG:
4538 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
4539 w = ar0822->cur_mode->width;
4540 h = ar0822->cur_mode->height;
4541 for (i = 0; i < ar0822->cfg_num; i++) {
4542 if (w == supported_modes[i].width &&
4543 h == supported_modes[i].height &&
4544 supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
4545 ar0822->cur_mode = &supported_modes[i];
4546 break;
4547 }
4548 }
4549 if (i == ar0822->cfg_num) {
4550 dev_err(&ar0822->client->dev,
4551 "not find hdr mode:%d %dx%d config\n",
4552 hdr_cfg->hdr_mode, w, h);
4553 ret = -EINVAL;
4554 } else {
4555 w = ar0822->cur_mode->hts_def - ar0822->cur_mode->width;
4556 h = ar0822->cur_mode->vts_def - ar0822->cur_mode->height;
4557 dev_info(&ar0822->client->dev,
4558 "set hdr cfg, hblank is (%d)\n", w);
4559 __v4l2_ctrl_modify_range(ar0822->hblank, w, w, 1, w);
4560 __v4l2_ctrl_modify_range(ar0822->vblank, h,
4561 AR0822_VTS_MAX - ar0822->cur_mode->height,
4562 1, h);
4563 dev_info(&ar0822->client->dev,
4564 "sensor mode: %d\n",
4565 ar0822->cur_mode->hdr_mode);
4566 }
4567 ar0822_set_rates(ar0822);
4568 break;
4569 case RKMODULE_GET_MODULE_INFO:
4570 ar0822_get_module_inf(ar0822, (struct rkmodule_inf *)arg);
4571 break;
4572 case RKMODULE_GET_HDR_CFG:
4573 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
4574 hdr_cfg->esp.mode = HDR_NORMAL_VC;
4575 hdr_cfg->hdr_mode = ar0822->cur_mode->hdr_mode;
4576 break;
4577 case RKMODULE_SET_CONVERSION_GAIN:
4578 ret = 0;//ar0822_set_conversion_gain(ar0822, (u32 *)arg);
4579 break;
4580 case RKMODULE_SET_QUICK_STREAM:
4581
4582 stream = *((u32 *)arg);
4583
4584 if (stream)
4585 ret = ar0822_write_reg(ar0822->client, AR0822_REG_CTRL_MODE,
4586 AR0822_REG_VALUE_16BIT, AR0822_MODE_STREAMING);
4587 else
4588 ret = ar0822_write_reg(ar0822->client, AR0822_REG_CTRL_MODE,
4589 AR0822_REG_VALUE_16BIT, AR0822_MODE_SW_STANDBY);
4590 break;
4591 case RKMODULE_GET_CHANNEL_INFO:
4592 ch_info = (struct rkmodule_channel_info *)arg;
4593 ret = ar0822_get_channel_info(ar0822, ch_info);
4594 break;
4595 default:
4596 ret = -ENOIOCTLCMD;
4597 break;
4598 }
4599
4600 return ret;
4601 }
4602
4603 #ifdef CONFIG_COMPAT
ar0822_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)4604 static long ar0822_compat_ioctl32(struct v4l2_subdev *sd,
4605 unsigned int cmd, unsigned long arg)
4606 {
4607 void __user *up = compat_ptr(arg);
4608 struct rkmodule_inf *inf;
4609 struct rkmodule_awb_cfg *cfg;
4610 struct rkmodule_hdr_cfg *hdr;
4611 struct preisp_hdrae_exp_s *hdrae;
4612 struct rkmodule_channel_info *ch_info;
4613 long ret;
4614 u32 cg = 0;
4615 u32 stream = 0;
4616
4617 switch (cmd) {
4618 case RKMODULE_GET_MODULE_INFO:
4619 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
4620 if (!inf) {
4621 ret = -ENOMEM;
4622 return ret;
4623 }
4624
4625 ret = ar0822_ioctl(sd, cmd, inf);
4626 if (!ret)
4627 ret = copy_to_user(up, inf, sizeof(*inf));
4628 kfree(inf);
4629 break;
4630 case RKMODULE_AWB_CFG:
4631 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
4632 if (!cfg) {
4633 ret = -ENOMEM;
4634 return ret;
4635 }
4636
4637 ret = copy_from_user(cfg, up, sizeof(*cfg));
4638 if (!ret)
4639 ret = ar0822_ioctl(sd, cmd, cfg);
4640 kfree(cfg);
4641 break;
4642 case RKMODULE_GET_HDR_CFG:
4643 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
4644 if (!hdr) {
4645 ret = -ENOMEM;
4646 return ret;
4647 }
4648
4649 ret = ar0822_ioctl(sd, cmd, hdr);
4650 if (!ret)
4651 ret = copy_to_user(up, hdr, sizeof(*hdr));
4652 kfree(hdr);
4653 break;
4654 case RKMODULE_SET_HDR_CFG:
4655 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
4656 if (!hdr) {
4657 ret = -ENOMEM;
4658 return ret;
4659 }
4660
4661 ret = copy_from_user(hdr, up, sizeof(*hdr));
4662 if (!ret)
4663 ret = ar0822_ioctl(sd, cmd, hdr);
4664 kfree(hdr);
4665 break;
4666 case PREISP_CMD_SET_HDRAE_EXP:
4667 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
4668 if (!hdrae) {
4669 ret = -ENOMEM;
4670 return ret;
4671 }
4672
4673 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
4674 if (!ret)
4675 ret = ar0822_ioctl(sd, cmd, hdrae);
4676 kfree(hdrae);
4677 break;
4678 case RKMODULE_SET_CONVERSION_GAIN:
4679 ret = copy_from_user(&cg, up, sizeof(cg));
4680 if (!ret)
4681 ret = ar0822_ioctl(sd, cmd, &cg);
4682 break;
4683 case RKMODULE_SET_QUICK_STREAM:
4684 ret = copy_from_user(&stream, up, sizeof(u32));
4685 if (!ret)
4686 ret = ar0822_ioctl(sd, cmd, &stream);
4687 break;
4688 case RKMODULE_GET_CHANNEL_INFO:
4689 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
4690 if (!ch_info) {
4691 ret = -ENOMEM;
4692 return ret;
4693 }
4694
4695 ret = ar0822_ioctl(sd, cmd, ch_info);
4696 if (!ret) {
4697 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
4698 if (ret)
4699 ret = -EFAULT;
4700 }
4701 kfree(ch_info);
4702 break;
4703 default:
4704 ret = -ENOIOCTLCMD;
4705 break;
4706 }
4707
4708 return ret;
4709 }
4710 #endif
4711
__ar0822_start_stream(struct ar0822 * ar0822)4712 static int __ar0822_start_stream(struct ar0822 *ar0822)
4713 {
4714 int ret;
4715
4716 if (!ar0822->is_thunderboot) {
4717 ret = ar0822_write_reg(ar0822->client,
4718 AR0822_SOFTWARE_RESET_REG,
4719 AR0822_REG_VALUE_16BIT,
4720 0x0001);
4721 usleep_range(100000, 200000);
4722 ret = ar0822_write_array(ar0822->client, ar0822->cur_mode->reg_list);
4723 if (ret)
4724 return ret;
4725 }
4726
4727 /* In case these controls are set before streaming */
4728 ret = __v4l2_ctrl_handler_setup(&ar0822->ctrl_handler);
4729 if (ret)
4730 return ret;
4731 if (ar0822->has_init_exp && ar0822->cur_mode->hdr_mode != NO_HDR) {
4732 ret = ar0822_ioctl(&ar0822->subdev, PREISP_CMD_SET_HDRAE_EXP, &ar0822->init_hdrae_exp);
4733 if (ret) {
4734 dev_err(&ar0822->client->dev,
4735 "init exp fail in hdr mode\n");
4736 return ret;
4737 }
4738 dev_err(&ar0822->client->dev,
4739 "init exp success in hdr mode\n");
4740 }
4741 return ar0822_write_reg(ar0822->client, AR0822_REG_CTRL_MODE,
4742 AR0822_REG_VALUE_16BIT, AR0822_MODE_STREAMING);
4743 }
4744
__ar0822_stop_stream(struct ar0822 * ar0822)4745 static int __ar0822_stop_stream(struct ar0822 *ar0822)
4746 {
4747 ar0822->has_init_exp = false;
4748 if (ar0822->is_thunderboot)
4749 ar0822->is_first_streamoff = true;
4750 return ar0822_write_reg(ar0822->client, AR0822_REG_CTRL_MODE,
4751 AR0822_REG_VALUE_16BIT, AR0822_MODE_SW_STANDBY);
4752 }
4753
ar0822_s_stream(struct v4l2_subdev * sd,int on)4754 static int ar0822_s_stream(struct v4l2_subdev *sd, int on)
4755 {
4756 struct ar0822 *ar0822 = to_ar0822(sd);
4757 struct i2c_client *client = ar0822->client;
4758 int ret = 0;
4759
4760 mutex_lock(&ar0822->mutex);
4761 on = !!on;
4762 if (on == ar0822->streaming)
4763 goto unlock_and_return;
4764 if (on) {
4765 if (ar0822->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
4766 ar0822->is_thunderboot = false;
4767 __ar0822_power_on(ar0822);
4768 }
4769 ret = pm_runtime_get_sync(&client->dev);
4770 if (ret < 0) {
4771 pm_runtime_put_noidle(&client->dev);
4772 goto unlock_and_return;
4773 }
4774
4775 ret = __ar0822_start_stream(ar0822);
4776 if (ret) {
4777 v4l2_err(sd, "start stream failed while write regs\n");
4778 pm_runtime_put(&client->dev);
4779 goto unlock_and_return;
4780 }
4781 } else {
4782 __ar0822_stop_stream(ar0822);
4783 pm_runtime_put(&client->dev);
4784 }
4785 ar0822->streaming = on;
4786
4787
4788 unlock_and_return:
4789 mutex_unlock(&ar0822->mutex);
4790
4791 return ret;
4792 }
4793
ar0822_s_power(struct v4l2_subdev * sd,int on)4794 static int ar0822_s_power(struct v4l2_subdev *sd, int on)
4795 {
4796 struct ar0822 *ar0822 = to_ar0822(sd);
4797 struct i2c_client *client = ar0822->client;
4798 int ret = 0;
4799
4800 mutex_lock(&ar0822->mutex);
4801 /* If the power state is not modified - no work to do. */
4802 if (ar0822->power_on == !!on)
4803 goto unlock_and_return;
4804
4805 if (on) {
4806 ret = pm_runtime_get_sync(&client->dev);
4807 if (ret < 0) {
4808 pm_runtime_put_noidle(&client->dev);
4809 goto unlock_and_return;
4810 }
4811
4812 if (!ar0822->is_thunderboot) {
4813 ret |= ar0822_write_reg(ar0822->client,
4814 AR0822_SOFTWARE_RESET_REG,
4815 AR0822_REG_VALUE_16BIT,
4816 0x0001);
4817 usleep_range(100, 200);
4818 }
4819
4820 ar0822->power_on = true;
4821 } else {
4822 pm_runtime_put(&client->dev);
4823 ar0822->power_on = false;
4824 }
4825
4826 unlock_and_return:
4827 mutex_unlock(&ar0822->mutex);
4828
4829 return ret;
4830 }
4831
4832 /* Calculate the delay in us by clock rate and clock cycles */
ar0822_cal_delay(u32 cycles)4833 static inline u32 ar0822_cal_delay(u32 cycles)
4834 {
4835 return DIV_ROUND_UP(cycles, AR0822_XVCLK_FREQ / 1000 / 1000);
4836 }
4837
__ar0822_power_on(struct ar0822 * ar0822)4838 static int __ar0822_power_on(struct ar0822 *ar0822) /* sensor power on config, need check power, MCLK, GPIO etc,,, need go to .dts file to change the config; open.k */
4839 {
4840 int ret;
4841 u32 delay_us;
4842 struct device *dev = &ar0822->client->dev;
4843
4844 if (ar0822->is_thunderboot)
4845 return 0;
4846
4847 if (!IS_ERR_OR_NULL(ar0822->pins_default)) {
4848 ret = pinctrl_select_state(ar0822->pinctrl,
4849 ar0822->pins_default);
4850 if (ret < 0)
4851 dev_err(dev, "could not set pins\n");
4852 }
4853 ret = clk_set_rate(ar0822->xvclk, AR0822_XVCLK_FREQ);
4854 if (ret < 0)
4855 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
4856 if (clk_get_rate(ar0822->xvclk) != AR0822_XVCLK_FREQ)
4857 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
4858 ret = clk_prepare_enable(ar0822->xvclk);
4859 if (ret < 0) {
4860 dev_err(dev, "Failed to enable xvclk\n");
4861 return ret;
4862 }
4863 if (!IS_ERR(ar0822->reset_gpio))
4864 gpiod_direction_output(ar0822->reset_gpio, 1);
4865
4866 ret = regulator_bulk_enable(AR0822_NUM_SUPPLIES, ar0822->supplies);
4867 if (ret < 0) {
4868 dev_err(dev, "Failed to enable regulators\n");
4869 goto disable_clk;
4870 }
4871
4872 if (!IS_ERR(ar0822->reset_gpio))
4873 gpiod_direction_output(ar0822->reset_gpio, 0);
4874
4875 usleep_range(500, 1000);
4876 if (!IS_ERR(ar0822->pwdn_gpio))
4877 gpiod_direction_output(ar0822->pwdn_gpio, 1);
4878 /*
4879 * There is no need to wait for the delay of RC circuit
4880 * if the reset signal is directly controlled by GPIO.
4881 */
4882 if (!IS_ERR(ar0822->reset_gpio))
4883 usleep_range(6000, 8000);
4884 else
4885 usleep_range(12000, 16000);
4886
4887 /* 8192 cycles prior to first SCCB transaction */
4888 delay_us = ar0822_cal_delay(8192);
4889 usleep_range(delay_us, delay_us * 2);
4890
4891 return 0;
4892
4893 disable_clk:
4894 clk_disable_unprepare(ar0822->xvclk);
4895
4896 return ret;
4897 }
4898
__ar0822_power_off(struct ar0822 * ar0822)4899 static void __ar0822_power_off(struct ar0822 *ar0822)
4900 {
4901 int ret;
4902 struct device *dev = &ar0822->client->dev;
4903
4904 if (ar0822->is_thunderboot) {
4905 if (ar0822->is_first_streamoff) {
4906 ar0822->is_thunderboot = false;
4907 ar0822->is_first_streamoff = false;
4908 } else {
4909 return;
4910 }
4911 }
4912
4913 if (!IS_ERR(ar0822->pwdn_gpio))
4914 gpiod_direction_output(ar0822->pwdn_gpio, 0);
4915
4916 clk_disable_unprepare(ar0822->xvclk);
4917
4918 if (!IS_ERR(ar0822->reset_gpio))
4919 gpiod_direction_output(ar0822->reset_gpio, 0);
4920 if (!IS_ERR_OR_NULL(ar0822->pins_sleep)) {
4921 ret = pinctrl_select_state(ar0822->pinctrl,
4922 ar0822->pins_sleep);
4923 if (ret < 0)
4924 dev_dbg(dev, "could not set pins\n");
4925 }
4926
4927 if (ar0822->is_thunderboot_ng) {
4928 ar0822->is_thunderboot_ng = false;
4929 regulator_bulk_disable(AR0822_NUM_SUPPLIES, ar0822->supplies);
4930 }
4931 }
4932
ar0822_runtime_resume(struct device * dev)4933 static int ar0822_runtime_resume(struct device *dev)
4934 {
4935 struct i2c_client *client = to_i2c_client(dev);
4936 struct v4l2_subdev *sd = i2c_get_clientdata(client);
4937 struct ar0822 *ar0822 = to_ar0822(sd);
4938
4939 return __ar0822_power_on(ar0822);
4940 }
4941
ar0822_runtime_suspend(struct device * dev)4942 static int ar0822_runtime_suspend(struct device *dev)
4943 {
4944 struct i2c_client *client = to_i2c_client(dev);
4945 struct v4l2_subdev *sd = i2c_get_clientdata(client);
4946 struct ar0822 *ar0822 = to_ar0822(sd);
4947
4948 __ar0822_power_off(ar0822);
4949
4950 return 0;
4951 }
4952
4953 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ar0822_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)4954 static int ar0822_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
4955 {
4956 struct ar0822 *ar0822 = to_ar0822(sd);
4957 struct v4l2_mbus_framefmt *try_fmt =
4958 v4l2_subdev_get_try_format(sd, fh->pad, 0);
4959 const struct ar0822_mode *def_mode = &supported_modes[0];
4960 mutex_lock(&ar0822->mutex);
4961 /* Initialize try_fmt */
4962 try_fmt->width = def_mode->width;
4963 try_fmt->height = def_mode->height;
4964 try_fmt->code = def_mode->bus_fmt;
4965 try_fmt->field = V4L2_FIELD_NONE;
4966
4967 mutex_unlock(&ar0822->mutex);
4968 /* No crop or compose */
4969
4970 return 0;
4971 }
4972 #endif
4973
ar0822_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)4974 static int ar0822_enum_frame_interval(struct v4l2_subdev *sd,
4975 struct v4l2_subdev_pad_config *cfg,
4976 struct v4l2_subdev_frame_interval_enum *fie)
4977 {
4978 struct ar0822 *ar0822 = to_ar0822(sd);
4979
4980 if (fie->index >= ar0822->cfg_num)
4981 return -EINVAL;
4982 fie->code = supported_modes[fie->index].bus_fmt;
4983 fie->width = supported_modes[fie->index].width;
4984 fie->height = supported_modes[fie->index].height;
4985 fie->interval = supported_modes[fie->index].max_fps;
4986 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
4987 return 0;
4988 }
4989
4990 static const struct dev_pm_ops ar0822_pm_ops = {
4991 SET_RUNTIME_PM_OPS(ar0822_runtime_suspend,
4992 ar0822_runtime_resume, NULL)
4993 };
4994
4995 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
4996 static const struct v4l2_subdev_internal_ops ar0822_internal_ops = {
4997 .open = ar0822_open,
4998 };
4999 #endif
5000
5001 static const struct v4l2_subdev_core_ops ar0822_core_ops = {
5002 .s_power = ar0822_s_power,
5003 .ioctl = ar0822_ioctl,
5004 #ifdef CONFIG_COMPAT
5005 .compat_ioctl32 = ar0822_compat_ioctl32,
5006 #endif
5007 };
5008
5009 static const struct v4l2_subdev_video_ops ar0822_video_ops = {
5010 .s_stream = ar0822_s_stream,
5011 .g_frame_interval = ar0822_g_frame_interval,
5012 };
5013
5014 static const struct v4l2_subdev_pad_ops ar0822_pad_ops = {
5015 .enum_mbus_code = ar0822_enum_mbus_code,
5016 .enum_frame_size = ar0822_enum_frame_sizes,
5017 .enum_frame_interval = ar0822_enum_frame_interval,
5018 .get_fmt = ar0822_get_fmt,
5019 .set_fmt = ar0822_set_fmt,
5020 .get_mbus_config = ar0822_g_mbus_config,
5021 };
5022
5023 static const struct v4l2_subdev_ops ar0822_subdev_ops = {
5024 .core = &ar0822_core_ops,
5025 .video = &ar0822_video_ops,
5026 .pad = &ar0822_pad_ops,
5027 };
5028
5029
ar0822_set_ctrl(struct v4l2_ctrl * ctrl)5030 static int ar0822_set_ctrl(struct v4l2_ctrl *ctrl)
5031 {
5032 struct ar0822 *ar0822 = container_of(ctrl->handler,
5033 struct ar0822, ctrl_handler);
5034 struct i2c_client *client = ar0822->client;
5035 s64 max;
5036 int ret = 0;
5037 u32 again = 0;
5038 u32 val = 0;
5039
5040 /* Propagate change of current control to all related controls */
5041 switch (ctrl->id) {
5042 case V4L2_CID_VBLANK:
5043 /* Update max exposure while meeting expected vblanking */
5044 max = ar0822->cur_mode->height + ctrl->val - 4;
5045 __v4l2_ctrl_modify_range(ar0822->exposure,
5046 ar0822->exposure->minimum, max,
5047 ar0822->exposure->step,
5048 ar0822->exposure->default_value);
5049 break;
5050 }
5051
5052 if (!pm_runtime_get_if_in_use(&client->dev))
5053 return 0;
5054
5055 switch (ctrl->id) {
5056 case V4L2_CID_EXPOSURE:
5057 if (ar0822->cur_mode->hdr_mode != NO_HDR)
5058 goto ctrl_end;
5059 ret = ar0822_write_reg(ar0822->client,
5060 AR0822_REG_EXP,
5061 AR0822_REG_VALUE_16BIT,
5062 ctrl->val);
5063
5064 dev_dbg(&client->dev, "set exposure 0x%x\n",
5065 ctrl->val);
5066 break;
5067 case V4L2_CID_ANALOGUE_GAIN:
5068 if (ar0822->cur_mode->hdr_mode != NO_HDR)
5069 goto ctrl_end;
5070 if (ctrl->val > AR0822_GAIN_MAX) {
5071 again = AR0822_GAIN_MAX;
5072 } else {
5073 again = ctrl->val;
5074 }
5075 if (ctrl->val < AR0822_GAIN_MIN) {
5076 again = AR0822_GAIN_MIN;
5077 } else {
5078 again = ctrl->val;
5079 }
5080
5081 val = again;
5082 ret = ar0822_write_reg(ar0822->client,
5083 AR0822_REG_GAIN,
5084 AR0822_REG_VALUE_16BIT,
5085 val);
5086
5087 dev_dbg(&client->dev, "Corn set analog gain 0x%x\n",
5088 ctrl->val);
5089 break;
5090 case V4L2_CID_VBLANK:
5091 //ret = ar0822_write_reg(ar0822->client, AR0822_REG_VTS,
5092 // AR0822_REG_VALUE_16BIT,
5093 // ctrl->val + ar0822->cur_mode->height);
5094 dev_dbg(&client->dev, "set vblank 0x%x\n",
5095 ctrl->val);
5096 break;
5097 case V4L2_CID_TEST_PATTERN:
5098 ret = ar0822_enable_test_pattern(ar0822, ctrl->val);
5099 break;
5100 case V4L2_CID_HFLIP:
5101 ret = ar0822_read_reg(ar0822->client, AR0822_FLIP_REG,
5102 AR0822_REG_VALUE_16BIT,
5103 &val);
5104 if (ctrl->val)
5105 val |= MIRROR_BIT_MASK;
5106 else
5107 val &= ~MIRROR_BIT_MASK;
5108 ret = ar0822_write_reg(ar0822->client, AR0822_FLIP_REG,
5109 AR0822_REG_VALUE_16BIT,
5110 val);
5111 if (ret == 0)
5112 ar0822->flip = val;
5113 break;
5114 case V4L2_CID_VFLIP:
5115 ret = ar0822_read_reg(ar0822->client, AR0822_FLIP_REG,
5116 AR0822_REG_VALUE_16BIT,
5117 &val);
5118 if (ctrl->val)
5119 val |= FLIP_BIT_MASK;
5120 else
5121 val &= ~FLIP_BIT_MASK;
5122 ret = ar0822_write_reg(ar0822->client, AR0822_FLIP_REG,
5123 AR0822_REG_VALUE_16BIT,
5124 val);
5125 if (ret == 0)
5126 ar0822->flip = val;
5127 break;
5128 default:
5129 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
5130 __func__, ctrl->id, ctrl->val);
5131 break;
5132 }
5133
5134
5135 ctrl_end:
5136 pm_runtime_put(&client->dev);
5137
5138 return ret;
5139 }
5140
5141 static const struct v4l2_ctrl_ops ar0822_ctrl_ops = {
5142 .s_ctrl = ar0822_set_ctrl,
5143 };
5144
ar0822_initialize_controls(struct ar0822 * ar0822)5145 static int ar0822_initialize_controls(struct ar0822 *ar0822)
5146 {
5147 const struct ar0822_mode *mode;
5148 struct v4l2_ctrl_handler *handler;
5149 s64 exposure_max, vblank_def;
5150 u32 h_blank;
5151 int ret;
5152 u64 dst_link_freq = 0;
5153 u64 dst_pixel_rate = 0;
5154
5155 handler = &ar0822->ctrl_handler;
5156 mode = ar0822->cur_mode;
5157 ret = v4l2_ctrl_handler_init(handler, 9);
5158 if (ret)
5159 return ret;
5160 handler->lock = &ar0822->mutex;
5161 ar0822->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
5162 V4L2_CID_LINK_FREQ,
5163 MIPI_FREQ_MAX_INDEX, 0, link_freq_menu_items);
5164
5165 dst_link_freq = mode->mipi_freq;
5166 dst_pixel_rate = mode->mipi_rate;
5167 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
5168 ar0822->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
5169 V4L2_CID_PIXEL_RATE,
5170 0, PIXEL_RATE_MAX,
5171 1, dst_pixel_rate);
5172 __v4l2_ctrl_s_ctrl(ar0822->link_freq,
5173 dst_link_freq);
5174
5175 h_blank = mode->hts_def - mode->width;
5176 ar0822->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
5177 h_blank, h_blank, 1, h_blank);
5178 if (ar0822->hblank)
5179 ar0822->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
5180
5181 vblank_def = mode->vts_def - mode->height;
5182 ar0822->vblank = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops,
5183 V4L2_CID_VBLANK, vblank_def,
5184 AR0822_VTS_MAX - mode->height,
5185 1, vblank_def);
5186
5187 exposure_max = mode->vts_def - 4;
5188 ar0822->exposure = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops,
5189 V4L2_CID_EXPOSURE, AR0822_EXPOSURE_MIN,
5190 exposure_max, AR0822_EXPOSURE_STEP,
5191 mode->exp_def);
5192
5193 ar0822->anal_gain = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops,
5194 V4L2_CID_ANALOGUE_GAIN, AR0822_GAIN_MIN,
5195 AR0822_GAIN_MAX, AR0822_GAIN_STEP,
5196 AR0822_GAIN_DEFAULT);
5197
5198 ar0822->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
5199 &ar0822_ctrl_ops, V4L2_CID_TEST_PATTERN,
5200 ARRAY_SIZE(ar0822_test_pattern_menu) - 1,
5201 0, 0, ar0822_test_pattern_menu);
5202
5203 ar0822->h_flip = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops,
5204 V4L2_CID_HFLIP, 0, 1, 1, 0);
5205
5206 ar0822->v_flip = v4l2_ctrl_new_std(handler, &ar0822_ctrl_ops,
5207 V4L2_CID_VFLIP, 0, 1, 1, 0);
5208 ar0822->flip = 0;
5209 if (handler->error) {
5210 ret = handler->error;
5211 dev_err(&ar0822->client->dev,
5212 "Failed to init controls(%d)\n", ret);
5213 goto err_free_handler;
5214 }
5215
5216 ar0822->subdev.ctrl_handler = handler;
5217 ar0822->has_init_exp = false;
5218 ar0822->long_hcg = false;
5219 ar0822->middle_hcg = false;
5220 ar0822->short_hcg = false;
5221
5222 return 0;
5223
5224 err_free_handler:
5225 v4l2_ctrl_handler_free(handler);
5226
5227 return ret;
5228 }
5229
ar0822_check_sensor_id(struct ar0822 * ar0822,struct i2c_client * client)5230 static int ar0822_check_sensor_id(struct ar0822 *ar0822,
5231 struct i2c_client *client)
5232 {
5233 struct device *dev = &ar0822->client->dev;
5234 u32 id = 0;
5235 int ret;
5236
5237 if (ar0822->is_thunderboot) {
5238 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
5239 return 0;
5240 }
5241
5242 ret = ar0822_read_reg(client, AR0822_REG_CHIP_ID,
5243 AR0822_REG_VALUE_16BIT, &id);
5244 if (id != CHIP_ID) {
5245 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
5246 return -ENODEV;
5247 }
5248
5249 dev_info(dev, "Detected ar0822%04x sensor\n", CHIP_ID);
5250
5251 return 0;
5252 }
5253
ar0822_configure_regulators(struct ar0822 * ar0822)5254 static int ar0822_configure_regulators(struct ar0822 *ar0822)
5255 {
5256 unsigned int i;
5257
5258 for (i = 0; i < AR0822_NUM_SUPPLIES; i++)
5259 ar0822->supplies[i].supply = ar0822_supply_names[i];
5260
5261 return devm_regulator_bulk_get(&ar0822->client->dev,
5262 AR0822_NUM_SUPPLIES,
5263 ar0822->supplies);
5264 }
5265
ar0822_probe(struct i2c_client * client,const struct i2c_device_id * id)5266 static int ar0822_probe(struct i2c_client *client,
5267 const struct i2c_device_id *id)
5268 {
5269 struct device *dev = &client->dev;
5270 struct device_node *node = dev->of_node;
5271 struct ar0822 *ar0822;
5272 struct v4l2_subdev *sd;
5273 char facing[2];
5274 int ret;
5275 u32 i, hdr_mode = 0;
5276
5277 dev_info(dev, "driver version: %02x.%02x.%02x",
5278 DRIVER_VERSION >> 16,
5279 (DRIVER_VERSION & 0xff00) >> 8,
5280 DRIVER_VERSION & 0x00ff);
5281
5282 ar0822 = devm_kzalloc(dev, sizeof(*ar0822), GFP_KERNEL);
5283 if (!ar0822)
5284 return -ENOMEM;
5285
5286 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
5287 &ar0822->module_index);
5288 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
5289 &ar0822->module_facing);
5290 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
5291 &ar0822->module_name);
5292 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
5293 &ar0822->len_name);
5294 if (ret) {
5295 dev_err(dev, "could not get module information!\n");
5296 return -EINVAL;
5297 }
5298
5299 ar0822->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
5300 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
5301 &hdr_mode);
5302 if (ret) {
5303 hdr_mode = NO_HDR;
5304 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
5305 }
5306 ar0822->cfg_num = ARRAY_SIZE(supported_modes);
5307 if(ar0822->cfg_num == 0){
5308 dev_err(dev, "no any supported mode providec, force exit probe!\n");
5309 return -EINVAL;
5310 }
5311 ar0822->cur_mode = &supported_modes[0];//initialize.
5312 for (i = 0; i < ar0822->cfg_num; i++) {
5313 if (hdr_mode == supported_modes[i].hdr_mode) {
5314 ar0822->cur_mode = &supported_modes[i];
5315 break;
5316 }
5317 }
5318 ar0822->client = client;
5319
5320 ar0822->xvclk = devm_clk_get(dev, "xvclk");
5321 if (IS_ERR(ar0822->xvclk)) {
5322 dev_err(dev, "Failed to get xvclk\n");
5323 return -EINVAL;
5324 }
5325
5326 ar0822->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
5327 if (IS_ERR(ar0822->reset_gpio))
5328 dev_warn(dev, "Failed to get reset-gpios\n");
5329
5330 ar0822->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
5331 if (IS_ERR(ar0822->pwdn_gpio))
5332 dev_warn(dev, "Failed to get pwdn-gpios\n");
5333
5334 ar0822->pinctrl = devm_pinctrl_get(dev);
5335 if (!IS_ERR(ar0822->pinctrl)) {
5336 ar0822->pins_default =
5337 pinctrl_lookup_state(ar0822->pinctrl,
5338 OF_CAMERA_PINCTRL_STATE_DEFAULT);
5339 if (IS_ERR(ar0822->pins_default))
5340 dev_err(dev, "could not get default pinstate\n");
5341
5342 ar0822->pins_sleep =
5343 pinctrl_lookup_state(ar0822->pinctrl,
5344 OF_CAMERA_PINCTRL_STATE_SLEEP);
5345 if (IS_ERR(ar0822->pins_sleep))
5346 dev_err(dev, "could not get sleep pinstate\n");
5347 } else {
5348 dev_err(dev, "no pinctrl\n");
5349 }
5350
5351 ret = ar0822_configure_regulators(ar0822);
5352 if (ret) {
5353 dev_err(dev, "Failed to get power regulators\n");
5354 return ret;
5355 }
5356
5357 mutex_init(&ar0822->mutex);
5358
5359 sd = &ar0822->subdev;
5360 v4l2_i2c_subdev_init(sd, client, &ar0822_subdev_ops);
5361 ret = ar0822_initialize_controls(ar0822);
5362 if (ret)
5363 goto err_destroy_mutex;
5364
5365 ret = __ar0822_power_on(ar0822);
5366 if (ret)
5367 goto err_free_handler;
5368
5369 ret = ar0822_check_sensor_id(ar0822, client);
5370 if (ret)
5371 goto err_power_off;
5372
5373 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
5374 sd->internal_ops = &ar0822_internal_ops;
5375 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
5376 #endif
5377 #if defined(CONFIG_MEDIA_CONTROLLER)
5378 ar0822->pad.flags = MEDIA_PAD_FL_SOURCE;
5379 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
5380 ret = media_entity_pads_init(&sd->entity, 1, &ar0822->pad);
5381 if (ret < 0)
5382 goto err_power_off;
5383 #endif
5384
5385 memset(facing, 0, sizeof(facing));
5386 if (strcmp(ar0822->module_facing, "back") == 0)
5387 facing[0] = 'b';
5388 else
5389 facing[0] = 'f';
5390
5391 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
5392 ar0822->module_index, facing,
5393 AR0822_NAME, dev_name(sd->dev));
5394 ret = v4l2_async_register_subdev_sensor_common(sd);
5395 if (ret) {
5396 dev_err(dev, "v4l2 async register subdev failed\n");
5397 goto err_clean_entity;
5398 }
5399
5400 pm_runtime_set_active(dev);
5401 pm_runtime_enable(dev);
5402 pm_runtime_idle(dev);
5403 #ifdef USED_SYS_DEBUG
5404 add_sysfs_interfaces(dev);
5405 #endif
5406 return 0;
5407
5408 err_clean_entity:
5409 #if defined(CONFIG_MEDIA_CONTROLLER)
5410 media_entity_cleanup(&sd->entity);
5411 #endif
5412 err_power_off:
5413 __ar0822_power_off(ar0822);
5414 err_free_handler:
5415 v4l2_ctrl_handler_free(&ar0822->ctrl_handler);
5416 err_destroy_mutex:
5417 mutex_destroy(&ar0822->mutex);
5418
5419 return ret;
5420 }
5421
ar0822_remove(struct i2c_client * client)5422 static int ar0822_remove(struct i2c_client *client)
5423 {
5424 struct v4l2_subdev *sd = i2c_get_clientdata(client);
5425 struct ar0822 *ar0822 = to_ar0822(sd);
5426
5427 v4l2_async_unregister_subdev(sd);
5428 #if defined(CONFIG_MEDIA_CONTROLLER)
5429 media_entity_cleanup(&sd->entity);
5430 #endif
5431 v4l2_ctrl_handler_free(&ar0822->ctrl_handler);
5432 mutex_destroy(&ar0822->mutex);
5433
5434 pm_runtime_disable(&client->dev);
5435 if (!pm_runtime_status_suspended(&client->dev))
5436 __ar0822_power_off(ar0822);
5437 pm_runtime_set_suspended(&client->dev);
5438
5439 return 0;
5440 }
5441
5442 #if IS_ENABLED(CONFIG_OF)
5443 static const struct of_device_id ar0822_of_match[] = {
5444 { .compatible = "onsemi,ar0822" },
5445 {},
5446 };
5447 MODULE_DEVICE_TABLE(of, ar0822_of_match);
5448 #endif
5449
5450 static const struct i2c_device_id ar0822_match_id[] = {
5451 { "onsemi,ar0822", 0 },
5452 { },
5453 };
5454
5455 static struct i2c_driver ar0822_i2c_driver = {
5456 .driver = {
5457 .name = AR0822_NAME,
5458 .pm = &ar0822_pm_ops,
5459 .of_match_table = of_match_ptr(ar0822_of_match),
5460 },
5461 .probe = &ar0822_probe,
5462 .remove = &ar0822_remove,
5463 .id_table = ar0822_match_id,
5464 };
5465
5466 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
5467 module_i2c_driver(ar0822_i2c_driver);
5468 #else
sensor_mod_init(void)5469 static int __init sensor_mod_init(void)
5470 {
5471 return i2c_add_driver(&ar0822_i2c_driver);
5472 }
5473
sensor_mod_exit(void)5474 static void __exit sensor_mod_exit(void)
5475 {
5476 i2c_del_driver(&ar0822_i2c_driver);
5477 }
5478
5479 device_initcall_sync(sensor_mod_init);
5480 module_exit(sensor_mod_exit);
5481 #endif
5482
5483 MODULE_DESCRIPTION("Onsemi ar0822 sensor driver");
5484 MODULE_LICENSE("GPL");
5485