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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/kernel/
H A Dvecemu.c25 0x800000,
26 0x8b95c2,
27 0x9837f0,
28 0xa5fed7,
29 0xb504f3,
30 0xc5672a,
31 0xd744fd,
32 0xeac0c7
45 exp = ((s >> 23) & 0xff) - 127; in eexp2()
48 if (exp == 128 && (s & 0x7fffff) != 0) in eexp2()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darmada-398-db.dts23 reg = <0x00000000 0x80000000>; /* 2 GB */
27 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
28 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
32 pinctrl-0 = <&i2c0_pins>;
39 pinctrl-0 = <&uart0_pins>;
45 pinctrl-0 = <&uart1_pins>;
62 pcie@1,0 {
66 pcie@2,0 {
70 pcie@3,0 {
79 pinctrl-0 = <&spi1_pins>;
[all …]
H A Darmada-390-db.dts24 reg = <0x00000000 0x80000000>; /* 2 GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
38 reg = <0x50>;
62 pcie@1,0 {
67 pcie@2,0 {
72 pcie@3,0 {
81 pinctrl-0 = <&spi1_pins>;
89 reg = <0>; /* Chip select 0 */
97 partition@0 {
[all …]
H A Darmada-388-db.dts25 reg = <0x00000000 0x10000000>; /* 256 MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
33 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
68 bm,pool-long = <0>;
73 phy0: ethernet-phy@0 {
74 reg = <0>;
121 pcie@1,0 {
[all …]
H A Darmada-375-db.dts24 memory@0 {
26 reg = <0x00000000 0x40000000>; /* 1 GB */
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
31 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
32 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
46 /* Port 0, Lane 0 */
51 /* Port 1, Lane 0 */
57 pinctrl-0 = <&spi0_pins>;
67 spi-flash@0 {
[all …]
H A Darmada-370-rd.dts11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
36 reg = <0x00000000 0x20000000>; /* 512 MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
59 pinctrl-0 = <&ge1_rgmii_pins>;
70 pinctrl-0 = <&sdio_pins1>;
[all …]
H A Darmada-370-db.dts13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
17 * left internal registers mapped at 0xd0000000. If you are in this
33 memory@0 {
35 reg = <0x00000000 0x40000000>; /* 1 GB */
39 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
40 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
41 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
53 pinctrl-0 = <&ge0_rgmii_pins>;
60 pinctrl-0 = <&ge1_rgmii_pins>;
[all …]
H A Darmada-xp-db.dts14 * internal registers to 0xf1000000 (instead of the default
15 * 0xd0000000). The 0xf1000000 is the default used by the recent,
18 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
36 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
43 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
44 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
[all …]
/OK3568_Linux_fs/u-boot/post/lib_powerpc/
H A Dthreex.c41 0x1234,
42 0x5678,
43 0x1234 | 0x5678
47 0x1234,
48 0x5678,
49 0x1234 | ~0x5678
53 0x1234,
54 0x5678,
55 0x1234 ^ 0x5678
59 0x1234,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/OK3568_Linux_fs/u-boot/drivers/dma/
H A Dfsl_dma.c18 #define FSL_DMA_MAX_SIZE (0x3ffffff)
65 volatile fsl_dma_t *dma = &dma_base->dma[0]; in dma_check()
77 if (status != 0) in dma_check()
85 volatile fsl_dma_t *dma = &dma_base->dma[0]; in dma_init()
89 out_dma32(&dma->sr, 0xffffffff); /* clear any errors */ in dma_init()
95 volatile fsl_dma_t *dma = &dma_base->dma[0]; in dmacpy()
101 out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF)); in dmacpy()
102 out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF)); in dmacpy()
129 return 0; in dmacpy()
141 uint *p = 0; in dma_meminit()
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Diconnect.h43 #define CONFIG_ENV_SECT_SIZE 0x20000
45 #define CONFIG_ENV_SIZE 0x20000
46 #define CONFIG_ENV_OFFSET 0x80000
55 "ubifsload 0x800000 ${kernel}; " \
56 "bootm 0x800000"
60 "0x80000@0x0(uboot)," \
61 "0x20000@0x80000(uboot_env)," \
62 "-@0xa0000(rootfs)\0"
65 "console=console=ttyS0,115200\0" \
66 "mtdids=nand0=orion_nand\0" \
[all …]
H A Ddockstar.h33 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
39 #define CONFIG_ENV_SIZE 0x20000 /* 128k */
40 #define CONFIG_ENV_ADDR 0x80000
41 #define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
50 "ubifsload 0x800000 ${kernel}; " \
51 "ubifsload 0x1100000 ${initrd}; " \
52 "bootm 0x800000 0x1100000"
54 #define CONFIG_MTDPARTS "mtdparts=orion_nand:1m(uboot),-(root)\0"
57 "console=console=ttyS0,115200\0" \
58 "mtdids=nand0=orion_nand\0" \
[all …]
H A Dnsa310s.h35 #define CONFIG_ENV_SECT_SIZE 0x20000
37 #define CONFIG_ENV_SIZE 0x20000
38 #define CONFIG_ENV_OFFSET 0xe0000
45 "ubifsload 0x800000 ${kernel}; " \
46 "ubifsload 0x700000 ${fdt}; " \
48 "fdt addr 0x700000; fdt resize; fdt chosen; " \
49 "bootz 0x800000 - 0x700000"
53 "0xe0000@0x0(uboot)," \
54 "0x20000@0xe0000(uboot_env)," \
55 "0x100000@0x100000(second_stage_uboot)," \
[all …]
H A Dib62x0.h41 #define CONFIG_ENV_SECT_SIZE 0x20000
43 #define CONFIG_ENV_SIZE 0x20000
44 #define CONFIG_ENV_OFFSET 0xe0000
53 "ubifsload 0x800000 ${kernel}; " \
54 "ubifsload 0x700000 ${fdt}; " \
56 "fdt addr 0x700000; fdt resize; fdt chosen; " \
57 "bootz 0x800000 - 0x700000"
61 "0xe0000@0x0(uboot)," \
62 "0x20000@0xe0000(uboot_env)," \
63 "-@0x100000(root)\0"
[all …]
H A Dguruplug.h34 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
40 #define CONFIG_ENV_SIZE 0x20000 /* 128k */
41 #define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */
50 "ubifsload 0x800000 ${kernel}; " \
51 "ubifsload 0x700000 ${fdt}; " \
53 "fdt addr 0x700000; fdt resize; fdt chosen; " \
54 "bootz 0x800000 - 0x700000"
59 "-@1M(root)\0"
62 "console=console=ttyS0,115200\0" \
63 "mtdids=nand0=orion_nand\0" \
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-375-db.dts70 reg = <0x00000000 0x40000000>; /* 1 GB */
74 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
75 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
76 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
77 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
81 pinctrl-0 = <&spi0_pins>;
91 spi-flash@0 {
96 reg = <0>; /* Chip select 0 */
104 pinctrl-0 = <&i2c0_pins>;
111 pinctrl-0 = <&i2c1_pins>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt24 0 <physical address of mapping> <size>
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
53 ALE[0] to the cycle that the first read data is sampled
63 DEV_OEn assertion. If set to 0 (default),
72 de-assertion of DEV_CSn. If set to 0 (default),
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
90 A[2:0] and Data are kept valid as long as DEV_WEn
97 DEV_A[2:0] and Data are kept valid (do not toggle) for
105 0: False
115 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
[all …]
/OK3568_Linux_fs/u-boot/include/environment/ti/
H A Ddfu.h14 "boot part 0 1;" \
15 "rootfs part 0 2;" \
16 "MLO fat 0 1;" \
17 "MLO.raw raw 0x100 0x100;" \
18 "u-boot.img.raw raw 0x300 0x1000;" \
19 "u-env.raw raw 0x1300 0x200;" \
20 "spl-os-args.raw raw 0x1500 0x200;" \
21 "spl-os-image.raw raw 0x1700 0x6900;" \
22 "spl-os-args fat 0 1;" \
23 "spl-os-image fat 0 1;" \
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dmpc8548cds_32b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
23 0x1 0x0 0x0 0xf8004000 0x00001000>;
28 ranges = <0 0x0 0xe0000000 0x100000>;
32 reg = <0 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
39 reg = <0 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
[all …]
H A Dmpc8548cds_36b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0xf 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0xf 0xff000000 0x01000000
23 0x1 0x0 0xf 0xf8004000 0x00001000>;
28 ranges = <0 0xf 0xe0000000 0x100000>;
32 reg = <0xf 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
39 reg = <0xf 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
[all …]

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