1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Marvell Armada 375 evaluation board 4*4882a593Smuzhiyun * (DB-88F6720) 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2014 Marvell 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com> 9*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/dts-v1/; 13*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 14*4882a593Smuzhiyun#include "armada-375.dtsi" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun model = "Marvell Armada 375 Development Board"; 18*4882a593Smuzhiyun compatible = "marvell,a375-db", "marvell,armada375"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun chosen { 21*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun memory@0 { 25*4882a593Smuzhiyun device_type = "memory"; 26*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; /* 1 GB */ 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun soc { 30*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 31*4882a593Smuzhiyun MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 32*4882a593Smuzhiyun MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 33*4882a593Smuzhiyun MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun&pciec { 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun/* 42*4882a593Smuzhiyun * The two PCIe units are accessible through 43*4882a593Smuzhiyun * standard PCIe slots on the board. 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun&pcie0 { 46*4882a593Smuzhiyun /* Port 0, Lane 0 */ 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&pcie1 { 51*4882a593Smuzhiyun /* Port 1, Lane 0 */ 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&spi0 { 57*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins>; 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * SPI conflicts with NAND, so we disable it here, and 62*4882a593Smuzhiyun * select NAND as the enabled device by default. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun status = "disabled"; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun spi-flash@0 { 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <1>; 70*4882a593Smuzhiyun compatible = "n25q128a13", "jedec,spi-nor"; 71*4882a593Smuzhiyun reg = <0>; /* Chip select 0 */ 72*4882a593Smuzhiyun spi-max-frequency = <108000000>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun&i2c0 { 77*4882a593Smuzhiyun status = "okay"; 78*4882a593Smuzhiyun clock-frequency = <100000>; 79*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 80*4882a593Smuzhiyun pinctrl-names = "default"; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&i2c1 { 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun clock-frequency = <100000>; 86*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 87*4882a593Smuzhiyun pinctrl-names = "default"; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&uart0 { 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun&pinctrl { 95*4882a593Smuzhiyun sdio_st_pins: sdio-st-pins { 96*4882a593Smuzhiyun marvell,pins = "mpp44", "mpp45"; 97*4882a593Smuzhiyun marvell,function = "gpio"; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&sata { 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun nr-ports = <2>; 104*4882a593Smuzhiyun}; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun&nand_controller { 107*4882a593Smuzhiyun status = "okay"; 108*4882a593Smuzhiyun pinctrl-0 = <&nand_pins>; 109*4882a593Smuzhiyun pinctrl-names = "default"; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun nand@0 { 112*4882a593Smuzhiyun reg = <0>; 113*4882a593Smuzhiyun label = "pxa3xx_nand-0"; 114*4882a593Smuzhiyun nand-rb = <0>; 115*4882a593Smuzhiyun marvell,nand-keep-config; 116*4882a593Smuzhiyun nand-on-flash-bbt; 117*4882a593Smuzhiyun nand-ecc-strength = <4>; 118*4882a593Smuzhiyun nand-ecc-step-size = <512>; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun partitions { 121*4882a593Smuzhiyun compatible = "fixed-partitions"; 122*4882a593Smuzhiyun #address-cells = <1>; 123*4882a593Smuzhiyun #size-cells = <1>; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun partition@0 { 126*4882a593Smuzhiyun label = "U-Boot"; 127*4882a593Smuzhiyun reg = <0 0x800000>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun partition@800000 { 130*4882a593Smuzhiyun label = "Linux"; 131*4882a593Smuzhiyun reg = <0x800000 0x800000>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun partition@1000000 { 134*4882a593Smuzhiyun label = "Filesystem"; 135*4882a593Smuzhiyun reg = <0x1000000 0x3f000000>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun&usb1 { 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&usb2 { 146*4882a593Smuzhiyun status = "okay"; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&sdio { 150*4882a593Smuzhiyun pinctrl-0 = <&sdio_pins &sdio_st_pins>; 151*4882a593Smuzhiyun pinctrl-names = "default"; 152*4882a593Smuzhiyun status = "okay"; 153*4882a593Smuzhiyun cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 154*4882a593Smuzhiyun wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&mdio { 158*4882a593Smuzhiyun phy0: ethernet-phy@0 { 159*4882a593Smuzhiyun reg = <0>; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun phy3: ethernet-phy@3 { 163*4882a593Smuzhiyun reg = <3>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyunðernet { 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun 172*4882a593Smuzhiyunð0 { 173*4882a593Smuzhiyun status = "okay"; 174*4882a593Smuzhiyun phy = <&phy0>; 175*4882a593Smuzhiyun phy-mode = "rgmii-id"; 176*4882a593Smuzhiyun}; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyunð1 { 179*4882a593Smuzhiyun status = "okay"; 180*4882a593Smuzhiyun phy = <&phy3>; 181*4882a593Smuzhiyun phy-mode = "gmii"; 182*4882a593Smuzhiyun}; 183