xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunDevice tree bindings for MVEBU Device Bus controllers
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe Device Bus controller available in some Marvell's SoC allows to control
4*4882a593Smuzhiyundifferent types of standard memory and I/O devices such as NOR, NAND, and FPGA.
5*4882a593SmuzhiyunThe actual devices are instantiated from the child nodes of a Device Bus node.
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunRequired properties:
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun - compatible:          Armada 370/XP SoC are supported using the
10*4882a593Smuzhiyun                        "marvell,mvebu-devbus" compatible string.
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun                        Orion5x SoC are supported using the
13*4882a593Smuzhiyun                        "marvell,orion-devbus" compatible string.
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun - reg:                 A resource specifier for the register space.
16*4882a593Smuzhiyun                        This is the base address of a chip select within
17*4882a593Smuzhiyun			the controller's register space.
18*4882a593Smuzhiyun                        (see the example below)
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun - #address-cells:      Must be set to 1
21*4882a593Smuzhiyun - #size-cells:         Must be set to 1
22*4882a593Smuzhiyun - ranges:              Must be set up to reflect the memory layout with four
23*4882a593Smuzhiyun                        integer values for each chip-select line in use:
24*4882a593Smuzhiyun                        0 <physical address of mapping> <size>
25*4882a593Smuzhiyun
26*4882a593SmuzhiyunOptional properties:
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun - devbus,keep-config   This property can optionally be used to keep
29*4882a593Smuzhiyun                        using the timing parameters set by the
30*4882a593Smuzhiyun                        bootloader. It makes all the timing properties
31*4882a593Smuzhiyun                        described below unused.
32*4882a593Smuzhiyun
33*4882a593SmuzhiyunTiming properties for child nodes:
34*4882a593Smuzhiyun
35*4882a593SmuzhiyunRead parameters:
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun - devbus,turn-off-ps:  Defines the time during which the controller does not
38*4882a593Smuzhiyun                        drive the AD bus after the completion of a device read.
39*4882a593Smuzhiyun                        This prevents contentions on the Device Bus after a read
40*4882a593Smuzhiyun                        cycle from a slow device.
41*4882a593Smuzhiyun                        Mandatory, except if devbus,keep-config is used.
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun - devbus,bus-width:    Defines the bus width, in bits (e.g. <16>).
44*4882a593Smuzhiyun                        Mandatory, except if devbus,keep-config is used.
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
47*4882a593Smuzhiyun                        to read data sample. This parameter is useful for
48*4882a593Smuzhiyun                        synchronous pipelined devices, where the address
49*4882a593Smuzhiyun                        precedes the read data by one or two cycles.
50*4882a593Smuzhiyun                        Mandatory, except if devbus,keep-config is used.
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun - devbus,acc-first-ps: Defines the time delay from the negation of
53*4882a593Smuzhiyun                        ALE[0] to the cycle that the first read data is sampled
54*4882a593Smuzhiyun                        by the controller.
55*4882a593Smuzhiyun                        Mandatory, except if devbus,keep-config is used.
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun - devbus,acc-next-ps:  Defines the time delay between the cycle that
58*4882a593Smuzhiyun                        samples data N and the cycle that samples data N+1
59*4882a593Smuzhiyun                        (in burst accesses).
60*4882a593Smuzhiyun                        Mandatory, except if devbus,keep-config is used.
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
63*4882a593Smuzhiyun			DEV_OEn assertion. If set to 0 (default),
64*4882a593Smuzhiyun                        DEV_OEn and DEV_CSn are asserted at the same cycle.
65*4882a593Smuzhiyun                        This parameter has no affect on <acc-first-ps> parameter
66*4882a593Smuzhiyun                        (no affect on first data sample). Set <rd-setup-ps>
67*4882a593Smuzhiyun                        to a value smaller than <acc-first-ps>.
68*4882a593Smuzhiyun                        Mandatory for "marvell,mvebu-devbus" compatible string,
69*4882a593Smuzhiyun                        except if devbus,keep-config is used.
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun - devbus,rd-hold-ps:   Defines the time between the last data sample to the
72*4882a593Smuzhiyun			de-assertion of DEV_CSn. If set to 0 (default),
73*4882a593Smuzhiyun			DEV_OEn and DEV_CSn are de-asserted at the same cycle
74*4882a593Smuzhiyun			(the cycle of the last data sample).
75*4882a593Smuzhiyun                        This parameter has no affect on DEV_OEn de-assertion.
76*4882a593Smuzhiyun                        DEV_OEn is always de-asserted the next cycle after
77*4882a593Smuzhiyun                        last data sampled. Also this parameter has no
78*4882a593Smuzhiyun                        affect on <turn-off-ps> parameter.
79*4882a593Smuzhiyun                        Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
80*4882a593Smuzhiyun                        Mandatory for "marvell,mvebu-devbus" compatible string,
81*4882a593Smuzhiyun                        except if devbus,keep-config is used.
82*4882a593Smuzhiyun
83*4882a593SmuzhiyunWrite parameters:
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun - devbus,ale-wr-ps:    Defines the time delay from the ALE[0] negation cycle
86*4882a593Smuzhiyun			to the DEV_WEn assertion.
87*4882a593Smuzhiyun                        Mandatory.
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun - devbus,wr-low-ps:    Defines the time during which DEV_WEn is active.
90*4882a593Smuzhiyun                        A[2:0] and Data are kept valid as long as DEV_WEn
91*4882a593Smuzhiyun                        is active. This parameter defines the setup time of
92*4882a593Smuzhiyun                        address and data to DEV_WEn rise.
93*4882a593Smuzhiyun                        Mandatory.
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun - devbus,wr-high-ps:   Defines the time during which DEV_WEn is kept
96*4882a593Smuzhiyun                        inactive (high) between data beats of a burst write.
97*4882a593Smuzhiyun                        DEV_A[2:0] and Data are kept valid (do not toggle) for
98*4882a593Smuzhiyun                        <wr-high-ps> - <tick> ps.
99*4882a593Smuzhiyun			This parameter defines the hold time of address and
100*4882a593Smuzhiyun			data after DEV_WEn rise.
101*4882a593Smuzhiyun                        Mandatory.
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun - devbus,sync-enable: Synchronous device enable.
104*4882a593Smuzhiyun                       1: True
105*4882a593Smuzhiyun                       0: False
106*4882a593Smuzhiyun                       Mandatory for "marvell,mvebu-devbus" compatible string,
107*4882a593Smuzhiyun                       except if devbus,keep-config is used.
108*4882a593Smuzhiyun
109*4882a593SmuzhiyunAn example for an Armada XP GP board, with a 16 MiB NOR device as child
110*4882a593Smuzhiyunis showed below. Note that the Device Bus driver is in charge of allocating
111*4882a593Smuzhiyunthe mbus address decoding window for each of its child devices.
112*4882a593SmuzhiyunThe window is created using the chip select specified in the child
113*4882a593Smuzhiyundevice node together with the base address and size specified in the ranges
114*4882a593Smuzhiyunproperty. For instance, in the example below the allocated decoding window
115*4882a593Smuzhiyunwill start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
116*4882a593Smuzhiyunfor chip select 0 (a.k.a DEV_BOOTCS).
117*4882a593Smuzhiyun
118*4882a593SmuzhiyunThis address window handling is done in this mvebu-devbus only as a temporary
119*4882a593Smuzhiyunsolution. It will be removed when the support for mbus device tree binding is
120*4882a593Smuzhiyunadded.
121*4882a593Smuzhiyun
122*4882a593SmuzhiyunThe reg property implicitly specifies the chip select as this:
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun  0x10400: DEV_BOOTCS
125*4882a593Smuzhiyun  0x10408: DEV_CS0
126*4882a593Smuzhiyun  0x10410: DEV_CS1
127*4882a593Smuzhiyun  0x10418: DEV_CS2
128*4882a593Smuzhiyun  0x10420: DEV_CS3
129*4882a593Smuzhiyun
130*4882a593SmuzhiyunExample:
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun	devbus-bootcs@d0010400 {
133*4882a593Smuzhiyun		ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
134*4882a593Smuzhiyun		#address-cells = <1>;
135*4882a593Smuzhiyun		#size-cells = <1>;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		/* Device Bus parameters are required */
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun		/* Read parameters */
140*4882a593Smuzhiyun		devbus,bus-width    = <8>;
141*4882a593Smuzhiyun		devbus,turn-off-ps  = <60000>;
142*4882a593Smuzhiyun		devbus,badr-skew-ps = <0>;
143*4882a593Smuzhiyun		devbus,acc-first-ps = <124000>;
144*4882a593Smuzhiyun		devbus,acc-next-ps  = <248000>;
145*4882a593Smuzhiyun		devbus,rd-setup-ps  = <0>;
146*4882a593Smuzhiyun		devbus,rd-hold-ps   = <0>;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun		/* Write parameters */
149*4882a593Smuzhiyun		devbus,sync-enable = <0>;
150*4882a593Smuzhiyun		devbus,wr-high-ps  = <60000>;
151*4882a593Smuzhiyun		devbus,wr-low-ps   = <60000>;
152*4882a593Smuzhiyun		devbus,ale-wr-ps   = <60000>;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun		flash@0 {
155*4882a593Smuzhiyun			compatible = "cfi-flash";
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun			/* 16 MiB */
158*4882a593Smuzhiyun			reg = <0 0x1000000>;
159*4882a593Smuzhiyun			bank-width = <2>;
160*4882a593Smuzhiyun			#address-cells = <1>;
161*4882a593Smuzhiyun			#size-cells = <1>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			/*
164*4882a593Smuzhiyun			 * We split the 16 MiB in two partitions,
165*4882a593Smuzhiyun			 * just as an example.
166*4882a593Smuzhiyun			 */
167*4882a593Smuzhiyun			partition@0 {
168*4882a593Smuzhiyun				label = "First";
169*4882a593Smuzhiyun				reg = <0 0x800000>;
170*4882a593Smuzhiyun			};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun			partition@800000 {
173*4882a593Smuzhiyun				label = "Second";
174*4882a593Smuzhiyun				reg = <0x800000 0x800000>;
175*4882a593Smuzhiyun			};
176*4882a593Smuzhiyun		};
177*4882a593Smuzhiyun	};
178