xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/armada-375-db.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Device Tree file for Marvell Armada 375 evaluation board
3*4882a593Smuzhiyun * (DB-88F6720)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun *  Copyright (C) 2014 Marvell
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com>
8*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
11*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
12*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
13*4882a593Smuzhiyun * whole.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
16*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License as
17*4882a593Smuzhiyun *     published by the Free Software Foundation; either version 2 of the
18*4882a593Smuzhiyun *     License, or (at your option) any later version.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful
21*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23*4882a593Smuzhiyun *     GNU General Public License for more details.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Or, alternatively
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
28*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
29*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
30*4882a593Smuzhiyun *     restriction, including without limitation the rights to use
31*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
32*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
33*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
34*4882a593Smuzhiyun *     conditions:
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
37*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun/dts-v1/;
50*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
51*4882a593Smuzhiyun#include "armada-375.dtsi"
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun/ {
54*4882a593Smuzhiyun	model = "Marvell Armada 375 Development Board";
55*4882a593Smuzhiyun	compatible = "marvell,a375-db", "marvell,armada375";
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	chosen {
58*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	aliases {
62*4882a593Smuzhiyun		/* So that mvebu u-boot can update the MAC addresses */
63*4882a593Smuzhiyun		ethernet0 = &eth0;
64*4882a593Smuzhiyun		ethernet1 = &eth1;
65*4882a593Smuzhiyun		spi0 = &spi0;
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	memory {
69*4882a593Smuzhiyun		device_type = "memory";
70*4882a593Smuzhiyun		reg = <0x00000000 0x40000000>; /* 1 GB */
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	soc {
74*4882a593Smuzhiyun		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
75*4882a593Smuzhiyun			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
76*4882a593Smuzhiyun			  MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
77*4882a593Smuzhiyun			  MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun		internal-regs {
80*4882a593Smuzhiyun			spi@10600 {
81*4882a593Smuzhiyun				pinctrl-0 = <&spi0_pins>;
82*4882a593Smuzhiyun				pinctrl-names = "default";
83*4882a593Smuzhiyun				/*
84*4882a593Smuzhiyun				 * SPI conflicts with NAND, so we disable it
85*4882a593Smuzhiyun				 * here, and select NAND as the enabled device
86*4882a593Smuzhiyun				 * by default.
87*4882a593Smuzhiyun				 */
88*4882a593Smuzhiyun				status = "okay";
89*4882a593Smuzhiyun				u-boot,dm-pre-reloc;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun				spi-flash@0 {
92*4882a593Smuzhiyun					u-boot,dm-pre-reloc;
93*4882a593Smuzhiyun					#address-cells = <1>;
94*4882a593Smuzhiyun					#size-cells = <1>;
95*4882a593Smuzhiyun					compatible = "n25q128a13", "jedec,spi-nor";
96*4882a593Smuzhiyun					reg = <0>; /* Chip select 0 */
97*4882a593Smuzhiyun					spi-max-frequency = <108000000>;
98*4882a593Smuzhiyun				};
99*4882a593Smuzhiyun			};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun			i2c@11000 {
102*4882a593Smuzhiyun				status = "okay";
103*4882a593Smuzhiyun				clock-frequency = <100000>;
104*4882a593Smuzhiyun				pinctrl-0 = <&i2c0_pins>;
105*4882a593Smuzhiyun				pinctrl-names = "default";
106*4882a593Smuzhiyun			};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun			i2c@11100 {
109*4882a593Smuzhiyun				status = "okay";
110*4882a593Smuzhiyun				clock-frequency = <100000>;
111*4882a593Smuzhiyun				pinctrl-0 = <&i2c1_pins>;
112*4882a593Smuzhiyun				pinctrl-names = "default";
113*4882a593Smuzhiyun			};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun			serial@12000 {
116*4882a593Smuzhiyun				u-boot,dm-pre-reloc;
117*4882a593Smuzhiyun				status = "okay";
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun			pinctrl {
121*4882a593Smuzhiyun				sdio_st_pins: sdio-st-pins {
122*4882a593Smuzhiyun					marvell,pins = "mpp44", "mpp45";
123*4882a593Smuzhiyun					marvell,function = "gpio";
124*4882a593Smuzhiyun				};
125*4882a593Smuzhiyun			};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun			sata@a0000 {
128*4882a593Smuzhiyun				status = "okay";
129*4882a593Smuzhiyun				nr-ports = <2>;
130*4882a593Smuzhiyun			};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun			nand: nand@d0000 {
133*4882a593Smuzhiyun				pinctrl-0 = <&nand_pins>;
134*4882a593Smuzhiyun				pinctrl-names = "default";
135*4882a593Smuzhiyun				status = "okay";
136*4882a593Smuzhiyun				num-cs = <1>;
137*4882a593Smuzhiyun				marvell,nand-keep-config;
138*4882a593Smuzhiyun				marvell,nand-enable-arbiter;
139*4882a593Smuzhiyun				nand-on-flash-bbt;
140*4882a593Smuzhiyun				nand-ecc-strength = <4>;
141*4882a593Smuzhiyun				nand-ecc-step-size = <512>;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun				partition@0 {
144*4882a593Smuzhiyun					label = "U-Boot";
145*4882a593Smuzhiyun					reg = <0 0x800000>;
146*4882a593Smuzhiyun				};
147*4882a593Smuzhiyun				partition@800000 {
148*4882a593Smuzhiyun					label = "Linux";
149*4882a593Smuzhiyun					reg = <0x800000 0x800000>;
150*4882a593Smuzhiyun				};
151*4882a593Smuzhiyun				partition@1000000 {
152*4882a593Smuzhiyun					label = "Filesystem";
153*4882a593Smuzhiyun					reg = <0x1000000 0x3f000000>;
154*4882a593Smuzhiyun				};
155*4882a593Smuzhiyun			};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun			usb@54000 {
158*4882a593Smuzhiyun				status = "okay";
159*4882a593Smuzhiyun			};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun			usb3@58000 {
162*4882a593Smuzhiyun				status = "okay";
163*4882a593Smuzhiyun			};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun			mvsdio@d4000 {
166*4882a593Smuzhiyun				pinctrl-0 = <&sdio_pins &sdio_st_pins>;
167*4882a593Smuzhiyun				pinctrl-names = "default";
168*4882a593Smuzhiyun				status = "okay";
169*4882a593Smuzhiyun				cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
170*4882a593Smuzhiyun				wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
171*4882a593Smuzhiyun			};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun			mdio {
174*4882a593Smuzhiyun				phy0: ethernet-phy@0 {
175*4882a593Smuzhiyun					reg = <0>;
176*4882a593Smuzhiyun				};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun				phy3: ethernet-phy@3 {
179*4882a593Smuzhiyun					reg = <3>;
180*4882a593Smuzhiyun				};
181*4882a593Smuzhiyun			};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun			ethernet@f0000 {
184*4882a593Smuzhiyun				status = "okay";
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun				eth0@c4000 {
187*4882a593Smuzhiyun					status = "okay";
188*4882a593Smuzhiyun					phy = <&phy0>;
189*4882a593Smuzhiyun					phy-mode = "rgmii-id";
190*4882a593Smuzhiyun				};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun				eth1@c5000 {
193*4882a593Smuzhiyun					status = "okay";
194*4882a593Smuzhiyun					phy = <&phy3>;
195*4882a593Smuzhiyun					phy-mode = "gmii";
196*4882a593Smuzhiyun				};
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun		};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun		pcie-controller {
201*4882a593Smuzhiyun			status = "okay";
202*4882a593Smuzhiyun			/*
203*4882a593Smuzhiyun			 * The two PCIe units are accessible through
204*4882a593Smuzhiyun			 * standard PCIe slots on the board.
205*4882a593Smuzhiyun			 */
206*4882a593Smuzhiyun			pcie@1,0 {
207*4882a593Smuzhiyun				/* Port 0, Lane 0 */
208*4882a593Smuzhiyun				status = "okay";
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun			pcie@2,0 {
211*4882a593Smuzhiyun				/* Port 1, Lane 0 */
212*4882a593Smuzhiyun				status = "okay";
213*4882a593Smuzhiyun			};
214*4882a593Smuzhiyun		};
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun};
217