1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MPC8548 CDS Device Tree Source (36-bit address map) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "mpc8548si-pre.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "MPC8548CDS"; 12*4882a593Smuzhiyun compatible = "MPC8548CDS", "MPC85xxCDS"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun reg = <0 0 0x0 0x8000000>; // 128M at 0x0 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun board_lbc: lbc: localbus@fe0005000 { 20*4882a593Smuzhiyun reg = <0xf 0xe0005000 0 0x1000>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun ranges = <0x0 0x0 0xf 0xff000000 0x01000000 23*4882a593Smuzhiyun 0x1 0x0 0xf 0xf8004000 0x00001000>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun board_soc: soc: soc8548@fe0000000 { 28*4882a593Smuzhiyun ranges = <0 0xf 0xe0000000 0x100000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun board_pci0: pci0: pci@fe0008000 { 32*4882a593Smuzhiyun reg = <0xf 0xe0008000 0 0x1000>; 33*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000 34*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>; 35*4882a593Smuzhiyun clock-frequency = <66666666>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun pci1: pci@fe0009000 { 39*4882a593Smuzhiyun reg = <0xf 0xe0009000 0 0x1000>; 40*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 41*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>; 42*4882a593Smuzhiyun clock-frequency = <66666666>; 43*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 44*4882a593Smuzhiyun interrupt-map = < 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* IDSEL 0x15 */ 47*4882a593Smuzhiyun 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0 48*4882a593Smuzhiyun 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 49*4882a593Smuzhiyun 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 50*4882a593Smuzhiyun 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun pci2: pcie@fe000a000 { 54*4882a593Smuzhiyun reg = <0xf 0xe000a000 0 0x1000>; 55*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 56*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x100000>; 57*4882a593Smuzhiyun pcie@0 { 58*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xa0000000 59*4882a593Smuzhiyun 0x2000000 0x0 0xa0000000 60*4882a593Smuzhiyun 0x0 0x20000000 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun 0x1000000 0x0 0x0 63*4882a593Smuzhiyun 0x1000000 0x0 0x0 64*4882a593Smuzhiyun 0x0 0x100000>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun rio: rapidio@fe00c0000 { 69*4882a593Smuzhiyun reg = <0xf 0xe00c0000 0x0 0x20000>; 70*4882a593Smuzhiyun port1 { 71*4882a593Smuzhiyun ranges = <0x0 0x0 0xc 0x40000000 0x0 0x20000000>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun/* 77*4882a593Smuzhiyun * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings 78*4882a593Smuzhiyun * for interrupt-map & interrupt-map-mask. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun/include/ "mpc8548si-post.dtsi" 82*4882a593Smuzhiyun/include/ "mpc8548cds.dtsi" 83