| /OK3568_Linux_fs/u-boot/doc/ |
| H A D | README.sha1 | 29 a) cp the new Image on a position in RAM (here 0x300000) 30 (for this example we use the Image from Flash, stored at 0xfffa0000 and 31 0x60000 Bytes long) 35 b) Initialize the SHA1 sum in the Image with 0x00 38 for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20 39 = 0xffffffe0 40 for the example in RAM: 0x300000 + 0x60000 + -0x20 41 = 0x35ffe0 45 "mw.b 35ffe0 0 14"
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| /OK3568_Linux_fs/buildroot/board/freescale/common/imx/ |
| H A D | imx8-bootloader-prepare.sh | 13 …BL31=${BINARIES_DIR}/bl31.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin ATF_LOAD_ADDR=0x00910000 ${HOS… 14 ${HOST_DIR}/bin/mkimage -E -p 0x3000 -f ${BINARIES_DIR}/u-boot.its ${BINARIES_DIR}/u-boot.itb 17 …loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x7E1000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x402… 20 …BL31=${BINARIES_DIR}/bl31.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin ATF_LOAD_ADDR=0x00920000 ${HOS… 21 ${HOST_DIR}/bin/mkimage -E -p 0x3000 -f ${BINARIES_DIR}/u-boot.its ${BINARIES_DIR}/u-boot.itb 24 …loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x7E1000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x402… 27 …BL31=${BINARIES_DIR}/bl31.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin ATF_LOAD_ADDR=0x00960000 ${HOS… 28 ${HOST_DIR}/bin/mkimage -E -p 0x3000 -f ${BINARIES_DIR}/u-boot.its ${BINARIES_DIR}/u-boot.itb 31 …loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x912000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x402… 34 …BL31=${BINARIES_DIR}/bl31.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin ATF_LOAD_ADDR=0x00970000 ${HOS… [all …]
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| /OK3568_Linux_fs/u-boot/doc/SPI/ |
| H A D | README.ti_qspi_dra_test | 11 U-Boot# mmc dev 0 13 U-Boot# fatload mmc 0 0x82000000 MLO 16 U-Boot# fatload mmc 0 0x83000000 u-boot.img 23 U-Boot# sf probe 0 26 U-Boot# sf erase 0 0x10000 27 SF: 65536 bytes @ 0x0 Erased: OK 28 U-Boot# sf erase 0x20000 0x10000 29 SF: 65536 bytes @ 0x20000 Erased: OK 30 U-Boot# sf erase 0x30000 0x10000 31 SF: 65536 bytes @ 0x30000 Erased: OK [all …]
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | openbmc-flash-layout.dtsi | 8 u-boot@0 { 9 reg = <0x0 0x60000>; 14 reg = <0x60000 0x20000>; 19 reg = <0x80000 0x440000>; 24 reg = <0x4c0000 0x1740000>; 29 reg = <0x1c00000 0x400000>;
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| H A D | facebook-bmc-flash-layout.dtsi | 9 u-boot@0 { 10 reg = <0x0 0x60000>; 15 reg = <0x60000 0x20000>; 20 reg = <0x80000 0x1b80000>; 29 reg = <0x1c00000 0x400000>; 38 flash0@0 { 39 reg = <0x0 0x2000000>;
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| H A D | kirkwood-linkstation.dtsi | 61 m25p40@0 { 65 reg = <0>; 67 mode = <0>; 69 partition@0 { 70 reg = <0x0 0x60000>; 76 reg = <0x60000 0x10000>; 82 reg = <0x70000 0x10000>; 92 #size-cells = <0>; 93 pinctrl-0 = <&pmx_button_function &pmx_power_switch 117 pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm [all …]
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| H A D | aspeed-bmc-opp-mowgli.dts | 18 reg = <0x80000000 0x20000000>; 28 reg = <0x98000000 0x04000000>; /* 64M */ 32 size = <0x01000000>; 33 alignment = <0x01000000>; 39 size = <0x02000000>; 40 alignment = <0x01000000>; 69 gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; 70 linux,code = <ASPEED_GPIO(Z, 0)>; 121 gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; 139 gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; [all …]
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| H A D | mt7629-rfb.dts | 41 reg = <0x40000000 0x10000000>; 65 pinctrl-0 = <ð_pins>; 69 gmac0: mac@0 { 71 reg = <0>; 89 #size-cells = <0>; 91 phy0: ethernet-phy@0 { 92 reg = <0>; 99 pinctrl-0 = <&i2c_pins>; 105 pinctrl-0 = <&qspi_pins>; 108 flash@0 { [all …]
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| H A D | kirkwood-lsxl.dtsi | 80 m25p40@0 { 84 reg = <0>; 86 mode = <0>; 88 partition@0 { 89 reg = <0x0 0x60000>; 95 reg = <0x60000 0x10000>; 101 reg = <0x70000 0x10000>; 111 #size-cells = <0>; 112 pinctrl-0 = <&pmx_button_function &pmx_power_switch 137 pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm [all …]
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| H A D | aspeed-bmc-opp-witherspoon.dts | 17 reg = <0x80000000 0x20000000>; 27 reg = <0x98000000 0x04000000>; /* 64M */ 33 reg = <0x9f000000 0x01000000>; /* 16M */ 37 size = <0x01000000>; 38 alignment = <0x01000000>; 44 size = <0x02000000>; /* 32MM */ 45 alignment = <0x01000000>; 74 gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; 75 linux,code = <ASPEED_GPIO(N, 0)>; 119 gpios = <&pca0 0 GPIO_ACTIVE_LOW>; [all …]
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| H A D | aspeed-bmc-opp-swift.dts | 17 reg = <0x80000000 0x20000000>; 27 reg = <0x98000000 0x04000000>; /* 64M */ 31 size = <0x01000000>; 32 alignment = <0x01000000>; 61 gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; 62 linux,code = <ASPEED_GPIO(N, 0)>; 73 gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; 74 linux,code = <ASPEED_GPIO(I, 0)>; 148 gpios = <&pca0 0 GPIO_ACTIVE_LOW>; 190 gpios = <&pca1 0 GPIO_ACTIVE_LOW>; [all …]
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| /OK3568_Linux_fs/u-boot/include/configs/ |
| H A D | smdkc100.h | 32 #define CONFIG_SYS_SDRAM_BASE 0x30000000 35 #define CONFIG_SYS_TEXT_BASE 0x34800000 44 * 1MB = 0x100000, 0x100000 = 1024 * 1024 51 #define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */ 69 #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \ 70 " onenand write 0x32008000 0x0 0x40000\0" 76 "onenand erase 0x60000 0x300000;" \ 77 "onenand write 0x31008000 0x60000 0x300000\0" \ 80 "onenand write 0x32000000 0x1260000 0x8C0000\0" \ 82 "onenand read 0x30007FC0 0x60000 0x300000;" \ [all …]
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| H A D | openrd.h | 39 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ 45 #define CONFIG_ENV_SIZE 0x20000 /* 128k */ 46 #define CONFIG_ENV_ADDR 0x60000 47 #define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ 59 "${x_bootcmd_usb}; bootm 0x6400000;" 62 #define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ 63 "0x400000@0x100000(uImage),"\ 64 "0x1fb00000@0x500000(rootfs)" 67 "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ 68 "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ [all …]
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| H A D | devkit3250.h | 31 #define CONFIG_SYS_TEXT_BASE 0x83F00000 75 #define CONFIG_PHY_ADDR 0x1F 106 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 114 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d 134 #define CONFIG_ENV_OFFSET 0x000A0000 145 "autoload=no\0" \ 146 "ethaddr=00:01:90:00:C0:81\0" \ 147 "dtbaddr=0x81000000\0" \ 148 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ 149 "tftpdir=vladimir/oe/devkit3250\0" \ [all …]
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| H A D | ea20.h | 35 #define CONFIG_SYS_TEXT_BASE 0xc1080000 41 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 4*1024*1024) /* malloc() len */ 47 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 50 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 89 #define CONFIG_ENV_OFFSET 0x80000 107 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 116 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 150 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 151 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 160 "as=3\0" \ [all …]
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| /OK3568_Linux_fs/u-boot/arch/arc/dts/ |
| H A D | axs10x_mb.dtsi | 12 ranges = <0x00000000 0xe0000000 0x10000000>; 22 #clock-cells = <0>; 28 #clock-cells = <0>; 36 reg = < 0x18000 0x2000 >; 46 ehci@0x40000 { 48 reg = < 0x40000 0x100 >; 52 ohci@0x60000 { 54 reg = < 0x60000 0x100 >; 60 reg = <0x22000 0x100>;
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/stm32/ |
| H A D | st,mlahb.yaml | 61 reg = <0x10000000 0x40000>; 63 dma-ranges = <0x00000000 0x38000000 0x10000>, 64 <0x10000000 0x10000000 0x60000>, 65 <0x30000000 0x30000000 0x60000>; 68 reg = <0x10000000 0x40000>;
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| /OK3568_Linux_fs/kernel/drivers/clk/imx/ |
| H A D | clk-imx8qxp-lpcg.h | 11 #define LSIO_PWM_0_LPCG 0x00000 12 #define LSIO_PWM_1_LPCG 0x10000 13 #define LSIO_PWM_2_LPCG 0x20000 14 #define LSIO_PWM_3_LPCG 0x30000 15 #define LSIO_PWM_4_LPCG 0x40000 16 #define LSIO_PWM_5_LPCG 0x50000 17 #define LSIO_PWM_6_LPCG 0x60000 18 #define LSIO_PWM_7_LPCG 0x70000 19 #define LSIO_GPIO_0_LPCG 0x80000 20 #define LSIO_GPIO_1_LPCG 0x90000 [all …]
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| /OK3568_Linux_fs/u-boot/configs/ |
| H A D | smdkc100_defconfig | 8 …n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x3… 24 CONFIG_SMC911X_BASE=0x98800300
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000/ |
| H A D | nfp_xpb.h | 14 #define NFP_XPB_OVERLAY(island) (((island) & 0x3f) << 24) 16 #define NFP_XPB_ISLAND(island) (NFP_XPB_OVERLAY(island) + 0x60000) 18 #define NFP_XPB_ISLAND_of(offset) (((offset) >> 24) & 0x3F) 25 (((device) & 0x3f) << 16))
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/ |
| H A D | bcmdevs_legacy.h | 28 #define BCM_DNGL_BL_PID_4322 0xbd13 29 #define BCM_DNGL_BL_PID_4319 0xbd16 30 #define BCM_DNGL_BL_PID_43236 0xbd17 31 #define BCM_DNGL_BL_PID_43143 0xbd1e 32 #define BCM_DNGL_BL_PID_43242 0xbd1f 33 #define BCM_DNGL_BL_PID_4350 0xbd23 34 #define BCM_DNGL_BL_PID_43569 0xbd27 37 #define BCM4335_D11AC_ID 0x43ae 38 #define BCM4335_D11AC2G_ID 0x43af 39 #define BCM4335_D11AC5G_ID 0x43b0 [all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/ |
| H A D | bcmdevs_legacy.h | 28 #define BCM_DNGL_BL_PID_4322 0xbd13 29 #define BCM_DNGL_BL_PID_4319 0xbd16 30 #define BCM_DNGL_BL_PID_43236 0xbd17 31 #define BCM_DNGL_BL_PID_43143 0xbd1e 32 #define BCM_DNGL_BL_PID_43242 0xbd1f 33 #define BCM_DNGL_BL_PID_4350 0xbd23 34 #define BCM_DNGL_BL_PID_43569 0xbd27 37 #define BCM4335_D11AC_ID 0x43ae 38 #define BCM4335_D11AC2G_ID 0x43af 39 #define BCM4335_D11AC5G_ID 0x43b0 [all …]
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| /OK3568_Linux_fs/u-boot/board/qualcomm/dragonboard410c/ |
| H A D | head.S | 20 .word 0 24 .quad 0 /* 0x60000 - ignored */ 26 .quad 0 27 .quad 0 /* reserved */ 28 .quad 0 /* reserved */ 29 .quad 0 /* reserved */ 30 .byte 0x41 /* Magic number, "ARM\x64" */ 31 .byte 0x52 32 .byte 0x4d 33 .byte 0x64 [all …]
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| /OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/ |
| H A D | mpc8308rdb.dts | 26 #size-cells = <0>; 28 PowerPC,8308@0 { 30 reg = <0x0>; 35 timebase-frequency = <0>; // from bootloader 36 bus-frequency = <0>; // from bootloader 37 clock-frequency = <0>; // from bootloader 43 reg = <0x00000000 0x08000000>; // 128MB at 0 50 reg = <0xe0005000 0x1000>; 51 interrupts = <77 0x8>; 57 ranges = <0x0 0x0 0xfe000000 0x00800000 [all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath10k/ |
| H A D | ahb.h | 34 #define ATH10K_GCC_REG_BASE 0x1800000 35 #define ATH10K_GCC_REG_SIZE 0x60000 37 #define ATH10K_TCSR_REG_BASE 0x1900000 38 #define ATH10K_TCSR_REG_SIZE 0x80000 40 #define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020 41 #define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014 43 #define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030 45 #define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000 46 #define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004 49 #define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000 [all …]
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