1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun axs10x_mb@e0000000 { 9*4882a593Smuzhiyun compatible = "simple-bus"; 10*4882a593Smuzhiyun #address-cells = <1>; 11*4882a593Smuzhiyun #size-cells = <1>; 12*4882a593Smuzhiyun ranges = <0x00000000 0xe0000000 0x10000000>; 13*4882a593Smuzhiyun u-boot,dm-pre-reloc; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun clocks { 16*4882a593Smuzhiyun compatible = "simple-bus"; 17*4882a593Smuzhiyun u-boot,dm-pre-reloc; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun apbclk: apbclk { 20*4882a593Smuzhiyun compatible = "fixed-clock"; 21*4882a593Smuzhiyun clock-frequency = <50000000>; 22*4882a593Smuzhiyun #clock-cells = <0>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun uartclk: uartclk { 26*4882a593Smuzhiyun compatible = "fixed-clock"; 27*4882a593Smuzhiyun clock-frequency = <33333333>; 28*4882a593Smuzhiyun #clock-cells = <0>; 29*4882a593Smuzhiyun u-boot,dm-pre-reloc; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun ethernet@18000 { 34*4882a593Smuzhiyun #interrupt-cells = <1>; 35*4882a593Smuzhiyun compatible = "altr,socfpga-stmmac"; 36*4882a593Smuzhiyun reg = < 0x18000 0x2000 >; 37*4882a593Smuzhiyun interrupts = < 25 >; 38*4882a593Smuzhiyun interrupt-names = "macirq"; 39*4882a593Smuzhiyun phy-mode = "gmii"; 40*4882a593Smuzhiyun snps,pbl = < 32 >; 41*4882a593Smuzhiyun clocks = <&apbclk>; 42*4882a593Smuzhiyun clock-names = "stmmaceth"; 43*4882a593Smuzhiyun max-speed = <100>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun ehci@0x40000 { 47*4882a593Smuzhiyun compatible = "generic-ehci"; 48*4882a593Smuzhiyun reg = < 0x40000 0x100 >; 49*4882a593Smuzhiyun interrupts = < 8 >; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ohci@0x60000 { 53*4882a593Smuzhiyun compatible = "generic-ohci"; 54*4882a593Smuzhiyun reg = < 0x60000 0x100 >; 55*4882a593Smuzhiyun interrupts = < 8 >; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun uart0: serial0@22000 { 59*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 60*4882a593Smuzhiyun reg = <0x22000 0x100>; 61*4882a593Smuzhiyun clocks = <&uartclk>; 62*4882a593Smuzhiyun reg-shift = <2>; 63*4882a593Smuzhiyun reg-io-width = <4>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun}; 67