1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2018 NXP 4*4882a593Smuzhiyun * Dong Aisheng <aisheng.dong@nxp.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _IMX8QXP_LPCG_H 8*4882a593Smuzhiyun #define _IMX8QXP_LPCG_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /*LSIO SS */ 11*4882a593Smuzhiyun #define LSIO_PWM_0_LPCG 0x00000 12*4882a593Smuzhiyun #define LSIO_PWM_1_LPCG 0x10000 13*4882a593Smuzhiyun #define LSIO_PWM_2_LPCG 0x20000 14*4882a593Smuzhiyun #define LSIO_PWM_3_LPCG 0x30000 15*4882a593Smuzhiyun #define LSIO_PWM_4_LPCG 0x40000 16*4882a593Smuzhiyun #define LSIO_PWM_5_LPCG 0x50000 17*4882a593Smuzhiyun #define LSIO_PWM_6_LPCG 0x60000 18*4882a593Smuzhiyun #define LSIO_PWM_7_LPCG 0x70000 19*4882a593Smuzhiyun #define LSIO_GPIO_0_LPCG 0x80000 20*4882a593Smuzhiyun #define LSIO_GPIO_1_LPCG 0x90000 21*4882a593Smuzhiyun #define LSIO_GPIO_2_LPCG 0xa0000 22*4882a593Smuzhiyun #define LSIO_GPIO_3_LPCG 0xb0000 23*4882a593Smuzhiyun #define LSIO_GPIO_4_LPCG 0xc0000 24*4882a593Smuzhiyun #define LSIO_GPIO_5_LPCG 0xd0000 25*4882a593Smuzhiyun #define LSIO_GPIO_6_LPCG 0xe0000 26*4882a593Smuzhiyun #define LSIO_GPIO_7_LPCG 0xf0000 27*4882a593Smuzhiyun #define LSIO_FSPI_0_LPCG 0x120000 28*4882a593Smuzhiyun #define LSIO_FSPI_1_LPCG 0x130000 29*4882a593Smuzhiyun #define LSIO_GPT_0_LPCG 0x140000 30*4882a593Smuzhiyun #define LSIO_GPT_1_LPCG 0x150000 31*4882a593Smuzhiyun #define LSIO_GPT_2_LPCG 0x160000 32*4882a593Smuzhiyun #define LSIO_GPT_3_LPCG 0x170000 33*4882a593Smuzhiyun #define LSIO_GPT_4_LPCG 0x180000 34*4882a593Smuzhiyun #define LSIO_OCRAM_LPCG 0x190000 35*4882a593Smuzhiyun #define LSIO_KPP_LPCG 0x1a0000 36*4882a593Smuzhiyun #define LSIO_ROMCP_LPCG 0x100000 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Connectivity SS */ 39*4882a593Smuzhiyun #define CONN_USDHC_0_LPCG 0x00000 40*4882a593Smuzhiyun #define CONN_USDHC_1_LPCG 0x10000 41*4882a593Smuzhiyun #define CONN_USDHC_2_LPCG 0x20000 42*4882a593Smuzhiyun #define CONN_ENET_0_LPCG 0x30000 43*4882a593Smuzhiyun #define CONN_ENET_1_LPCG 0x40000 44*4882a593Smuzhiyun #define CONN_DTCP_LPCG 0x50000 45*4882a593Smuzhiyun #define CONN_MLB_LPCG 0x60000 46*4882a593Smuzhiyun #define CONN_USB_2_LPCG 0x70000 47*4882a593Smuzhiyun #define CONN_USB_3_LPCG 0x80000 48*4882a593Smuzhiyun #define CONN_NAND_LPCG 0x90000 49*4882a593Smuzhiyun #define CONN_EDMA_LPCG 0xa0000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* ADMA SS */ 52*4882a593Smuzhiyun #define ADMA_ASRC_0_LPCG 0x400000 53*4882a593Smuzhiyun #define ADMA_ESAI_0_LPCG 0x410000 54*4882a593Smuzhiyun #define ADMA_SPDIF_0_LPCG 0x420000 55*4882a593Smuzhiyun #define ADMA_SAI_0_LPCG 0x440000 56*4882a593Smuzhiyun #define ADMA_SAI_1_LPCG 0x450000 57*4882a593Smuzhiyun #define ADMA_SAI_2_LPCG 0x460000 58*4882a593Smuzhiyun #define ADMA_SAI_3_LPCG 0x470000 59*4882a593Smuzhiyun #define ADMA_GPT_5_LPCG 0x4b0000 60*4882a593Smuzhiyun #define ADMA_GPT_6_LPCG 0x4c0000 61*4882a593Smuzhiyun #define ADMA_GPT_7_LPCG 0x4d0000 62*4882a593Smuzhiyun #define ADMA_GPT_8_LPCG 0x4e0000 63*4882a593Smuzhiyun #define ADMA_GPT_9_LPCG 0x4f0000 64*4882a593Smuzhiyun #define ADMA_GPT_10_LPCG 0x500000 65*4882a593Smuzhiyun #define ADMA_HIFI_LPCG 0x580000 66*4882a593Smuzhiyun #define ADMA_OCRAM_LPCG 0x590000 67*4882a593Smuzhiyun #define ADMA_EDMA_0_LPCG 0x5f0000 68*4882a593Smuzhiyun #define ADMA_ASRC_1_LPCG 0xc00000 69*4882a593Smuzhiyun #define ADMA_SAI_4_LPCG 0xc20000 70*4882a593Smuzhiyun #define ADMA_SAI_5_LPCG 0xc30000 71*4882a593Smuzhiyun #define ADMA_AMIX_LPCG 0xc40000 72*4882a593Smuzhiyun #define ADMA_MQS_LPCG 0xc50000 73*4882a593Smuzhiyun #define ADMA_ACM_LPCG 0xc60000 74*4882a593Smuzhiyun #define ADMA_REC_CLK0_LPCG 0xd00000 75*4882a593Smuzhiyun #define ADMA_REC_CLK1_LPCG 0xd10000 76*4882a593Smuzhiyun #define ADMA_PLL_CLK0_LPCG 0xd20000 77*4882a593Smuzhiyun #define ADMA_PLL_CLK1_LPCG 0xd30000 78*4882a593Smuzhiyun #define ADMA_MCLKOUT0_LPCG 0xd50000 79*4882a593Smuzhiyun #define ADMA_MCLKOUT1_LPCG 0xd60000 80*4882a593Smuzhiyun #define ADMA_EDMA_1_LPCG 0xdf0000 81*4882a593Smuzhiyun #define ADMA_LPSPI_0_LPCG 0x1400000 82*4882a593Smuzhiyun #define ADMA_LPSPI_1_LPCG 0x1410000 83*4882a593Smuzhiyun #define ADMA_LPSPI_2_LPCG 0x1420000 84*4882a593Smuzhiyun #define ADMA_LPSPI_3_LPCG 0x1430000 85*4882a593Smuzhiyun #define ADMA_LPUART_0_LPCG 0x1460000 86*4882a593Smuzhiyun #define ADMA_LPUART_1_LPCG 0x1470000 87*4882a593Smuzhiyun #define ADMA_LPUART_2_LPCG 0x1480000 88*4882a593Smuzhiyun #define ADMA_LPUART_3_LPCG 0x1490000 89*4882a593Smuzhiyun #define ADMA_LCD_LPCG 0x1580000 90*4882a593Smuzhiyun #define ADMA_PWM_LPCG 0x1590000 91*4882a593Smuzhiyun #define ADMA_LPI2C_0_LPCG 0x1c00000 92*4882a593Smuzhiyun #define ADMA_LPI2C_1_LPCG 0x1c10000 93*4882a593Smuzhiyun #define ADMA_LPI2C_2_LPCG 0x1c20000 94*4882a593Smuzhiyun #define ADMA_LPI2C_3_LPCG 0x1c30000 95*4882a593Smuzhiyun #define ADMA_ADC_0_LPCG 0x1c80000 96*4882a593Smuzhiyun #define ADMA_FTM_0_LPCG 0x1ca0000 97*4882a593Smuzhiyun #define ADMA_FTM_1_LPCG 0x1cb0000 98*4882a593Smuzhiyun #define ADMA_FLEXCAN_0_LPCG 0x1cd0000 99*4882a593Smuzhiyun #define ADMA_FLEXCAN_1_LPCG 0x1ce0000 100*4882a593Smuzhiyun #define ADMA_FLEXCAN_2_LPCG 0x1cf0000 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* _IMX8QXP_LPCG_H */ 103