xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/mt7629-rfb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Ryder Lee <ryder.lee@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
9*4882a593Smuzhiyun#include "mt7629.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "MediaTek MT7629 reference board";
13*4882a593Smuzhiyun	compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	aliases {
16*4882a593Smuzhiyun		serial0 = &uart0;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	chosen {
20*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	gpio-keys {
24*4882a593Smuzhiyun		compatible = "gpio-keys";
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		reset {
27*4882a593Smuzhiyun			label = "factory";
28*4882a593Smuzhiyun			linux,code = <KEY_RESTART>;
29*4882a593Smuzhiyun			gpios = <&pio 60 GPIO_ACTIVE_LOW>;
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		wps {
33*4882a593Smuzhiyun			label = "wps";
34*4882a593Smuzhiyun			linux,code = <KEY_WPS_BUTTON>;
35*4882a593Smuzhiyun			gpios = <&pio 58 GPIO_ACTIVE_LOW>;
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	memory@40000000 {
40*4882a593Smuzhiyun		device_type = "memory";
41*4882a593Smuzhiyun		reg = <0x40000000 0x10000000>;
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
45*4882a593Smuzhiyun		compatible = "regulator-fixed";
46*4882a593Smuzhiyun		regulator-name = "fixed-3.3V";
47*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
48*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
49*4882a593Smuzhiyun		regulator-boot-on;
50*4882a593Smuzhiyun		regulator-always-on;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	reg_5v: regulator-5v {
54*4882a593Smuzhiyun		compatible = "regulator-fixed";
55*4882a593Smuzhiyun		regulator-name = "fixed-5V";
56*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
57*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
58*4882a593Smuzhiyun		regulator-boot-on;
59*4882a593Smuzhiyun		regulator-always-on;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun&eth {
64*4882a593Smuzhiyun	pinctrl-names = "default";
65*4882a593Smuzhiyun	pinctrl-0 = <&eth_pins>;
66*4882a593Smuzhiyun	pinctrl-1 = <&ephy_leds_pins>;
67*4882a593Smuzhiyun	status = "okay";
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	gmac0: mac@0 {
70*4882a593Smuzhiyun		compatible = "mediatek,eth-mac";
71*4882a593Smuzhiyun		reg = <0>;
72*4882a593Smuzhiyun		phy-mode = "2500base-x";
73*4882a593Smuzhiyun		fixed-link {
74*4882a593Smuzhiyun			speed = <2500>;
75*4882a593Smuzhiyun			full-duplex;
76*4882a593Smuzhiyun			pause;
77*4882a593Smuzhiyun		};
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	gmac1: mac@1 {
81*4882a593Smuzhiyun		compatible = "mediatek,eth-mac";
82*4882a593Smuzhiyun		reg = <1>;
83*4882a593Smuzhiyun		phy-mode = "gmii";
84*4882a593Smuzhiyun		phy-handle = <&phy0>;
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	mdio: mdio-bus {
88*4882a593Smuzhiyun		#address-cells = <1>;
89*4882a593Smuzhiyun		#size-cells = <0>;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun		phy0: ethernet-phy@0 {
92*4882a593Smuzhiyun			reg = <0>;
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun&i2c {
98*4882a593Smuzhiyun	pinctrl-names = "default";
99*4882a593Smuzhiyun	pinctrl-0 = <&i2c_pins>;
100*4882a593Smuzhiyun	status = "okay";
101*4882a593Smuzhiyun};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun&qspi {
104*4882a593Smuzhiyun	pinctrl-names = "default";
105*4882a593Smuzhiyun	pinctrl-0 = <&qspi_pins>;
106*4882a593Smuzhiyun	status = "okay";
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	flash@0 {
109*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
110*4882a593Smuzhiyun		reg = <0>;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun		partitions {
113*4882a593Smuzhiyun			compatible = "fixed-partitions";
114*4882a593Smuzhiyun			#address-cells = <1>;
115*4882a593Smuzhiyun			#size-cells = <1>;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun			partition@0 {
118*4882a593Smuzhiyun				label = "u-boot";
119*4882a593Smuzhiyun				reg = <0x00000 0x60000>;
120*4882a593Smuzhiyun				read-only;
121*4882a593Smuzhiyun			};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun			partition@60000 {
124*4882a593Smuzhiyun				label = "u-boot-env";
125*4882a593Smuzhiyun				reg = <0x60000 0x10000>;
126*4882a593Smuzhiyun				read-only;
127*4882a593Smuzhiyun			};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun			factory: partition@70000 {
130*4882a593Smuzhiyun				label = "factory";
131*4882a593Smuzhiyun				reg = <0x70000 0x40000>;
132*4882a593Smuzhiyun				read-only;
133*4882a593Smuzhiyun			};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun			partition@b0000 {
136*4882a593Smuzhiyun				label = "kernel";
137*4882a593Smuzhiyun				reg = <0xb0000 0xb50000>;
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun&pcie {
144*4882a593Smuzhiyun	pinctrl-names = "default";
145*4882a593Smuzhiyun	pinctrl-0 = <&pcie_pins>;
146*4882a593Smuzhiyun};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun&pciephy1 {
149*4882a593Smuzhiyun	status = "okay";
150*4882a593Smuzhiyun};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun&pio {
153*4882a593Smuzhiyun	eth_pins: eth-pins {
154*4882a593Smuzhiyun		mux {
155*4882a593Smuzhiyun			function = "eth";
156*4882a593Smuzhiyun			groups = "mdc_mdio";
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	ephy_leds_pins: ephy-leds-pins {
161*4882a593Smuzhiyun		mux {
162*4882a593Smuzhiyun			function = "led";
163*4882a593Smuzhiyun			groups = "gphy_leds_0", "ephy_leds";
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	i2c_pins: i2c-pins {
168*4882a593Smuzhiyun		mux {
169*4882a593Smuzhiyun			function = "i2c";
170*4882a593Smuzhiyun			groups =  "i2c_0";
171*4882a593Smuzhiyun		};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun		conf {
174*4882a593Smuzhiyun			pins = "I2C_SDA", "I2C_SCL";
175*4882a593Smuzhiyun			drive-strength = <4>;
176*4882a593Smuzhiyun			bias-disable;
177*4882a593Smuzhiyun		};
178*4882a593Smuzhiyun	};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun	pcie_pins: pcie-pins {
181*4882a593Smuzhiyun		mux {
182*4882a593Smuzhiyun			function = "pcie";
183*4882a593Smuzhiyun			groups = "pcie_clkreq",
184*4882a593Smuzhiyun				 "pcie_pereset",
185*4882a593Smuzhiyun				 "pcie_wake";
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	pwm_pins: pwm-pins {
190*4882a593Smuzhiyun		mux {
191*4882a593Smuzhiyun			function = "pwm";
192*4882a593Smuzhiyun			groups = "pwm_0";
193*4882a593Smuzhiyun		};
194*4882a593Smuzhiyun	};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun	/* SPI-NOR is shared pin with serial NAND */
197*4882a593Smuzhiyun	qspi_pins: qspi-pins {
198*4882a593Smuzhiyun		mux {
199*4882a593Smuzhiyun			function = "flash";
200*4882a593Smuzhiyun			groups = "spi_nor";
201*4882a593Smuzhiyun		};
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun	/* Serial NAND is shared pin with SPI-NOR */
205*4882a593Smuzhiyun	serial_nand_pins: serial-nand-pins {
206*4882a593Smuzhiyun		mux {
207*4882a593Smuzhiyun			function = "flash";
208*4882a593Smuzhiyun			groups = "snfi";
209*4882a593Smuzhiyun		};
210*4882a593Smuzhiyun	};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun	spi_pins: spi-pins {
213*4882a593Smuzhiyun		mux {
214*4882a593Smuzhiyun			function = "spi";
215*4882a593Smuzhiyun			groups = "spi_0";
216*4882a593Smuzhiyun		};
217*4882a593Smuzhiyun	};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun	uart0_pins: uart0-pins {
220*4882a593Smuzhiyun		mux {
221*4882a593Smuzhiyun			function = "uart";
222*4882a593Smuzhiyun			groups = "uart0_txd_rxd" ;
223*4882a593Smuzhiyun		};
224*4882a593Smuzhiyun	};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun	uart1_pins: uart1-pins {
227*4882a593Smuzhiyun		mux {
228*4882a593Smuzhiyun			function = "uart";
229*4882a593Smuzhiyun			groups = "uart1_0_tx_rx" ;
230*4882a593Smuzhiyun		};
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	uart2_pins: uart2-pins {
234*4882a593Smuzhiyun		mux {
235*4882a593Smuzhiyun			function = "uart";
236*4882a593Smuzhiyun			groups = "uart2_0_txd_rxd" ;
237*4882a593Smuzhiyun		};
238*4882a593Smuzhiyun	};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun	watchdog_pins: watchdog-pins {
241*4882a593Smuzhiyun		mux {
242*4882a593Smuzhiyun			function = "watchdog";
243*4882a593Smuzhiyun			groups = "watchdog";
244*4882a593Smuzhiyun		};
245*4882a593Smuzhiyun	};
246*4882a593Smuzhiyun};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun&spi {
249*4882a593Smuzhiyun	pinctrl-names = "default";
250*4882a593Smuzhiyun	pinctrl-0 = <&spi_pins>;
251*4882a593Smuzhiyun	status = "okay";
252*4882a593Smuzhiyun};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun&ssusb {
255*4882a593Smuzhiyun	vusb33-supply = <&reg_3p3v>;
256*4882a593Smuzhiyun	vbus-supply = <&reg_5v>;
257*4882a593Smuzhiyun	status = "okay";
258*4882a593Smuzhiyun};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun&u3phy0 {
261*4882a593Smuzhiyun	status = "okay";
262*4882a593Smuzhiyun};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun&uart0 {
265*4882a593Smuzhiyun	pinctrl-names = "default";
266*4882a593Smuzhiyun	pinctrl-0 = <&uart0_pins>;
267*4882a593Smuzhiyun	status = "okay";
268*4882a593Smuzhiyun};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun&watchdog {
271*4882a593Smuzhiyun	pinctrl-names = "default";
272*4882a593Smuzhiyun	pinctrl-0 = <&watchdog_pins>;
273*4882a593Smuzhiyun	status = "okay";
274*4882a593Smuzhiyun};
275