1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved. 4*4882a593Smuzhiyun * Copyright (c) 2015 The Linux Foundation. All rights reserved. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _AHB_H_ 8*4882a593Smuzhiyun #define _AHB_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/platform_device.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct ath10k_ahb { 13*4882a593Smuzhiyun struct platform_device *pdev; 14*4882a593Smuzhiyun void __iomem *mem; 15*4882a593Smuzhiyun unsigned long mem_len; 16*4882a593Smuzhiyun void __iomem *gcc_mem; 17*4882a593Smuzhiyun void __iomem *tcsr_mem; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun int irq; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct clk *cmd_clk; 22*4882a593Smuzhiyun struct clk *ref_clk; 23*4882a593Smuzhiyun struct clk *rtc_clk; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct reset_control *core_cold_rst; 26*4882a593Smuzhiyun struct reset_control *radio_cold_rst; 27*4882a593Smuzhiyun struct reset_control *radio_warm_rst; 28*4882a593Smuzhiyun struct reset_control *radio_srif_rst; 29*4882a593Smuzhiyun struct reset_control *cpu_init_rst; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifdef CONFIG_ATH10K_AHB 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define ATH10K_GCC_REG_BASE 0x1800000 35*4882a593Smuzhiyun #define ATH10K_GCC_REG_SIZE 0x60000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define ATH10K_TCSR_REG_BASE 0x1900000 38*4882a593Smuzhiyun #define ATH10K_TCSR_REG_SIZE 0x80000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020 41*4882a593Smuzhiyun #define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000 46*4882a593Smuzhiyun #define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004 47*4882a593Smuzhiyun #define TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK BIT(25) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000 50*4882a593Smuzhiyun #define ATH10K_AHB_TCSR_WCSS1_HALTREQ 0x52010 51*4882a593Smuzhiyun #define ATH10K_AHB_TCSR_WCSS0_HALTACK 0x52004 52*4882a593Smuzhiyun #define ATH10K_AHB_TCSR_WCSS1_HALTACK 0x52014 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define ATH10K_AHB_AXI_BUS_HALT_TIMEOUT 10 /* msec */ 55*4882a593Smuzhiyun #define AHB_AXI_BUS_HALT_REQ 1 56*4882a593Smuzhiyun #define AHB_AXI_BUS_HALT_ACK 1 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK 1 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun int ath10k_ahb_init(void); 61*4882a593Smuzhiyun void ath10k_ahb_exit(void); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #else /* CONFIG_ATH10K_AHB */ 64*4882a593Smuzhiyun ath10k_ahb_init(void)65*4882a593Smuzhiyunstatic inline int ath10k_ahb_init(void) 66*4882a593Smuzhiyun { 67*4882a593Smuzhiyun return 0; 68*4882a593Smuzhiyun } 69*4882a593Smuzhiyun ath10k_ahb_exit(void)70*4882a593Smuzhiyunstatic inline void ath10k_ahb_exit(void) 71*4882a593Smuzhiyun { 72*4882a593Smuzhiyun } 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* CONFIG_ATH10K_AHB */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* _AHB_H_ */ 77