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/OK3568_Linux_fs/kernel/drivers/of/unittest-data/
H A Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x40000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/sbc/
H A Dsbc.c14 #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
15 #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
16 #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
18 #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
19 #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
20 #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
23 #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
24 #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
25 #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
26 #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Drcar-pci.txt55 reg = <0 0xfe000000 0 0x80000>;
58 bus-range = <0x00 0xff>;
60 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
61 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
62 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
63 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
64 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
65 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
66 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
68 interrupt-map-mask = <0 0 0 0>;
[all …]
H A Dcdns,cdns-pcie-host.yaml47 bus-range = <0x0 0xff>;
48 linux,pci-domain = <0>;
49 vendor-id = <0x17cd>;
50 device-id = <0x0200>;
52 reg = <0x0 0xfb000000 0x0 0x01000000>,
53 <0x0 0x41000000 0x0 0x00001000>;
56 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
57 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
58 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
60 #interrupt-cells = <0x1>;
[all …]
H A Dxgene-pci.txt35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
H A Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
H A Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
H A Dbrcm,stb-pcie.yaml123 reg = <0x0 0x7d500000 0x9310>;
131 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
132 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
135 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
136 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
137 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
139 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
/OK3568_Linux_fs/kernel/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
30 #define XBUS_SIZE 0x00100000
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/platforms/44x/
H A Dcanyonlands.c19 #define BCSR_USB_EN 0x11
33 return 0; in ppc460ex_device_probe()
45 return 0; in ppc460ex_probe()
55 int ret = 0; in ppc460ex_canyonlands_fixup()
63 bcsr = of_iomap(np, 0); in ppc460ex_canyonlands_fixup()
78 vaddr = of_iomap(np, 0); in ppc460ex_canyonlands_fixup()
101 setbits32((vaddr + GPIO0_OSRH), 0x42000000); in ppc460ex_canyonlands_fixup()
102 setbits32((vaddr + GPIO0_TSRH), 0x42000000); in ppc460ex_canyonlands_fixup()
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
H A Duniphier-support-card.dtsi10 ranges = <1 0x00000000 0x42000000 0x02000000>;
15 reg = <1 0x01f00000 0x1000>;
22 reg = <1 0x01fb0000 0x20>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
H A Dakebono.dts14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
[all …]
H A Dkatmai.dts22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
H A Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dodroid.h20 #define CONFIG_SYS_PL310_BASE 0x10502000
26 #define CONFIG_SYS_SDRAM_BASE 0x40000000
35 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
36 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
37 #define CONFIG_SYS_TEXT_BASE 0x43e00000
47 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
52 #define CONFIG_SYS_MONITOR_BASE 0x00000000
64 "uImage fat 0 1;" \
65 "zImage fat 0 1;" \
66 "Image.itb fat 0 1;" \
[all …]
H A Dm28evk.h18 #define PHYS_SDRAM_1 0x40000000 /* Base address */
19 #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
60 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
75 #define CONFIG_DEFAULT_SPI_CS 0
81 #define CONFIG_SF_DEFAULT_CS 0
86 #define CONFIG_ENV_SPI_CS 0
106 #define CONFIG_LOADADDR 0x42000000
114 "consdev=ttyAMA0\0" \
115 "baudrate=115200\0" \
116 "bootscript=boot.scr\0" \
[all …]
H A Dxfi3.h16 #define PHYS_SDRAM_1 0x40000000 /* Base address */
17 #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
26 #define CONFIG_LOADADDR 0x42000000
H A Dsansa_fuze_plus.h16 #define PHYS_SDRAM_1 0x40000000 /* Base address */
17 #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
26 #define CONFIG_LOADADDR 0x42000000
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.odroid41 The block offset is starting from 0 and the block size is 512B.
46 | Bl1 | 1 | 0 | 1 (boot) |
50 | Uboot Env | 2560 | 2560 | 0 (user) |
178 scanning bus 0 for devices... 4 USB Device(s) found
233 Odroid # tftpboot 0x40080000 zImage.3.17
238 Load address: 0x40080000
246 Odroid # tftpboot 0x42000000 exynos4412-odroidu3.dtb
251 Load address: 0x42000000
260 Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ]
262 Booting using the fdt blob at 0x42000000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Duniphier-support-card.dtsi12 ranges = <1 0x00000000 0x42000000 0x02000000>;
18 ranges = <0x00000000 1 0x01f00000 0x00100000>;
20 ethsc: ethernet@0 {
22 reg = <0x00000000 0x1000>;
29 reg = <0x000b0000 0x20>;
/OK3568_Linux_fs/kernel/arch/arm/include/debug/
H A Ddc21285.S14 .equ dc21285_high, ARMCSR_BASE & 0xff000000
15 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
21 mov \rp, #0
24 orr \rp, \rp, #0x42000000
28 str \rd, [\rx, #0x160] @ UARTDR
32 1001: ldr \rd, [\rx, #0x178] @ UARTFLG

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