1*4882a593Smuzhiyun* AppliedMicro X-Gene v1 PCIe MSI controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: should be "apm,xgene1-msi" to identify 6*4882a593Smuzhiyun X-Gene v1 PCIe MSI controller block. 7*4882a593Smuzhiyun- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node 8*4882a593Smuzhiyun- reg: physical base address (0x79000000) and length (0x900000) for controller 9*4882a593Smuzhiyun registers. These registers include the MSI termination address and data 10*4882a593Smuzhiyun registers as well as the MSI interrupt status registers. 11*4882a593Smuzhiyun- reg-names: not required 12*4882a593Smuzhiyun- interrupts: A list of 16 interrupt outputs of the controller, starting from 13*4882a593Smuzhiyun interrupt number 0x10 to 0x1f. 14*4882a593Smuzhiyun- interrupt-names: not required 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunEach PCIe node needs to have property msi-parent that points to an MSI 17*4882a593Smuzhiyuncontroller node 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExamples: 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunSoC DTSI: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun + MSI node: 24*4882a593Smuzhiyun msi@79000000 { 25*4882a593Smuzhiyun compatible = "apm,xgene1-msi"; 26*4882a593Smuzhiyun msi-controller; 27*4882a593Smuzhiyun reg = <0x00 0x79000000 0x0 0x900000>; 28*4882a593Smuzhiyun interrupts = <0x0 0x10 0x4> 29*4882a593Smuzhiyun <0x0 0x11 0x4> 30*4882a593Smuzhiyun <0x0 0x12 0x4> 31*4882a593Smuzhiyun <0x0 0x13 0x4> 32*4882a593Smuzhiyun <0x0 0x14 0x4> 33*4882a593Smuzhiyun <0x0 0x15 0x4> 34*4882a593Smuzhiyun <0x0 0x16 0x4> 35*4882a593Smuzhiyun <0x0 0x17 0x4> 36*4882a593Smuzhiyun <0x0 0x18 0x4> 37*4882a593Smuzhiyun <0x0 0x19 0x4> 38*4882a593Smuzhiyun <0x0 0x1a 0x4> 39*4882a593Smuzhiyun <0x0 0x1b 0x4> 40*4882a593Smuzhiyun <0x0 0x1c 0x4> 41*4882a593Smuzhiyun <0x0 0x1d 0x4> 42*4882a593Smuzhiyun <0x0 0x1e 0x4> 43*4882a593Smuzhiyun <0x0 0x1f 0x4>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun + PCIe controller node with msi-parent property pointing to MSI node: 47*4882a593Smuzhiyun pcie0: pcie@1f2b0000 { 48*4882a593Smuzhiyun device_type = "pci"; 49*4882a593Smuzhiyun compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 50*4882a593Smuzhiyun #interrupt-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <2>; 52*4882a593Smuzhiyun #address-cells = <3>; 53*4882a593Smuzhiyun reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 54*4882a593Smuzhiyun 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 55*4882a593Smuzhiyun reg-names = "csr", "cfg"; 56*4882a593Smuzhiyun ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 57*4882a593Smuzhiyun 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ 58*4882a593Smuzhiyun dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 59*4882a593Smuzhiyun 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 60*4882a593Smuzhiyun interrupt-map-mask = <0x0 0x0 0x0 0x7>; 61*4882a593Smuzhiyun interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 62*4882a593Smuzhiyun 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 63*4882a593Smuzhiyun 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 64*4882a593Smuzhiyun 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; 65*4882a593Smuzhiyun dma-coherent; 66*4882a593Smuzhiyun clocks = <&pcie0clk 0>; 67*4882a593Smuzhiyun msi-parent= <&msi>; 68*4882a593Smuzhiyun }; 69