1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2011-2015 Panasonic Corporation
3*4882a593Smuzhiyun * Copyright (C) 2015-2017 Socionext Inc.
4*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "../init.h"
12*4882a593Smuzhiyun #include "sbc-regs.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
15*4882a593Smuzhiyun #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
16*4882a593Smuzhiyun #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
19*4882a593Smuzhiyun #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
20*4882a593Smuzhiyun #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* slower but LED works */
23*4882a593Smuzhiyun #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
24*4882a593Smuzhiyun #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
25*4882a593Smuzhiyun #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
26*4882a593Smuzhiyun #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* faster but LED does not work */
29*4882a593Smuzhiyun #define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
30*4882a593Smuzhiyun #define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
31*4882a593Smuzhiyun /* NOR flash needs more wait counts than SRAM */
32*4882a593Smuzhiyun #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
33*4882a593Smuzhiyun #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
34*4882a593Smuzhiyun
__uniphier_sbc_init(int savepin)35*4882a593Smuzhiyun static void __uniphier_sbc_init(int savepin)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * Only CS1 is connected to support card.
39*4882a593Smuzhiyun * BKSZ[1:0] should be set to "01".
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun if (savepin) {
42*4882a593Smuzhiyun writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
43*4882a593Smuzhiyun writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
44*4882a593Smuzhiyun writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
45*4882a593Smuzhiyun writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
46*4882a593Smuzhiyun } else {
47*4882a593Smuzhiyun writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
48*4882a593Smuzhiyun writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
49*4882a593Smuzhiyun writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (boot_is_swapped()) {
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * Boot Swap On: boot from external NOR/SRAM
55*4882a593Smuzhiyun * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
58*4882a593Smuzhiyun * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun writel(0x0000bc01, SBBASE0);
61*4882a593Smuzhiyun } else {
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * Boot Swap Off: boot from mask ROM
64*4882a593Smuzhiyun * 0x40000000-0x41ffffff: mask ROM
65*4882a593Smuzhiyun * 0x42000000-0x43efffff: memory bank (31MB)
66*4882a593Smuzhiyun * 0x43f00000-0x43ffffff: peripherals (1MB)
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun writel(0x0000be01, SBBASE0); /* dummy */
69*4882a593Smuzhiyun writel(0x0200be01, SBBASE1);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
uniphier_sbc_init_admulti(void)73*4882a593Smuzhiyun void uniphier_sbc_init_admulti(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun __uniphier_sbc_init(0);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
uniphier_sbc_init_savepin(void)78*4882a593Smuzhiyun void uniphier_sbc_init_savepin(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun __uniphier_sbc_init(1);
81*4882a593Smuzhiyun }
82