1*4882a593Smuzhiyun* AppliedMicro X-Gene PCIe interface 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- device_type: set to "pci" 5*4882a593Smuzhiyun- compatible: should contain "apm,xgene-pcie" to identify the core. 6*4882a593Smuzhiyun- reg: A list of physical base address and length for each set of controller 7*4882a593Smuzhiyun registers. Must contain an entry for each entry in the reg-names 8*4882a593Smuzhiyun property. 9*4882a593Smuzhiyun- reg-names: Must include the following entries: 10*4882a593Smuzhiyun "csr": controller configuration registers. 11*4882a593Smuzhiyun "cfg": PCIe configuration space registers. 12*4882a593Smuzhiyun- #address-cells: set to <3> 13*4882a593Smuzhiyun- #size-cells: set to <2> 14*4882a593Smuzhiyun- ranges: ranges for the outbound memory, I/O regions. 15*4882a593Smuzhiyun- dma-ranges: ranges for the inbound memory regions. 16*4882a593Smuzhiyun- #interrupt-cells: set to <1> 17*4882a593Smuzhiyun- interrupt-map-mask and interrupt-map: standard PCI properties 18*4882a593Smuzhiyun to define the mapping of the PCIe interface to interrupt 19*4882a593Smuzhiyun numbers. 20*4882a593Smuzhiyun- clocks: from common clock binding: handle to pci clock. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional properties: 23*4882a593Smuzhiyun- status: Either "ok" or "disabled". 24*4882a593Smuzhiyun- dma-coherent: Present if DMA operations are coherent 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun pcie0: pcie@1f2b0000 { 29*4882a593Smuzhiyun status = "disabled"; 30*4882a593Smuzhiyun device_type = "pci"; 31*4882a593Smuzhiyun compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 32*4882a593Smuzhiyun #interrupt-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <2>; 34*4882a593Smuzhiyun #address-cells = <3>; 35*4882a593Smuzhiyun reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 36*4882a593Smuzhiyun 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 37*4882a593Smuzhiyun reg-names = "csr", "cfg"; 38*4882a593Smuzhiyun ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 39*4882a593Smuzhiyun 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ 40*4882a593Smuzhiyun dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 41*4882a593Smuzhiyun 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 42*4882a593Smuzhiyun interrupt-map-mask = <0x0 0x0 0x0 0x7>; 43*4882a593Smuzhiyun interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 44*4882a593Smuzhiyun 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 45*4882a593Smuzhiyun 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 46*4882a593Smuzhiyun 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; 47*4882a593Smuzhiyun dma-coherent; 48*4882a593Smuzhiyun clocks = <&pcie0clk 0>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51