1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-footbridge/include/mach/hardware.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1998-1999 Russell King. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file contains the hardware definitions of the EBSA-285. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_HARDWARE_H 10*4882a593Smuzhiyun #define __ASM_ARCH_HARDWARE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Virtual Physical Size 13*4882a593Smuzhiyun * 0xff800000 0x40000000 1MB X-Bus 14*4882a593Smuzhiyun * 0xff000000 0x7c000000 1MB PCI I/O space 15*4882a593Smuzhiyun * 0xfe000000 0x42000000 1MB CSR 16*4882a593Smuzhiyun * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) 17*4882a593Smuzhiyun * 0xfc000000 0x79000000 1MB PCI IACK/special space 18*4882a593Smuzhiyun * 0xfb000000 0x7a000000 16MB PCI Config type 1 19*4882a593Smuzhiyun * 0xfa000000 0x7b000000 16MB PCI Config type 0 20*4882a593Smuzhiyun * 0xf9000000 0x50000000 1MB Cache flush 21*4882a593Smuzhiyun * 0xf0000000 0x80000000 16MB ISA memory 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifdef CONFIG_MMU 25*4882a593Smuzhiyun #define MMU_IO(a, b) (a) 26*4882a593Smuzhiyun #else 27*4882a593Smuzhiyun #define MMU_IO(a, b) (b) 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define XBUS_SIZE 0x00100000 31*4882a593Smuzhiyun #define XBUS_BASE MMU_IO(0xff800000, 0x40000000) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define ARMCSR_SIZE 0x00100000 34*4882a593Smuzhiyun #define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define WFLUSH_SIZE 0x00100000 37*4882a593Smuzhiyun #define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PCIIACK_SIZE 0x00100000 40*4882a593Smuzhiyun #define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define PCICFG1_SIZE 0x01000000 43*4882a593Smuzhiyun #define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define PCICFG0_SIZE 0x01000000 46*4882a593Smuzhiyun #define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define PCIMEM_SIZE 0x01000000 49*4882a593Smuzhiyun #define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define XBUS_CS2 0x40012000 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 54*4882a593Smuzhiyun #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) 55*4882a593Smuzhiyun #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) 56*4882a593Smuzhiyun #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) 57*4882a593Smuzhiyun #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* PIC irq control */ 63*4882a593Smuzhiyun #define PIC_LO 0x20 64*4882a593Smuzhiyun #define PIC_MASK_LO 0x21 65*4882a593Smuzhiyun #define PIC_HI 0xA0 66*4882a593Smuzhiyun #define PIC_MASK_HI 0xA1 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* GPIO pins */ 69*4882a593Smuzhiyun #define GPIO_CCLK 0x800 70*4882a593Smuzhiyun #define GPIO_DSCLK 0x400 71*4882a593Smuzhiyun #define GPIO_E2CLK 0x200 72*4882a593Smuzhiyun #define GPIO_IOLOAD 0x100 73*4882a593Smuzhiyun #define GPIO_RED_LED 0x080 74*4882a593Smuzhiyun #define GPIO_WDTIMER 0x040 75*4882a593Smuzhiyun #define GPIO_DATA 0x020 76*4882a593Smuzhiyun #define GPIO_IOCLK 0x010 77*4882a593Smuzhiyun #define GPIO_DONE 0x008 78*4882a593Smuzhiyun #define GPIO_FAN 0x004 79*4882a593Smuzhiyun #define GPIO_GREEN_LED 0x002 80*4882a593Smuzhiyun #define GPIO_RESET 0x001 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* CPLD pins */ 83*4882a593Smuzhiyun #define CPLD_DS_ENABLE 8 84*4882a593Smuzhiyun #define CPLD_7111_DISABLE 4 85*4882a593Smuzhiyun #define CPLD_UNMUTE 2 86*4882a593Smuzhiyun #define CPLD_FLASH_WR_ENABLE 1 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 89*4882a593Smuzhiyun extern raw_spinlock_t nw_gpio_lock; 90*4882a593Smuzhiyun extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); 91*4882a593Smuzhiyun extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); 92*4882a593Smuzhiyun extern unsigned int nw_gpio_read(void); 93*4882a593Smuzhiyun extern void nw_cpld_modify(unsigned int mask, unsigned int set); 94*4882a593Smuzhiyun #endif 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif 97