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/OK3568_Linux_fs/kernel/drivers/phy/qualcomm/
H A Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/OK3568_Linux_fs/kernel/drivers/ide/
H A Dide-generic.c24 module_param(probe_mask, int, 0);
33 static const u16 legacy_bases[] = { 0x1f0 };
36 static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168 };
39 static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
50 if (pci_resource_start(p, 0) == 0x1f0) in ide_generic_check_pci_legacy_iobases()
52 if (pci_resource_start(p, 2) == 0x170) in ide_generic_check_pci_legacy_iobases()
55 /* Cyrix CS55{1,2}0 pre SFF MWDMA ATA on the bridge */ in ide_generic_check_pci_legacy_iobases()
64 pci_read_config_word(p, 0x6C, &val); in ide_generic_check_pci_legacy_iobases()
65 if (val & 0x8000) { in ide_generic_check_pci_legacy_iobases()
67 if (val & 0x4000) in ide_generic_check_pci_legacy_iobases()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/marvell/mwifiex/
H A Dcfp.c40 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 };
42 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
43 0xb0, 0x48, 0x60, 0x6c, 0 };
45 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96,
46 0x0c, 0x12, 0x18, 0x24,
47 0x30, 0x48, 0x60, 0x6c, 0 };
49 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
50 0xb0, 0x48, 0x60, 0x6c, 0 };
51 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24,
52 0xb0, 0x48, 0x60, 0x6c, 0 };
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/ifpsp060/
H A Dfplsp.doc87 fmovm.x &0x01,-(%sp) # pass operand on stack
88 bsr.l _060FPLSP_TOP+0x1a8 # branch to fsin routine
89 add.l &0xc,%sp # clear operand from stack
100 bsr.l _060FPLSP_TOP+0x168 # branch to frem routine
101 addq.l &0x8,%sp # clear operands from stack
132 0x000: _060LSP__facoss_
133 0x008: _060LSP__facosd_
134 0x010: _060LSP__facosx_
135 0x018: _060LSP__fasins_
136 0x020: _060LSP__fasind_
[all …]
/OK3568_Linux_fs/kernel/drivers/video/rockchip/vehicle/
H A Dvehicle-csi2-dphy-common.h18 #define RK3562_GRF_VI_CON0 (0x0520)
19 #define RK3562_GRF_VI_CON1 (0x0524)
22 #define GRF_VI_CON0 (0x0340)
23 #define GRF_VI_CON1 (0x0344)
26 #define GRF_DPHY_CON0 (0x0)
27 #define GRF_SOC_CON2 (0x0308)
30 #define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
31 #define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0)
32 #define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0)
35 #define GRF_DCPHY_CON0 (0x0)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx6dl-pinfunc.h17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/OK3568_Linux_fs/kernel/drivers/tty/serial/8250/
H A D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/
H A Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/OK3568_Linux_fs/kernel/drivers/devfreq/event/
H A Dexynos-nocp.h13 NOCP_ID_REVISION_ID = 0x04,
14 NOCP_MAIN_CTL = 0x08,
15 NOCP_CFG_CTL = 0x0C,
17 NOCP_STAT_PERIOD = 0x24,
18 NOCP_STAT_GO = 0x28,
19 NOCP_STAT_ALARM_MIN = 0x2C,
20 NOCP_STAT_ALARM_MAX = 0x30,
21 NOCP_STAT_ALARM_STATUS = 0x34,
22 NOCP_STAT_ALARM_CLR = 0x38,
24 NOCP_COUNTERS_0_SRC = 0x138,
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/mtk-jpeg/
H A Dmtk_jpeg_enc_hw.h15 #define JPEG_ENC_INT_STATUS_DONE BIT(0)
16 #define JPEG_ENC_INT_STATUS_MASK_ALLIRQ 0x13
18 #define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
20 #define JPEG_ENC_CTRL_YUV_FORMAT_MASK 0x18
24 #define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
25 #define JPEG_ENC_RESET_BIT BIT(0)
27 #define JPEG_ENC_YUV_FORMAT_YUYV 0
32 #define JPEG_ENC_QUALITY_Q60 0x0
33 #define JPEG_ENC_QUALITY_Q80 0x1
34 #define JPEG_ENC_QUALITY_Q90 0x2
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/halmac/
H A Dhalmac_pcie_reg.h20 #define RAC_CTRL_PPR 0x00
21 #define RAC_SET_PPR 0x20
22 #define RAC_TRG_PPR 0x21
23 #define RAC_CTRL_PPR_V1 0x30
24 #define RAC_SET_PPR_V1 0x31
27 #define PCIE_L1SS_CTRL 0x718
28 #define PCIE_L1_CTRL 0x719
29 #define PCIE_ASPM_CTRL 0x70F
30 #define PCIE_CLK_CTRL 0x725
31 #define PCIE_L1SS_CAP 0x160
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/hal/halmac/
H A Dhalmac_pcie_reg.h20 #define RAC_CTRL_PPR 0x00
21 #define RAC_SET_PPR 0x20
22 #define RAC_TRG_PPR 0x21
23 #define RAC_CTRL_PPR_V1 0x30
24 #define RAC_SET_PPR_V1 0x31
27 #define PCIE_L1SS_CTRL 0x718
28 #define PCIE_L1_CTRL 0x719
29 #define PCIE_ASPM_CTRL 0x70F
30 #define PCIE_CLK_CTRL 0x725
31 #define PCIE_L1SS_CAP 0x160
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/hal/halmac/
H A Dhalmac_pcie_reg.h20 #define RAC_CTRL_PPR 0x00
21 #define RAC_SET_PPR 0x20
22 #define RAC_TRG_PPR 0x21
23 #define RAC_CTRL_PPR_V1 0x30
24 #define RAC_SET_PPR_V1 0x31
27 #define PCIE_L1SS_CTRL 0x718
28 #define PCIE_L1_CTRL 0x719
29 #define PCIE_ASPM_CTRL 0x70F
30 #define PCIE_CLK_CTRL 0x725
31 #define PCIE_L1SS_CAP 0x160
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/hal/halmac/
H A Dhalmac_pcie_reg.h21 #define RAC_CTRL_PPR 0x00
22 #define RAC_SET_PPR 0x20
23 #define RAC_TRG_PPR 0x21
24 #define RAC_CTRL_PPR_V1 0x30
25 #define RAC_SET_PPR_V1 0x31
28 #define PCIE_L1SS_CTRL 0x718
29 #define PCIE_L1_CTRL 0x719
30 #define PCIE_ASPM_CTRL 0x70F
31 #define PCIE_CLK_CTRL 0x725
32 #define PCIE_L1SS_CAP 0x160
[all …]
/OK3568_Linux_fs/kernel/include/linux/soc/mmp/
H A Dcputype.h12 * PXA168 S0 0x56158400 0x0000C910
13 * PXA168 A0 0x56158400 0x00A0A168
14 * PXA910 Y1 0x56158400 0x00F2C920
15 * PXA910 A0 0x56158400 0x00F2C910
16 * PXA910 A1 0x56158400 0x00A0C910
17 * PXA920 Y0 0x56158400 0x00F2C920
18 * PXA920 A0 0x56158400 0x00A0C920
19 * PXA920 A1 0x56158400 0x00A1C920
20 * MMP2 Z0 0x560f5811 0x00F00410
21 * MMP2 Z1 0x560f5811 0x00E00410
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-mmp/
H A Dregs-icu.h11 #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
14 #define ICU2_VIRT_BASE (AXI_VIRT_BASE + 0x84000)
18 #define ICU_INT_CONF_MASK (0xf)
25 #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26 #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
27 #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
28 #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29 #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
41 #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
42 #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
[all …]
/OK3568_Linux_fs/kernel/drivers/video/rockchip/rga/
H A Drga.h9 #define RGA_BLIT_SYNC 0x5017
10 #define RGA_BLIT_ASYNC 0x5018
11 #define RGA_FLUSH 0x5019
12 #define RGA_GET_RESULT 0x501a
13 #define RGA_GET_VERSION 0x501b
16 #define RGA_REG_CTRL_LEN 0x8 /* 8 */
17 #define RGA_REG_CMD_LEN 0x20 /* 32 */
18 #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */
23 #define RGA_BUF_GEM_TYPE_MASK 0xC0
25 #define rgaIS_ERROR(status) (status < 0)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/
H A Dpcie_reg.h21 #define RAC_CTRL_PPR 0x00
22 #define RAC_ANA10 0x10
23 #define RAC_ANA19 0x19
25 #define RAC_REG_REV2 0x1B
27 #define BAC_CMU_EN_DLY_MSK 0xF
29 #define RAC_REG_FLD_0 0x1D
31 #define BAC_AUTOK_N_MSK 0x3
33 #define RAC_ANA1F 0x1F
34 #define RAC_SET_PPR 0x20
35 #define RAC_TRG_PPR 0x21
[all …]

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