1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef QCOM_PHY_QMP_H_ 7*4882a593Smuzhiyun #define QCOM_PHY_QMP_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Only for QMP V2 PHY - QSERDES COM registers */ 10*4882a593Smuzhiyun #define QSERDES_COM_BG_TIMER 0x00c 11*4882a593Smuzhiyun #define QSERDES_COM_SSC_EN_CENTER 0x010 12*4882a593Smuzhiyun #define QSERDES_COM_SSC_ADJ_PER1 0x014 13*4882a593Smuzhiyun #define QSERDES_COM_SSC_ADJ_PER2 0x018 14*4882a593Smuzhiyun #define QSERDES_COM_SSC_PER1 0x01c 15*4882a593Smuzhiyun #define QSERDES_COM_SSC_PER2 0x020 16*4882a593Smuzhiyun #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17*4882a593Smuzhiyun #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18*4882a593Smuzhiyun #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19*4882a593Smuzhiyun #define QSERDES_COM_CLK_ENABLE1 0x038 20*4882a593Smuzhiyun #define QSERDES_COM_SYS_CLK_CTRL 0x03c 21*4882a593Smuzhiyun #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 22*4882a593Smuzhiyun #define QSERDES_COM_PLL_IVCO 0x048 23*4882a593Smuzhiyun #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 24*4882a593Smuzhiyun #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 25*4882a593Smuzhiyun #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 26*4882a593Smuzhiyun #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 27*4882a593Smuzhiyun #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 28*4882a593Smuzhiyun #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 29*4882a593Smuzhiyun #define QSERDES_COM_BG_TRIM 0x070 30*4882a593Smuzhiyun #define QSERDES_COM_CLK_EP_DIV 0x074 31*4882a593Smuzhiyun #define QSERDES_COM_CP_CTRL_MODE0 0x078 32*4882a593Smuzhiyun #define QSERDES_COM_CP_CTRL_MODE1 0x07c 33*4882a593Smuzhiyun #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 34*4882a593Smuzhiyun #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 35*4882a593Smuzhiyun #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 36*4882a593Smuzhiyun #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 37*4882a593Smuzhiyun #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 38*4882a593Smuzhiyun #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 39*4882a593Smuzhiyun #define QSERDES_COM_RESETSM_CNTRL 0x0b4 40*4882a593Smuzhiyun #define QSERDES_COM_RESTRIM_CTRL 0x0bc 41*4882a593Smuzhiyun #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 42*4882a593Smuzhiyun #define QSERDES_COM_LOCK_CMP_EN 0x0c8 43*4882a593Smuzhiyun #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 44*4882a593Smuzhiyun #define QSERDES_COM_DEC_START_MODE0 0x0d0 45*4882a593Smuzhiyun #define QSERDES_COM_DEC_START_MODE1 0x0d4 46*4882a593Smuzhiyun #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 47*4882a593Smuzhiyun #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 48*4882a593Smuzhiyun #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 49*4882a593Smuzhiyun #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 50*4882a593Smuzhiyun #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 51*4882a593Smuzhiyun #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 52*4882a593Smuzhiyun #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 53*4882a593Smuzhiyun #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 54*4882a593Smuzhiyun #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 55*4882a593Smuzhiyun #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 56*4882a593Smuzhiyun #define QSERDES_COM_VCO_TUNE_CTRL 0x124 57*4882a593Smuzhiyun #define QSERDES_COM_VCO_TUNE_MAP 0x128 58*4882a593Smuzhiyun #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 59*4882a593Smuzhiyun #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 60*4882a593Smuzhiyun #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 61*4882a593Smuzhiyun #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 62*4882a593Smuzhiyun #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 63*4882a593Smuzhiyun #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 64*4882a593Smuzhiyun #define QSERDES_COM_BG_CTRL 0x170 65*4882a593Smuzhiyun #define QSERDES_COM_CLK_SELECT 0x174 66*4882a593Smuzhiyun #define QSERDES_COM_HSCLK_SEL 0x178 67*4882a593Smuzhiyun #define QSERDES_COM_CORECLK_DIV 0x184 68*4882a593Smuzhiyun #define QSERDES_COM_CORE_CLK_EN 0x18c 69*4882a593Smuzhiyun #define QSERDES_COM_C_READY_STATUS 0x190 70*4882a593Smuzhiyun #define QSERDES_COM_CMN_CONFIG 0x194 71*4882a593Smuzhiyun #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 72*4882a593Smuzhiyun #define QSERDES_COM_DEBUG_BUS0 0x1a0 73*4882a593Smuzhiyun #define QSERDES_COM_DEBUG_BUS1 0x1a4 74*4882a593Smuzhiyun #define QSERDES_COM_DEBUG_BUS2 0x1a8 75*4882a593Smuzhiyun #define QSERDES_COM_DEBUG_BUS3 0x1ac 76*4882a593Smuzhiyun #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 77*4882a593Smuzhiyun #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Only for QMP V2 PHY - TX registers */ 80*4882a593Smuzhiyun #define QSERDES_TX_EMP_POST1_LVL 0x018 81*4882a593Smuzhiyun #define QSERDES_TX_SLEW_CNTL 0x040 82*4882a593Smuzhiyun #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 83*4882a593Smuzhiyun #define QSERDES_TX_DEBUG_BUS_SEL 0x064 84*4882a593Smuzhiyun #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 85*4882a593Smuzhiyun #define QSERDES_TX_LANE_MODE 0x094 86*4882a593Smuzhiyun #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Only for QMP V2 PHY - RX registers */ 89*4882a593Smuzhiyun #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 90*4882a593Smuzhiyun #define QSERDES_RX_UCDR_SO_GAIN 0x01c 91*4882a593Smuzhiyun #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 92*4882a593Smuzhiyun #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 93*4882a593Smuzhiyun #define QSERDES_RX_RX_TERM_BW 0x090 94*4882a593Smuzhiyun #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 95*4882a593Smuzhiyun #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 96*4882a593Smuzhiyun #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 97*4882a593Smuzhiyun #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 98*4882a593Smuzhiyun #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 99*4882a593Smuzhiyun #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 100*4882a593Smuzhiyun #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 101*4882a593Smuzhiyun #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 102*4882a593Smuzhiyun #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 103*4882a593Smuzhiyun #define QSERDES_RX_SIGDET_ENABLES 0x110 104*4882a593Smuzhiyun #define QSERDES_RX_SIGDET_CNTRL 0x114 105*4882a593Smuzhiyun #define QSERDES_RX_SIGDET_LVL 0x118 106*4882a593Smuzhiyun #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 107*4882a593Smuzhiyun #define QSERDES_RX_RX_BAND 0x120 108*4882a593Smuzhiyun #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Only for QMP V2 PHY - PCS registers */ 111*4882a593Smuzhiyun #define QPHY_POWER_DOWN_CONTROL 0x04 112*4882a593Smuzhiyun #define QPHY_TXDEEMPH_M6DB_V0 0x24 113*4882a593Smuzhiyun #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 114*4882a593Smuzhiyun #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 115*4882a593Smuzhiyun #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 116*4882a593Smuzhiyun #define QPHY_POWER_STATE_CONFIG1 0x60 117*4882a593Smuzhiyun #define QPHY_POWER_STATE_CONFIG2 0x64 118*4882a593Smuzhiyun #define QPHY_POWER_STATE_CONFIG4 0x6c 119*4882a593Smuzhiyun #define QPHY_LOCK_DETECT_CONFIG1 0x80 120*4882a593Smuzhiyun #define QPHY_LOCK_DETECT_CONFIG2 0x84 121*4882a593Smuzhiyun #define QPHY_LOCK_DETECT_CONFIG3 0x88 122*4882a593Smuzhiyun #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 123*4882a593Smuzhiyun #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 124*4882a593Smuzhiyun #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 125*4882a593Smuzhiyun #define QPHY_OSC_DTCT_ACTIONS 0x1AC 126*4882a593Smuzhiyun #define QPHY_RX_SIGDET_LVL 0x1D8 127*4882a593Smuzhiyun #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 128*4882a593Smuzhiyun #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* Only for QMP V3 & V4 PHY - DP COM registers */ 131*4882a593Smuzhiyun #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 132*4882a593Smuzhiyun #define QPHY_V3_DP_COM_SW_RESET 0x04 133*4882a593Smuzhiyun #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 134*4882a593Smuzhiyun #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 135*4882a593Smuzhiyun #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 136*4882a593Smuzhiyun #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 137*4882a593Smuzhiyun #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* Only for QMP V3 PHY - QSERDES COM registers */ 140*4882a593Smuzhiyun #define QSERDES_V3_COM_ATB_SEL1 0x000 141*4882a593Smuzhiyun #define QSERDES_V3_COM_ATB_SEL2 0x004 142*4882a593Smuzhiyun #define QSERDES_V3_COM_FREQ_UPDATE 0x008 143*4882a593Smuzhiyun #define QSERDES_V3_COM_BG_TIMER 0x00c 144*4882a593Smuzhiyun #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 145*4882a593Smuzhiyun #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 146*4882a593Smuzhiyun #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 147*4882a593Smuzhiyun #define QSERDES_V3_COM_SSC_PER1 0x01c 148*4882a593Smuzhiyun #define QSERDES_V3_COM_SSC_PER2 0x020 149*4882a593Smuzhiyun #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 150*4882a593Smuzhiyun #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 151*4882a593Smuzhiyun #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 152*4882a593Smuzhiyun # define QSERDES_V3_COM_BIAS_EN 0x0001 153*4882a593Smuzhiyun # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 154*4882a593Smuzhiyun # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 155*4882a593Smuzhiyun # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 156*4882a593Smuzhiyun # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 157*4882a593Smuzhiyun # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 158*4882a593Smuzhiyun # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 159*4882a593Smuzhiyun #define QSERDES_V3_COM_CLK_ENABLE1 0x038 160*4882a593Smuzhiyun #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 161*4882a593Smuzhiyun #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 162*4882a593Smuzhiyun #define QSERDES_V3_COM_PLL_IVCO 0x048 163*4882a593Smuzhiyun #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 164*4882a593Smuzhiyun #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 165*4882a593Smuzhiyun #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 166*4882a593Smuzhiyun #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 167*4882a593Smuzhiyun #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 168*4882a593Smuzhiyun #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 169*4882a593Smuzhiyun #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 170*4882a593Smuzhiyun #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 171*4882a593Smuzhiyun #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 172*4882a593Smuzhiyun #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 173*4882a593Smuzhiyun #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 174*4882a593Smuzhiyun #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 175*4882a593Smuzhiyun #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 176*4882a593Smuzhiyun #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 177*4882a593Smuzhiyun #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 178*4882a593Smuzhiyun #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 179*4882a593Smuzhiyun #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 180*4882a593Smuzhiyun #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 181*4882a593Smuzhiyun #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 182*4882a593Smuzhiyun #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 183*4882a593Smuzhiyun #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 184*4882a593Smuzhiyun #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 185*4882a593Smuzhiyun #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 186*4882a593Smuzhiyun #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 187*4882a593Smuzhiyun #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 188*4882a593Smuzhiyun #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 189*4882a593Smuzhiyun #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 190*4882a593Smuzhiyun #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 191*4882a593Smuzhiyun #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 192*4882a593Smuzhiyun #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 193*4882a593Smuzhiyun #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 194*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 195*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 196*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 197*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 198*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 199*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 200*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 201*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 202*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 203*4882a593Smuzhiyun #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 204*4882a593Smuzhiyun #define QSERDES_V3_COM_CLK_SELECT 0x138 205*4882a593Smuzhiyun #define QSERDES_V3_COM_HSCLK_SEL 0x13c 206*4882a593Smuzhiyun #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 207*4882a593Smuzhiyun #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 208*4882a593Smuzhiyun #define QSERDES_V3_COM_CORE_CLK_EN 0x154 209*4882a593Smuzhiyun #define QSERDES_V3_COM_C_READY_STATUS 0x158 210*4882a593Smuzhiyun #define QSERDES_V3_COM_CMN_CONFIG 0x15c 211*4882a593Smuzhiyun #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 212*4882a593Smuzhiyun #define QSERDES_V3_COM_DEBUG_BUS0 0x168 213*4882a593Smuzhiyun #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 214*4882a593Smuzhiyun #define QSERDES_V3_COM_DEBUG_BUS2 0x170 215*4882a593Smuzhiyun #define QSERDES_V3_COM_DEBUG_BUS3 0x174 216*4882a593Smuzhiyun #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 217*4882a593Smuzhiyun #define QSERDES_V3_COM_CMN_MODE 0x184 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* Only for QMP V3 PHY - TX registers */ 220*4882a593Smuzhiyun #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 221*4882a593Smuzhiyun #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 222*4882a593Smuzhiyun #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 223*4882a593Smuzhiyun # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 224*4882a593Smuzhiyun # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 227*4882a593Smuzhiyun # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 228*4882a593Smuzhiyun # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 231*4882a593Smuzhiyun #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun #define QSERDES_V3_TX_TX_BAND 0x02c 234*4882a593Smuzhiyun #define QSERDES_V3_TX_SLEW_CNTL 0x030 235*4882a593Smuzhiyun #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 236*4882a593Smuzhiyun #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 237*4882a593Smuzhiyun #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 238*4882a593Smuzhiyun #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 239*4882a593Smuzhiyun #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 240*4882a593Smuzhiyun #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 241*4882a593Smuzhiyun #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 242*4882a593Smuzhiyun #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 243*4882a593Smuzhiyun #define QSERDES_V3_TX_TX_POL_INV 0x064 244*4882a593Smuzhiyun #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 245*4882a593Smuzhiyun #define QSERDES_V3_TX_LANE_MODE_1 0x08c 246*4882a593Smuzhiyun #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 247*4882a593Smuzhiyun #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 248*4882a593Smuzhiyun #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 249*4882a593Smuzhiyun #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* Only for QMP V3 PHY - RX registers */ 252*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 253*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 254*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 255*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 256*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 257*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 258*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 259*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 260*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 261*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 262*4882a593Smuzhiyun #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 263*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_TERM_BW 0x07c 264*4882a593Smuzhiyun #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 265*4882a593Smuzhiyun #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 266*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 267*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 268*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 269*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 270*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 271*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 272*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 273*4882a593Smuzhiyun #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 274*4882a593Smuzhiyun #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 275*4882a593Smuzhiyun #define QSERDES_V3_RX_SIGDET_LVL 0x108 276*4882a593Smuzhiyun #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 277*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_BAND 0x110 278*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 279*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_MODE_00 0x164 280*4882a593Smuzhiyun #define QSERDES_V3_RX_RX_MODE_01 0x168 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun /* Only for QMP V3 PHY - PCS registers */ 283*4882a593Smuzhiyun #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 284*4882a593Smuzhiyun #define QPHY_V3_PCS_TXMGN_V0 0x00c 285*4882a593Smuzhiyun #define QPHY_V3_PCS_TXMGN_V1 0x010 286*4882a593Smuzhiyun #define QPHY_V3_PCS_TXMGN_V2 0x014 287*4882a593Smuzhiyun #define QPHY_V3_PCS_TXMGN_V3 0x018 288*4882a593Smuzhiyun #define QPHY_V3_PCS_TXMGN_V4 0x01c 289*4882a593Smuzhiyun #define QPHY_V3_PCS_TXMGN_LS 0x020 290*4882a593Smuzhiyun #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 291*4882a593Smuzhiyun #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 292*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 293*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 294*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 295*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 296*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 297*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 298*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 299*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 300*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 301*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 302*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 303*4882a593Smuzhiyun #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 304*4882a593Smuzhiyun #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 305*4882a593Smuzhiyun #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 306*4882a593Smuzhiyun #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 307*4882a593Smuzhiyun #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 308*4882a593Smuzhiyun #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 309*4882a593Smuzhiyun #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 310*4882a593Smuzhiyun #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 311*4882a593Smuzhiyun #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 312*4882a593Smuzhiyun #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 313*4882a593Smuzhiyun #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 314*4882a593Smuzhiyun #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 315*4882a593Smuzhiyun #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 316*4882a593Smuzhiyun #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 317*4882a593Smuzhiyun #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 318*4882a593Smuzhiyun #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 319*4882a593Smuzhiyun #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 320*4882a593Smuzhiyun #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 321*4882a593Smuzhiyun #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 322*4882a593Smuzhiyun #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 323*4882a593Smuzhiyun #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 324*4882a593Smuzhiyun #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 325*4882a593Smuzhiyun #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 326*4882a593Smuzhiyun #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 327*4882a593Smuzhiyun #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 328*4882a593Smuzhiyun #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 329*4882a593Smuzhiyun #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 330*4882a593Smuzhiyun #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 331*4882a593Smuzhiyun #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 332*4882a593Smuzhiyun #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 333*4882a593Smuzhiyun #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 334*4882a593Smuzhiyun #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 335*4882a593Smuzhiyun #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 336*4882a593Smuzhiyun #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 337*4882a593Smuzhiyun #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 338*4882a593Smuzhiyun #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 339*4882a593Smuzhiyun #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 340*4882a593Smuzhiyun #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 341*4882a593Smuzhiyun #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 342*4882a593Smuzhiyun #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /* Only for QMP V3 PHY - PCS_MISC registers */ 345*4882a593Smuzhiyun #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 346*4882a593Smuzhiyun #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 347*4882a593Smuzhiyun #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 348*4882a593Smuzhiyun #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 349*4882a593Smuzhiyun #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 350*4882a593Smuzhiyun #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun /* Only for QMP V3 PHY - DP PHY registers */ 353*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_REVISION_ID0 0x000 354*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_REVISION_ID1 0x004 355*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_REVISION_ID2 0x008 356*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_REVISION_ID3 0x00c 357*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_CFG 0x010 358*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_PD_CTL 0x018 359*4882a593Smuzhiyun # define DP_PHY_PD_CTL_PWRDN 0x001 360*4882a593Smuzhiyun # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 361*4882a593Smuzhiyun # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 362*4882a593Smuzhiyun # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 363*4882a593Smuzhiyun # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 364*4882a593Smuzhiyun # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 365*4882a593Smuzhiyun # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 366*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_MODE 0x01c 367*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG0 0x020 368*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG1 0x024 369*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG2 0x028 370*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG3 0x02c 371*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG4 0x030 372*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG5 0x034 373*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG6 0x038 374*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG7 0x03c 375*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG8 0x040 376*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_CFG9 0x044 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 379*4882a593Smuzhiyun # define PHY_AUX_STOP_ERR_MASK 0x01 380*4882a593Smuzhiyun # define PHY_AUX_DEC_ERR_MASK 0x02 381*4882a593Smuzhiyun # define PHY_AUX_SYNC_ERR_MASK 0x04 382*4882a593Smuzhiyun # define PHY_AUX_ALIGN_ERR_MASK 0x08 383*4882a593Smuzhiyun # define PHY_AUX_REQ_ERR_MASK 0x10 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 386*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 389*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 390*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 393*4882a593Smuzhiyun #define DP_PHY_SPARE0_MASK 0x0f 394*4882a593Smuzhiyun #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun #define QSERDES_V3_DP_PHY_STATUS 0x0c0 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun /* Only for QMP V4 PHY - QSERDES COM registers */ 399*4882a593Smuzhiyun #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 400*4882a593Smuzhiyun #define QSERDES_V4_COM_SSC_PER1 0x01c 401*4882a593Smuzhiyun #define QSERDES_V4_COM_SSC_PER2 0x020 402*4882a593Smuzhiyun #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 403*4882a593Smuzhiyun #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 404*4882a593Smuzhiyun #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 405*4882a593Smuzhiyun #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 406*4882a593Smuzhiyun #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 407*4882a593Smuzhiyun #define QSERDES_V4_COM_PLL_IVCO 0x058 408*4882a593Smuzhiyun #define QSERDES_V4_COM_CMN_IPTRIM 0x060 409*4882a593Smuzhiyun #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 410*4882a593Smuzhiyun #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 411*4882a593Smuzhiyun #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 412*4882a593Smuzhiyun #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 413*4882a593Smuzhiyun #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 414*4882a593Smuzhiyun #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 415*4882a593Smuzhiyun #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 416*4882a593Smuzhiyun #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 417*4882a593Smuzhiyun #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 418*4882a593Smuzhiyun #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 419*4882a593Smuzhiyun #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 420*4882a593Smuzhiyun #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 421*4882a593Smuzhiyun #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 422*4882a593Smuzhiyun #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 423*4882a593Smuzhiyun #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 424*4882a593Smuzhiyun #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 425*4882a593Smuzhiyun #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 426*4882a593Smuzhiyun #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 427*4882a593Smuzhiyun #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 428*4882a593Smuzhiyun #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 429*4882a593Smuzhiyun #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 430*4882a593Smuzhiyun #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 431*4882a593Smuzhiyun #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 432*4882a593Smuzhiyun #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 433*4882a593Smuzhiyun #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 434*4882a593Smuzhiyun #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 435*4882a593Smuzhiyun #define QSERDES_V4_COM_HSCLK_SEL 0x158 436*4882a593Smuzhiyun #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 437*4882a593Smuzhiyun #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 438*4882a593Smuzhiyun #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 439*4882a593Smuzhiyun #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 440*4882a593Smuzhiyun #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 441*4882a593Smuzhiyun #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 442*4882a593Smuzhiyun #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 443*4882a593Smuzhiyun #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun /* Only for QMP V4 PHY - TX registers */ 446*4882a593Smuzhiyun #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 447*4882a593Smuzhiyun #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 448*4882a593Smuzhiyun #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 449*4882a593Smuzhiyun #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 450*4882a593Smuzhiyun #define QSERDES_V4_TX_LANE_MODE_1 0x84 451*4882a593Smuzhiyun #define QSERDES_V4_TX_LANE_MODE_2 0x88 452*4882a593Smuzhiyun #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 453*4882a593Smuzhiyun #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 454*4882a593Smuzhiyun #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 455*4882a593Smuzhiyun #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 456*4882a593Smuzhiyun #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 457*4882a593Smuzhiyun #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 458*4882a593Smuzhiyun #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun /* Only for QMP V4 PHY - RX registers */ 461*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 462*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 463*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 464*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 465*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 466*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 467*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 468*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 469*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 470*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 471*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 472*4882a593Smuzhiyun #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 473*4882a593Smuzhiyun #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 474*4882a593Smuzhiyun #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 475*4882a593Smuzhiyun #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 476*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_TERM_BW 0x080 477*4882a593Smuzhiyun #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 478*4882a593Smuzhiyun #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 479*4882a593Smuzhiyun #define QSERDES_V4_RX_GM_CAL 0x0dc 480*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 481*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 482*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 483*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 484*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 485*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 486*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 487*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 488*4882a593Smuzhiyun #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 489*4882a593Smuzhiyun #define QSERDES_V4_RX_SIGDET_LVL 0x120 490*4882a593Smuzhiyun #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 491*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_BAND 0x128 492*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 493*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 494*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 495*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 496*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 497*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 498*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 499*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 500*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 501*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 502*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 503*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 504*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 505*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 506*4882a593Smuzhiyun #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 507*4882a593Smuzhiyun #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 508*4882a593Smuzhiyun #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 509*4882a593Smuzhiyun #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 510*4882a593Smuzhiyun #define QSERDES_V4_RX_VTH_CODE 0x1c4 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun /* Only for QMP V4 PHY - UFS PCS registers */ 513*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_PHY_START 0x000 514*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 515*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_SW_RESET 0x008 516*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 517*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 518*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 519*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 520*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 521*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 522*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 523*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 524*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 525*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 526*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 527*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 528*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 529*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 530*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 531*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 532*4882a593Smuzhiyun #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun /* PCIE GEN3 COM registers */ 535*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 536*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 537*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 538*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 539*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 540*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 541*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 542*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 543*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 544*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 545*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 546*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 547*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 548*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 549*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 550*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 551*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 552*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 553*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 554*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 555*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 556*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 557*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 558*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 559*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 560*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 561*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 562*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 563*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 564*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 565*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 566*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 567*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 568*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 569*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 570*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 571*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 572*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 573*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 574*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 575*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 576*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 577*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 578*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 579*4882a593Smuzhiyun #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun /* PCIE GEN3 QHP Lane registers */ 582*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 583*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 584*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 585*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 586*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 587*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 588*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 589*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 590*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 591*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 592*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 593*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 594*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 595*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 596*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 597*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 598*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 599*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 600*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 601*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 602*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 603*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 604*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 605*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 606*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 607*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 608*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 609*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 610*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 611*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 612*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 613*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 614*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 615*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 616*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 617*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 618*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 619*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 620*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 621*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 622*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 623*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 624*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 625*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 626*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 627*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 628*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 629*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 630*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 631*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 632*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 633*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 634*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 635*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 636*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 637*4882a593Smuzhiyun #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun /* PCIE GEN3 PCS registers */ 640*4882a593Smuzhiyun #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 641*4882a593Smuzhiyun #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 642*4882a593Smuzhiyun #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 643*4882a593Smuzhiyun #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 644*4882a593Smuzhiyun #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 645*4882a593Smuzhiyun #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 646*4882a593Smuzhiyun #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 649*4882a593Smuzhiyun #define QPHY_V4_PCS_SW_RESET 0x000 650*4882a593Smuzhiyun #define QPHY_V4_PCS_REVISION_ID0 0x004 651*4882a593Smuzhiyun #define QPHY_V4_PCS_REVISION_ID1 0x008 652*4882a593Smuzhiyun #define QPHY_V4_PCS_REVISION_ID2 0x00c 653*4882a593Smuzhiyun #define QPHY_V4_PCS_REVISION_ID3 0x010 654*4882a593Smuzhiyun #define QPHY_V4_PCS_PCS_STATUS1 0x014 655*4882a593Smuzhiyun #define QPHY_V4_PCS_PCS_STATUS2 0x018 656*4882a593Smuzhiyun #define QPHY_V4_PCS_PCS_STATUS3 0x01c 657*4882a593Smuzhiyun #define QPHY_V4_PCS_PCS_STATUS4 0x020 658*4882a593Smuzhiyun #define QPHY_V4_PCS_PCS_STATUS5 0x024 659*4882a593Smuzhiyun #define QPHY_V4_PCS_PCS_STATUS6 0x028 660*4882a593Smuzhiyun #define QPHY_V4_PCS_PCS_STATUS7 0x02c 661*4882a593Smuzhiyun #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 662*4882a593Smuzhiyun #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 663*4882a593Smuzhiyun #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 664*4882a593Smuzhiyun #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 665*4882a593Smuzhiyun #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 666*4882a593Smuzhiyun #define QPHY_V4_PCS_START_CONTROL 0x044 667*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 668*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 669*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 670*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 671*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 672*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 673*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 674*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 675*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 676*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 677*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 678*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 679*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 680*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 681*4882a593Smuzhiyun #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 682*4882a593Smuzhiyun #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 683*4882a593Smuzhiyun #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 684*4882a593Smuzhiyun #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 685*4882a593Smuzhiyun #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 686*4882a593Smuzhiyun #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 687*4882a593Smuzhiyun #define QPHY_V4_PCS_FLL_CNTRL1 0x098 688*4882a593Smuzhiyun #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 689*4882a593Smuzhiyun #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 690*4882a593Smuzhiyun #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 691*4882a593Smuzhiyun #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 692*4882a593Smuzhiyun #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 693*4882a593Smuzhiyun #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 694*4882a593Smuzhiyun #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 695*4882a593Smuzhiyun #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 696*4882a593Smuzhiyun #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 697*4882a593Smuzhiyun #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 698*4882a593Smuzhiyun #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 699*4882a593Smuzhiyun #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 700*4882a593Smuzhiyun #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 701*4882a593Smuzhiyun #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 702*4882a593Smuzhiyun #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 703*4882a593Smuzhiyun #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 704*4882a593Smuzhiyun #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 705*4882a593Smuzhiyun #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 706*4882a593Smuzhiyun #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 707*4882a593Smuzhiyun #define QPHY_V4_PCS_BIST_CTRL 0x0e8 708*4882a593Smuzhiyun #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 709*4882a593Smuzhiyun #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 710*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 711*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 712*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 713*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT3 0x100 714*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT4 0x104 715*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT5 0x108 716*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT6 0x10c 717*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT7 0x110 718*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT8 0x114 719*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT9 0x118 720*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT10 0x11c 721*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT11 0x120 722*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT12 0x124 723*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT13 0x128 724*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT14 0x12c 725*4882a593Smuzhiyun #define QPHY_V4_PCS_FIXED_PAT15 0x130 726*4882a593Smuzhiyun #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 727*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 728*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 729*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 730*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 731*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 732*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 733*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 734*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 735*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 736*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 737*4882a593Smuzhiyun #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 738*4882a593Smuzhiyun #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 739*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 740*4882a593Smuzhiyun #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 741*4882a593Smuzhiyun #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 742*4882a593Smuzhiyun #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 743*4882a593Smuzhiyun #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 744*4882a593Smuzhiyun #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 745*4882a593Smuzhiyun #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 746*4882a593Smuzhiyun #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 747*4882a593Smuzhiyun #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 748*4882a593Smuzhiyun #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 749*4882a593Smuzhiyun #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 750*4882a593Smuzhiyun #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 751*4882a593Smuzhiyun #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 752*4882a593Smuzhiyun #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 753*4882a593Smuzhiyun #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 754*4882a593Smuzhiyun #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 755*4882a593Smuzhiyun #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 756*4882a593Smuzhiyun #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 757*4882a593Smuzhiyun #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 758*4882a593Smuzhiyun #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 759*4882a593Smuzhiyun #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 760*4882a593Smuzhiyun #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 761*4882a593Smuzhiyun #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 762*4882a593Smuzhiyun #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 763*4882a593Smuzhiyun #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 764*4882a593Smuzhiyun #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 765*4882a593Smuzhiyun #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 766*4882a593Smuzhiyun #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 767*4882a593Smuzhiyun #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 768*4882a593Smuzhiyun #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 769*4882a593Smuzhiyun #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 770*4882a593Smuzhiyun #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 771*4882a593Smuzhiyun #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 772*4882a593Smuzhiyun #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 773*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 774*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 775*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 776*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 777*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 778*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 779*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 780*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 781*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 782*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 783*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 784*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 785*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 786*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 787*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 788*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 789*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 790*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 791*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 792*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 793*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 794*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 795*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 796*4882a593Smuzhiyun 797*4882a593Smuzhiyun /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 798*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 799*4882a593Smuzhiyun #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 800*4882a593Smuzhiyun 801*4882a593Smuzhiyun /* Only for QMP V4 PHY - PCS_MISC registers */ 802*4882a593Smuzhiyun #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 803*4882a593Smuzhiyun #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 804*4882a593Smuzhiyun #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 805*4882a593Smuzhiyun #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 806*4882a593Smuzhiyun #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 807*4882a593Smuzhiyun #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun #endif 810