1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * TI DaVinci clock definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2006-2007 Texas Instruments. 6*4882a593Smuzhiyun * Copyright (C) 2008-2009 Deep Root Systems, LLC 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ARCH_ARM_DAVINCI_CLOCK_H 10*4882a593Smuzhiyun #define __ARCH_ARM_DAVINCI_CLOCK_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* PLL/Reset register offsets */ 13*4882a593Smuzhiyun #define PLLCTL 0x100 14*4882a593Smuzhiyun #define PLLCTL_PLLEN BIT(0) 15*4882a593Smuzhiyun #define PLLCTL_PLLPWRDN BIT(1) 16*4882a593Smuzhiyun #define PLLCTL_PLLRST BIT(3) 17*4882a593Smuzhiyun #define PLLCTL_PLLDIS BIT(4) 18*4882a593Smuzhiyun #define PLLCTL_PLLENSRC BIT(5) 19*4882a593Smuzhiyun #define PLLCTL_CLKMODE BIT(8) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define PLLM 0x110 22*4882a593Smuzhiyun #define PLLM_PLLM_MASK 0xff 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PREDIV 0x114 25*4882a593Smuzhiyun #define PLLDIV1 0x118 26*4882a593Smuzhiyun #define PLLDIV2 0x11c 27*4882a593Smuzhiyun #define PLLDIV3 0x120 28*4882a593Smuzhiyun #define POSTDIV 0x128 29*4882a593Smuzhiyun #define BPDIV 0x12c 30*4882a593Smuzhiyun #define PLLCMD 0x138 31*4882a593Smuzhiyun #define PLLSTAT 0x13c 32*4882a593Smuzhiyun #define PLLALNCTL 0x140 33*4882a593Smuzhiyun #define PLLDCHANGE 0x144 34*4882a593Smuzhiyun #define PLLCKEN 0x148 35*4882a593Smuzhiyun #define PLLCKSTAT 0x14c 36*4882a593Smuzhiyun #define PLLSYSTAT 0x150 37*4882a593Smuzhiyun #define PLLDIV4 0x160 38*4882a593Smuzhiyun #define PLLDIV5 0x164 39*4882a593Smuzhiyun #define PLLDIV6 0x168 40*4882a593Smuzhiyun #define PLLDIV7 0x16c 41*4882a593Smuzhiyun #define PLLDIV8 0x170 42*4882a593Smuzhiyun #define PLLDIV9 0x174 43*4882a593Smuzhiyun #define PLLDIV_EN BIT(15) 44*4882a593Smuzhiyun #define PLLDIV_RATIO_MASK 0x1f 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN 48*4882a593Smuzhiyun * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us 49*4882a593Smuzhiyun * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input 50*4882a593Smuzhiyun * is ~25MHz. Units are micro seconds. 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define PLL_BYPASS_TIME 1 53*4882a593Smuzhiyun /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ 54*4882a593Smuzhiyun #define PLL_RESET_TIME 1 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 57*4882a593Smuzhiyun * Units are micro seconds. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define PLL_LOCK_TIME 20 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62