1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Interrupt Control Unit 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ASM_MACH_ICU_H 7*4882a593Smuzhiyun #define __ASM_MACH_ICU_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "addr-map.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000) 12*4882a593Smuzhiyun #define ICU_REG(x) (ICU_VIRT_BASE + (x)) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define ICU2_VIRT_BASE (AXI_VIRT_BASE + 0x84000) 15*4882a593Smuzhiyun #define ICU2_REG(x) (ICU2_VIRT_BASE + (x)) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define ICU_INT_CONF(n) ICU_REG((n) << 2) 18*4882a593Smuzhiyun #define ICU_INT_CONF_MASK (0xf) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /************ PXA168/PXA910 (MMP) *********************/ 21*4882a593Smuzhiyun #define ICU_INT_CONF_AP_INT (1 << 6) 22*4882a593Smuzhiyun #define ICU_INT_CONF_CP_INT (1 << 5) 23*4882a593Smuzhiyun #define ICU_INT_CONF_IRQ (1 << 4) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ 26*4882a593Smuzhiyun #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ 27*4882a593Smuzhiyun #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */ 28*4882a593Smuzhiyun #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ 29*4882a593Smuzhiyun #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /************************** MMP2 ***********************/ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * IRQ0/FIQ0 is routed to SP IRQ/FIQ. 35*4882a593Smuzhiyun * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define ICU_INT_ROUTE_SP_IRQ (1 << 4) 38*4882a593Smuzhiyun #define ICU_INT_ROUTE_PJ4_IRQ (1 << 5) 39*4882a593Smuzhiyun #define ICU_INT_ROUTE_PJ4_FIQ (1 << 6) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138) 42*4882a593Smuzhiyun #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c) 43*4882a593Smuzhiyun #define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140) 44*4882a593Smuzhiyun #define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define MMP2_ICU_INT4_STATUS ICU_REG(0x150) 47*4882a593Smuzhiyun #define MMP2_ICU_INT5_STATUS ICU_REG(0x154) 48*4882a593Smuzhiyun #define MMP2_ICU_INT17_STATUS ICU_REG(0x158) 49*4882a593Smuzhiyun #define MMP2_ICU_INT35_STATUS ICU_REG(0x15c) 50*4882a593Smuzhiyun #define MMP2_ICU_INT51_STATUS ICU_REG(0x160) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MMP2_ICU_INT4_MASK ICU_REG(0x168) 53*4882a593Smuzhiyun #define MMP2_ICU_INT5_MASK ICU_REG(0x16C) 54*4882a593Smuzhiyun #define MMP2_ICU_INT17_MASK ICU_REG(0x170) 55*4882a593Smuzhiyun #define MMP2_ICU_INT35_MASK ICU_REG(0x174) 56*4882a593Smuzhiyun #define MMP2_ICU_INT51_MASK ICU_REG(0x178) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100) 59*4882a593Smuzhiyun #define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104) 60*4882a593Smuzhiyun #define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define MMP2_ICU_INVERT ICU_REG(0x164) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define MMP2_ICU_INV_PMIC (1 << 0) 65*4882a593Smuzhiyun #define MMP2_ICU_INV_PERF (1 << 1) 66*4882a593Smuzhiyun #define MMP2_ICU_INV_COMMTX (1 << 2) 67*4882a593Smuzhiyun #define MMP2_ICU_INV_COMMRX (1 << 3) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* __ASM_MACH_ICU_H */ 70