1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Texas Instruments, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLK_DM814_H 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLK_DM814_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define DM814_CLKCTRL_OFFSET 0x0 9*4882a593Smuzhiyun #define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* default clocks */ 12*4882a593Smuzhiyun #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* alwon clocks */ 15*4882a593Smuzhiyun #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) 16*4882a593Smuzhiyun #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) 17*4882a593Smuzhiyun #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) 18*4882a593Smuzhiyun #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) 19*4882a593Smuzhiyun #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) 20*4882a593Smuzhiyun #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) 21*4882a593Smuzhiyun #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) 22*4882a593Smuzhiyun #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) 23*4882a593Smuzhiyun #define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190) 24*4882a593Smuzhiyun #define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0) 25*4882a593Smuzhiyun #define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4) 26*4882a593Smuzhiyun #define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc) 27*4882a593Smuzhiyun #define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0) 28*4882a593Smuzhiyun #define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4) 29*4882a593Smuzhiyun #define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8) 30*4882a593Smuzhiyun #define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc) 31*4882a593Smuzhiyun #define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200) 32*4882a593Smuzhiyun #define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204) 33*4882a593Smuzhiyun #define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c) 34*4882a593Smuzhiyun #define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220) 35*4882a593Smuzhiyun #define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* alwon_ethernet clocks */ 38*4882a593Smuzhiyun #define DM814_ETHERNET_CLKCTRL_OFFSET 0x1d4 39*4882a593Smuzhiyun #define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET) 40*4882a593Smuzhiyun #define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif 43