1 /****************************************************************************** 2 * 3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 #ifndef __HALMAC_PCIE_REG_H__ 17 #define __HALMAC_PCIE_REG_H__ 18 19 /* PCIE PHY register */ 20 #define RAC_CTRL_PPR 0x00 21 #define RAC_SET_PPR 0x20 22 #define RAC_TRG_PPR 0x21 23 #define RAC_CTRL_PPR_V1 0x30 24 #define RAC_SET_PPR_V1 0x31 25 26 /* PCIE CFG register */ 27 #define PCIE_L1SS_CTRL 0x718 28 #define PCIE_L1_CTRL 0x719 29 #define PCIE_ASPM_CTRL 0x70F 30 #define PCIE_CLK_CTRL 0x725 31 #define PCIE_L1SS_CAP 0x160 32 #define PCIE_L1SS_SUP 0x164 33 #define PCIE_L1SS_STS 0x168 34 35 /* PCIE CFG bit */ 36 #define PCIE_BIT_WAKE BIT(2) 37 #define PCIE_BIT_L1 BIT(3) 38 #define PCIE_BIT_CLK BIT(4) 39 #define PCIE_BIT_L0S BIT(7) 40 #define PCIE_BIT_L1SS BIT(5) 41 #define PCIE_BIT_L1SSSUP BIT(4) 42 43 /* PCIE ASPM mask*/ 44 #define SHFT_L1DLY 3 45 #define SHFT_L0SDLY 0 46 #define PCIE_ASPMDLY_MASK 0x07 47 #define PCIE_L1SS_MASK 0x0F 48 49 /* PCIE Capability */ 50 #define PCIE_L1SS_ID 0x001E 51 52 /* PCIE MAC register */ 53 #define LINK_CTRL2_REG_OFFSET 0xA0 54 #define GEN2_CTRL_OFFSET 0x80C 55 #define LINK_STATUS_REG_OFFSET 0x82 56 57 #define PCIE_GEN1_SPEED 0x01 58 #define PCIE_GEN2_SPEED 0x02 59 60 #endif/* __HALMAC_PCIE_REG_H__ */ 61