1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip Vehicle driver 4 * 5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef _VEHICLE_CSI2_DPHY_COMMON_H_ 9 #define _VEHICLE_CSI2_DPHY_COMMON_H_ 10 11 #include <linux/kernel.h> 12 #include <linux/rk-camera-module.h> 13 #include <media/v4l2-subdev.h> 14 #include "vehicle_samsung_dcphy_common.h" 15 #include "../../../media/platform/rockchip/cif/mipi-csi2.h" 16 17 /* RK3562 DPHY GRF REG OFFSET */ 18 #define RK3562_GRF_VI_CON0 (0x0520) 19 #define RK3562_GRF_VI_CON1 (0x0524) 20 21 /* GRF REG OFFSET */ 22 #define GRF_VI_CON0 (0x0340) 23 #define GRF_VI_CON1 (0x0344) 24 25 /*RK3588 DPHY GRF REG OFFSET */ 26 #define GRF_DPHY_CON0 (0x0) 27 #define GRF_SOC_CON2 (0x0308) 28 29 /*GRF REG BIT DEFINE */ 30 #define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1) 31 #define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0) 32 #define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0) 33 34 /*RK3588 DCPHY GRF REG OFFSET */ 35 #define GRF_DCPHY_CON0 (0x0) 36 37 /* PHY REG OFFSET */ 38 #define CSI2_DPHY_CTRL_INVALID_OFFSET (0xffff) 39 #define CSI2_DPHY_CTRL_PWRCTL \ 40 CSI2_DPHY_CTRL_INVALID_OFFSET 41 #define CSI2_DPHY_CTRL_LANE_ENABLE (0x00) 42 #define CSI2_DPHY_CLK1_LANE_EN (0x2C) 43 #define CSI2_DPHY_DUAL_CAL_EN (0x80) 44 #define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160) 45 #define CSI2_DPHY_CLK_CALIB_EN (0x168) 46 #define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0) 47 #define CSI2_DPHY_LANE0_CALIB_EN (0x1e8) 48 #define CSI2_DPHY_LANE1_WR_THS_SETTLE (0x260) 49 #define CSI2_DPHY_LANE1_CALIB_EN (0x268) 50 #define CSI2_DPHY_LANE2_WR_THS_SETTLE (0x2e0) 51 #define CSI2_DPHY_LANE2_CALIB_EN (0x2e8) 52 #define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360) 53 #define CSI2_DPHY_LANE3_CALIB_EN (0x368) 54 #define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0) 55 #define CSI2_DPHY_CLK1_CALIB_EN (0x3e8) 56 57 //DCPHY 58 #define CSI2_DCPHY_CLK_WR_THS_SETTLE (0x030) 59 #define CSI2_DCPHY_LANE0_WR_THS_SETTLE (0x130) 60 #define CSI2_DCPHY_LANE0_WR_ERR_SOT_SYNC (0x134) 61 #define CSI2_DCPHY_LANE1_WR_THS_SETTLE (0x230) 62 #define CSI2_DCPHY_LANE1_WR_ERR_SOT_SYNC (0x234) 63 #define CSI2_DCPHY_LANE2_WR_THS_SETTLE (0x330) 64 #define CSI2_DCPHY_LANE2_WR_ERR_SOT_SYNC (0x334) 65 #define CSI2_DCPHY_LANE3_WR_THS_SETTLE (0x430) 66 #define CSI2_DCPHY_LANE3_WR_ERR_SOT_SYNC (0x434) 67 #define CSI2_DCPHY_CLK_LANE_ENABLE (0x000) 68 #define CSI2_DCPHY_DATA_LANE0_ENABLE (0x100) 69 #define CSI2_DCPHY_DATA_LANE1_ENABLE (0x200) 70 #define CSI2_DCPHY_DATA_LANE2_ENABLE (0x300) 71 #define CSI2_DCPHY_DATA_LANE3_ENABLE (0x400) 72 73 #define CSI2_DCPHY_S0C_GNR_CON1 (0x004) 74 #define CSI2_DCPHY_S0C_ANA_CON1 (0x00c) 75 #define CSI2_DCPHY_S0C_ANA_CON2 (0x010) 76 #define CSI2_DCPHY_S0C_ANA_CON3 (0x014) 77 #define CSI2_DCPHY_COMBO_S0D0_GNR_CON1 (0x104) 78 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON1 (0x10c) 79 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON2 (0x110) 80 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON3 (0x114) 81 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON6 (0x120) 82 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON7 (0x124) 83 #define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON0 (0x140) 84 #define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON2 (0x148) 85 #define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON4 (0x150) 86 #define CSI2_DCPHY_COMBO_S0D0_CRC_CON1 (0x164) 87 #define CSI2_DCPHY_COMBO_S0D0_CRC_CON2 (0x168) 88 #define CSI2_DCPHY_COMBO_S0D1_GNR_CON1 (0x204) 89 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON1 (0x20c) 90 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON2 (0x210) 91 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON3 (0x214) 92 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON6 (0x220) 93 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON7 (0x224) 94 #define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON0 (0x240) 95 #define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON2 (0x248) 96 #define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON4 (0x250) 97 #define CSI2_DCPHY_COMBO_S0D1_CRC_CON1 (0x264) 98 #define CSI2_DCPHY_COMBO_S0D1_CRC_CON2 (0x268) 99 #define CSI2_DCPHY_COMBO_S0D2_GNR_CON1 (0x304) 100 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON1 (0x30c) 101 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON2 (0x310) 102 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON3 (0x314) 103 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON6 (0x320) 104 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON7 (0x324) 105 #define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON0 (0x340) 106 #define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON2 (0x348) 107 #define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON4 (0x350) 108 #define CSI2_DCPHY_COMBO_S0D2_CRC_CON1 (0x364) 109 #define CSI2_DCPHY_COMBO_S0D2_CRC_CON2 (0x368) 110 #define CSI2_DCPHY_S0D3_GNR_CON1 (0x404) 111 #define CSI2_DCPHY_S0D3_ANA_CON1 (0x40c) 112 #define CSI2_DCPHY_S0D3_ANA_CON2 (0x410) 113 #define CSI2_DCPHY_S0D3_ANA_CON3 (0x414) 114 #define CSI2_DCPHY_S0D3_DESKEW_CON0 (0x440) 115 #define CSI2_DCPHY_S0D3_DESKEW_CON2 (0x448) 116 #define CSI2_DCPHY_S0D3_DESKEW_CON4 (0x450) 117 118 /* PHY REG BIT DEFINE */ 119 #define CSI2_DPHY_LANE_MODE_FULL (0x4) 120 #define CSI2_DPHY_LANE_MODE_SPLIT (0x2) 121 #define CSI2_DPHY_LANE_SPLIT_TOP (0x1) 122 #define CSI2_DPHY_LANE_SPLIT_BOT (0x2) 123 #define CSI2_DPHY_LANE_SPLIT_LANE0_1 (0x3 << 2) 124 #define CSI2_DPHY_LANE_SPLIT_LANE2_3 (0x3 << 4) 125 #define CSI2_DPHY_LANE_DUAL_MODE_EN BIT(6) 126 #define CSI2_DPHY_LANE_PARA_ARR_NUM (0x2) 127 128 #define CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2 129 #define CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT 4 130 #define CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6 131 132 enum csi2_dphy_index { 133 DPHY0 = 0x0, 134 DPHY1, 135 DPHY2, 136 }; 137 138 enum csi2_dphy_lane { 139 CSI2_DPHY_LANE_CLOCK = 0, 140 CSI2_DPHY_LANE_CLOCK1, 141 CSI2_DPHY_LANE_DATA0, 142 CSI2_DPHY_LANE_DATA1, 143 CSI2_DPHY_LANE_DATA2, 144 CSI2_DPHY_LANE_DATA3 145 }; 146 147 enum grf_reg_id { 148 GRF_DPHY_RX0_TURNDISABLE = 0, 149 GRF_DPHY_RX0_FORCERXMODE, 150 GRF_DPHY_RX0_FORCETXSTOPMODE, 151 GRF_DPHY_RX0_ENABLE, 152 GRF_DPHY_RX0_TESTCLR, 153 GRF_DPHY_RX0_TESTCLK, 154 GRF_DPHY_RX0_TESTEN, 155 GRF_DPHY_RX0_TESTDIN, 156 GRF_DPHY_RX0_TURNREQUEST, 157 GRF_DPHY_RX0_TESTDOUT, 158 GRF_DPHY_TX0_TURNDISABLE, 159 GRF_DPHY_TX0_FORCERXMODE, 160 GRF_DPHY_TX0_FORCETXSTOPMODE, 161 GRF_DPHY_TX0_TURNREQUEST, 162 GRF_DPHY_TX1RX1_TURNDISABLE, 163 GRF_DPHY_TX1RX1_FORCERXMODE, 164 GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 165 GRF_DPHY_TX1RX1_ENABLE, 166 GRF_DPHY_TX1RX1_MASTERSLAVEZ, 167 GRF_DPHY_TX1RX1_BASEDIR, 168 GRF_DPHY_TX1RX1_ENABLECLK, 169 GRF_DPHY_TX1RX1_TURNREQUEST, 170 GRF_DPHY_RX1_SRC_SEL, 171 /* rk3288 only */ 172 GRF_CON_DISABLE_ISP, 173 GRF_CON_ISP_DPHY_SEL, 174 GRF_DSI_CSI_TESTBUS_SEL, 175 GRF_DVP_V18SEL, 176 /* rk1808 & rk3326 & rv1126 */ 177 GRF_DPHY_CSI2PHY_FORCERXMODE, 178 GRF_DPHY_CSI2PHY_CLKLANE_EN, 179 GRF_DPHY_CSI2PHY_DATALANE_EN, 180 /* rv1126 only */ 181 GRF_DPHY_CLK_INV_SEL, 182 GRF_DPHY_SEL, 183 /* rk3368 only */ 184 GRF_ISP_MIPI_CSI_HOST_SEL, 185 /* below is for rk3399 only */ 186 GRF_DPHY_RX0_CLK_INV_SEL, 187 GRF_DPHY_RX1_CLK_INV_SEL, 188 GRF_DPHY_TX1RX1_SRC_SEL, 189 /* below is for rk3568 only */ 190 GRF_DPHY_CSI2PHY_CLKLANE1_EN, 191 GRF_DPHY_CLK1_INV_SEL, 192 GRF_DPHY_ISP_CSI2PHY_SEL, 193 GRF_DPHY_CIF_CSI2PHY_SEL, 194 GRF_DPHY_CSI2PHY_LANE_SEL, 195 GRF_DPHY_CSI2PHY1_LANE_SEL, 196 GRF_DPHY_CSI2PHY_DATALANE_EN0, 197 GRF_DPHY_CSI2PHY_DATALANE_EN1, 198 GRF_CPHY_MODE, 199 GRF_DPHY_CSIHOST2_SEL, 200 GRF_DPHY_CSIHOST3_SEL, 201 GRF_DPHY_CSIHOST4_SEL, 202 GRF_DPHY_CSIHOST5_SEL, 203 /* below is for rv1106 only */ 204 GRF_MIPI_HOST0_SEL, 205 GRF_LVDS_HOST0_SEL, 206 /* below is for rk3562 */ 207 GRF_DPHY1_CLK_INV_SEL, 208 GRF_DPHY1_CLK1_INV_SEL, 209 GRF_DPHY1_CSI2PHY_CLKLANE1_EN, 210 GRF_DPHY1_CSI2PHY_FORCERXMODE, 211 GRF_DPHY1_CSI2PHY_CLKLANE_EN, 212 GRF_DPHY1_CSI2PHY_DATALANE_EN, 213 GRF_DPHY1_CSI2PHY_DATALANE_EN0, 214 GRF_DPHY1_CSI2PHY_DATALANE_EN1, 215 }; 216 217 enum csi2dphy_reg_id { 218 CSI2PHY_REG_CTRL_LANE_ENABLE = 0, 219 CSI2PHY_CTRL_PWRCTL, 220 CSI2PHY_CTRL_DIG_RST, 221 CSI2PHY_CLK_THS_SETTLE, 222 CSI2PHY_LANE0_THS_SETTLE, 223 CSI2PHY_LANE1_THS_SETTLE, 224 CSI2PHY_LANE2_THS_SETTLE, 225 CSI2PHY_LANE3_THS_SETTLE, 226 CSI2PHY_CLK_CALIB_ENABLE, 227 CSI2PHY_LANE0_CALIB_ENABLE, 228 CSI2PHY_LANE1_CALIB_ENABLE, 229 CSI2PHY_LANE2_CALIB_ENABLE, 230 CSI2PHY_LANE3_CALIB_ENABLE, 231 //rv1126 only 232 CSI2PHY_MIPI_LVDS_MODEL, 233 CSI2PHY_LVDS_MODE, 234 //rk3568 only 235 CSI2PHY_DUAL_CLK_EN, 236 CSI2PHY_CLK1_THS_SETTLE, 237 CSI2PHY_CLK1_CALIB_ENABLE, 238 //rk3588 239 CSI2PHY_CLK_LANE_ENABLE, 240 CSI2PHY_CLK1_LANE_ENABLE, 241 CSI2PHY_DATA_LANE0_ENABLE, 242 CSI2PHY_DATA_LANE1_ENABLE, 243 CSI2PHY_DATA_LANE2_ENABLE, 244 CSI2PHY_DATA_LANE3_ENABLE, 245 CSI2PHY_LANE0_ERR_SOT_SYNC, 246 CSI2PHY_LANE1_ERR_SOT_SYNC, 247 CSI2PHY_LANE2_ERR_SOT_SYNC, 248 CSI2PHY_LANE3_ERR_SOT_SYNC, 249 CSI2PHY_S0C_GNR_CON1, 250 CSI2PHY_S0C_ANA_CON1, 251 CSI2PHY_S0C_ANA_CON2, 252 CSI2PHY_S0C_ANA_CON3, 253 CSI2PHY_COMBO_S0D0_GNR_CON1, 254 CSI2PHY_COMBO_S0D0_ANA_CON1, 255 CSI2PHY_COMBO_S0D0_ANA_CON2, 256 CSI2PHY_COMBO_S0D0_ANA_CON3, 257 CSI2PHY_COMBO_S0D0_ANA_CON6, 258 CSI2PHY_COMBO_S0D0_ANA_CON7, 259 CSI2PHY_COMBO_S0D0_DESKEW_CON0, 260 CSI2PHY_COMBO_S0D0_DESKEW_CON2, 261 CSI2PHY_COMBO_S0D0_DESKEW_CON4, 262 CSI2PHY_COMBO_S0D0_CRC_CON1, 263 CSI2PHY_COMBO_S0D0_CRC_CON2, 264 CSI2PHY_COMBO_S0D1_GNR_CON1, 265 CSI2PHY_COMBO_S0D1_ANA_CON1, 266 CSI2PHY_COMBO_S0D1_ANA_CON2, 267 CSI2PHY_COMBO_S0D1_ANA_CON3, 268 CSI2PHY_COMBO_S0D1_ANA_CON6, 269 CSI2PHY_COMBO_S0D1_ANA_CON7, 270 CSI2PHY_COMBO_S0D1_DESKEW_CON0, 271 CSI2PHY_COMBO_S0D1_DESKEW_CON2, 272 CSI2PHY_COMBO_S0D1_DESKEW_CON4, 273 CSI2PHY_COMBO_S0D1_CRC_CON1, 274 CSI2PHY_COMBO_S0D1_CRC_CON2, 275 CSI2PHY_COMBO_S0D2_GNR_CON1, 276 CSI2PHY_COMBO_S0D2_ANA_CON1, 277 CSI2PHY_COMBO_S0D2_ANA_CON2, 278 CSI2PHY_COMBO_S0D2_ANA_CON3, 279 CSI2PHY_COMBO_S0D2_ANA_CON6, 280 CSI2PHY_COMBO_S0D2_ANA_CON7, 281 CSI2PHY_COMBO_S0D2_DESKEW_CON0, 282 CSI2PHY_COMBO_S0D2_DESKEW_CON2, 283 CSI2PHY_COMBO_S0D2_DESKEW_CON4, 284 CSI2PHY_COMBO_S0D2_CRC_CON1, 285 CSI2PHY_COMBO_S0D2_CRC_CON2, 286 CSI2PHY_S0D3_GNR_CON1, 287 CSI2PHY_S0D3_ANA_CON1, 288 CSI2PHY_S0D3_ANA_CON2, 289 CSI2PHY_S0D3_ANA_CON3, 290 CSI2PHY_S0D3_DESKEW_CON0, 291 CSI2PHY_S0D3_DESKEW_CON2, 292 CSI2PHY_S0D3_DESKEW_CON4, 293 }; 294 295 #define HIWORD_UPDATE(val, mask, shift) \ 296 ((val) << (shift) | (mask) << ((shift) + 16)) 297 298 #define GRF_REG(_offset, _width, _shift) \ 299 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } 300 301 #define CSI2PHY_REG(_offset) \ 302 { .offset = _offset, } 303 304 /* add new chip id in tail by time order */ 305 enum csi2_dphy_chip_id { 306 CHIP_ID_RK3568 = 0x0, 307 CHIP_ID_RK3588 = 0x1, 308 CHIP_ID_RK3588_DCPHY = 0x2, 309 CHIP_ID_RV1106 = 0x3, 310 CHIP_ID_RK3562 = 0x4, 311 }; 312 313 enum csi2_dphy_rx_pads { 314 CSI2_DPHY_RX_PAD_SINK = 0, 315 CSI2_DPHY_RX_PAD_SOURCE, 316 CSI2_DPHY_RX_PADS_NUM, 317 }; 318 319 enum csi2_dphy_lane_mode { 320 LANE_MODE_UNDEF = 0x0, 321 LANE_MODE_FULL, 322 LANE_MODE_SPLIT, 323 }; 324 325 struct grf_reg { 326 u32 offset; 327 u32 mask; 328 u32 shift; 329 }; 330 331 struct csi2dphy_reg { 332 u32 offset; 333 }; 334 335 struct hsfreq_range { 336 u32 range_h; 337 u16 cfg_bit; 338 }; 339 340 #define MAX_DPHY_SENSORS (2) 341 #define MAX_NUM_CSI2_DPHY (0x2) 342 343 #define RKCSI2_MAX_RESET 8 344 #define RKDPHY_MAX_RESET 8 345 /* csi2 head */ 346 347 struct csi2_dphy_hw { 348 struct clk_bulk_data *dphy_clks; 349 int num_dphy_clks; 350 struct clk_bulk_data *csi2_clks; 351 int num_csi2_clks; 352 const char * const *csi2_rsts; 353 struct reset_control *csi2_rst[RKCSI2_MAX_RESET]; 354 int num_csi2_rsts; 355 const char * const *dphy_rsts; 356 struct reset_control *dphy_rst[RKDPHY_MAX_RESET]; 357 int num_dphy_rsts; 358 // struct reset_control *rsts_bulk; 359 /* spinlock_t lock; */ 360 bool on; 361 const struct hsfreq_range *hsfreq_ranges; 362 int num_hsfreq_ranges; 363 const struct grf_reg *grf_regs; 364 const struct txrx_reg *txrx_regs; 365 const struct csi2dphy_reg *csi2dphy_regs; 366 enum csi2_dphy_chip_id chip_id; 367 struct device *dev; 368 struct regmap *regmap_grf; 369 struct regmap *regmap_sys_grf; 370 void __iomem *csi2_dphy_base; /*csi2_dphy base addr*/ 371 void __iomem *csi2_base; /*csi2 base addr*/ 372 struct mutex mutex; /* lock for updating protection */ 373 atomic_t stream_cnt; 374 struct csi2_err_stats err_list[RK_CSI2_ERR_MAX]; 375 u64 data_rate_mbps; 376 struct rkmodule_csi_dphy_param *dphy_param; 377 struct samsung_mipi_dcphy *samsung_phy; 378 int phy_index; 379 }; 380 381 #endif 382