1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Texas Instruments, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLK_DM816_H 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLK_DM816_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define DM816_CLKCTRL_OFFSET 0x0 9*4882a593Smuzhiyun #define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* default clocks */ 12*4882a593Smuzhiyun #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* alwon clocks */ 15*4882a593Smuzhiyun #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16*4882a593Smuzhiyun #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17*4882a593Smuzhiyun #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18*4882a593Smuzhiyun #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19*4882a593Smuzhiyun #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20*4882a593Smuzhiyun #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21*4882a593Smuzhiyun #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22*4882a593Smuzhiyun #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) 23*4882a593Smuzhiyun #define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174) 24*4882a593Smuzhiyun #define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178) 25*4882a593Smuzhiyun #define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c) 26*4882a593Smuzhiyun #define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180) 27*4882a593Smuzhiyun #define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184) 28*4882a593Smuzhiyun #define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188) 29*4882a593Smuzhiyun #define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c) 30*4882a593Smuzhiyun #define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190) 31*4882a593Smuzhiyun #define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194) 32*4882a593Smuzhiyun #define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198) 33*4882a593Smuzhiyun #define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0) 34*4882a593Smuzhiyun #define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0) 35*4882a593Smuzhiyun #define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4) 36*4882a593Smuzhiyun #define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8) 37*4882a593Smuzhiyun #define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc) 38*4882a593Smuzhiyun #define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0) 39*4882a593Smuzhiyun #define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4) 40*4882a593Smuzhiyun #define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8) 41*4882a593Smuzhiyun #define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc) 42*4882a593Smuzhiyun #define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200) 43*4882a593Smuzhiyun #define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif 46