Lines Matching +full:0 +full:x168
18 #define RK3562_GRF_VI_CON0 (0x0520)
19 #define RK3562_GRF_VI_CON1 (0x0524)
22 #define GRF_VI_CON0 (0x0340)
23 #define GRF_VI_CON1 (0x0344)
26 #define GRF_DPHY_CON0 (0x0)
27 #define GRF_SOC_CON2 (0x0308)
30 #define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
31 #define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0)
32 #define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0)
35 #define GRF_DCPHY_CON0 (0x0)
38 #define CSI2_DPHY_CTRL_INVALID_OFFSET (0xffff)
41 #define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
42 #define CSI2_DPHY_CLK1_LANE_EN (0x2C)
43 #define CSI2_DPHY_DUAL_CAL_EN (0x80)
44 #define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
45 #define CSI2_DPHY_CLK_CALIB_EN (0x168)
46 #define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
47 #define CSI2_DPHY_LANE0_CALIB_EN (0x1e8)
48 #define CSI2_DPHY_LANE1_WR_THS_SETTLE (0x260)
49 #define CSI2_DPHY_LANE1_CALIB_EN (0x268)
50 #define CSI2_DPHY_LANE2_WR_THS_SETTLE (0x2e0)
51 #define CSI2_DPHY_LANE2_CALIB_EN (0x2e8)
52 #define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360)
53 #define CSI2_DPHY_LANE3_CALIB_EN (0x368)
54 #define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0)
55 #define CSI2_DPHY_CLK1_CALIB_EN (0x3e8)
58 #define CSI2_DCPHY_CLK_WR_THS_SETTLE (0x030)
59 #define CSI2_DCPHY_LANE0_WR_THS_SETTLE (0x130)
60 #define CSI2_DCPHY_LANE0_WR_ERR_SOT_SYNC (0x134)
61 #define CSI2_DCPHY_LANE1_WR_THS_SETTLE (0x230)
62 #define CSI2_DCPHY_LANE1_WR_ERR_SOT_SYNC (0x234)
63 #define CSI2_DCPHY_LANE2_WR_THS_SETTLE (0x330)
64 #define CSI2_DCPHY_LANE2_WR_ERR_SOT_SYNC (0x334)
65 #define CSI2_DCPHY_LANE3_WR_THS_SETTLE (0x430)
66 #define CSI2_DCPHY_LANE3_WR_ERR_SOT_SYNC (0x434)
67 #define CSI2_DCPHY_CLK_LANE_ENABLE (0x000)
68 #define CSI2_DCPHY_DATA_LANE0_ENABLE (0x100)
69 #define CSI2_DCPHY_DATA_LANE1_ENABLE (0x200)
70 #define CSI2_DCPHY_DATA_LANE2_ENABLE (0x300)
71 #define CSI2_DCPHY_DATA_LANE3_ENABLE (0x400)
73 #define CSI2_DCPHY_S0C_GNR_CON1 (0x004)
74 #define CSI2_DCPHY_S0C_ANA_CON1 (0x00c)
75 #define CSI2_DCPHY_S0C_ANA_CON2 (0x010)
76 #define CSI2_DCPHY_S0C_ANA_CON3 (0x014)
77 #define CSI2_DCPHY_COMBO_S0D0_GNR_CON1 (0x104)
78 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON1 (0x10c)
79 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON2 (0x110)
80 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON3 (0x114)
81 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON6 (0x120)
82 #define CSI2_DCPHY_COMBO_S0D0_ANA_CON7 (0x124)
83 #define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON0 (0x140)
84 #define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON2 (0x148)
85 #define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON4 (0x150)
86 #define CSI2_DCPHY_COMBO_S0D0_CRC_CON1 (0x164)
87 #define CSI2_DCPHY_COMBO_S0D0_CRC_CON2 (0x168)
88 #define CSI2_DCPHY_COMBO_S0D1_GNR_CON1 (0x204)
89 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON1 (0x20c)
90 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON2 (0x210)
91 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON3 (0x214)
92 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON6 (0x220)
93 #define CSI2_DCPHY_COMBO_S0D1_ANA_CON7 (0x224)
94 #define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON0 (0x240)
95 #define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON2 (0x248)
96 #define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON4 (0x250)
97 #define CSI2_DCPHY_COMBO_S0D1_CRC_CON1 (0x264)
98 #define CSI2_DCPHY_COMBO_S0D1_CRC_CON2 (0x268)
99 #define CSI2_DCPHY_COMBO_S0D2_GNR_CON1 (0x304)
100 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON1 (0x30c)
101 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON2 (0x310)
102 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON3 (0x314)
103 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON6 (0x320)
104 #define CSI2_DCPHY_COMBO_S0D2_ANA_CON7 (0x324)
105 #define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON0 (0x340)
106 #define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON2 (0x348)
107 #define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON4 (0x350)
108 #define CSI2_DCPHY_COMBO_S0D2_CRC_CON1 (0x364)
109 #define CSI2_DCPHY_COMBO_S0D2_CRC_CON2 (0x368)
110 #define CSI2_DCPHY_S0D3_GNR_CON1 (0x404)
111 #define CSI2_DCPHY_S0D3_ANA_CON1 (0x40c)
112 #define CSI2_DCPHY_S0D3_ANA_CON2 (0x410)
113 #define CSI2_DCPHY_S0D3_ANA_CON3 (0x414)
114 #define CSI2_DCPHY_S0D3_DESKEW_CON0 (0x440)
115 #define CSI2_DCPHY_S0D3_DESKEW_CON2 (0x448)
116 #define CSI2_DCPHY_S0D3_DESKEW_CON4 (0x450)
119 #define CSI2_DPHY_LANE_MODE_FULL (0x4)
120 #define CSI2_DPHY_LANE_MODE_SPLIT (0x2)
121 #define CSI2_DPHY_LANE_SPLIT_TOP (0x1)
122 #define CSI2_DPHY_LANE_SPLIT_BOT (0x2)
123 #define CSI2_DPHY_LANE_SPLIT_LANE0_1 (0x3 << 2)
124 #define CSI2_DPHY_LANE_SPLIT_LANE2_3 (0x3 << 4)
126 #define CSI2_DPHY_LANE_PARA_ARR_NUM (0x2)
133 DPHY0 = 0x0,
139 CSI2_DPHY_LANE_CLOCK = 0,
148 GRF_DPHY_RX0_TURNDISABLE = 0,
218 CSI2PHY_REG_CTRL_LANE_ENABLE = 0,
306 CHIP_ID_RK3568 = 0x0,
307 CHIP_ID_RK3588 = 0x1,
308 CHIP_ID_RK3588_DCPHY = 0x2,
309 CHIP_ID_RV1106 = 0x3,
310 CHIP_ID_RK3562 = 0x4,
314 CSI2_DPHY_RX_PAD_SINK = 0,
320 LANE_MODE_UNDEF = 0x0,
341 #define MAX_NUM_CSI2_DPHY (0x2)