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/OK3568_Linux_fs/kernel/include/linux/mtd/
H A Ddoc2000.h17 #define DoC_Sig1 0
20 #define DoC_ChipID 0x1000
21 #define DoC_DOCStatus 0x1001
22 #define DoC_DOCControl 0x1002
23 #define DoC_FloorSelect 0x1003
24 #define DoC_CDSNControl 0x1004
25 #define DoC_CDSNDeviceSelect 0x1005
26 #define DoC_ECCConf 0x1006
27 #define DoC_2k_ECCStatus 0x1007
29 #define DoC_CDSNSlowIO 0x100d
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-armada100/
H A Dcpu.h20 u8 pad0[0x08 - 0x00];
21 u32 fccr; /*0x0008*/
22 u32 pocr; /*0x000c*/
23 u32 posr; /*0x0010*/
24 u32 succr; /*0x0014*/
25 u8 pad1[0x030 - 0x014 - 4];
26 u32 gpcr; /*0x0030*/
27 u8 pad2[0x200 - 0x030 - 4];
28 u32 wdtpcr; /*0x0200*/
29 u8 pad3[0x1000 - 0x200 - 4];
[all …]
/OK3568_Linux_fs/u-boot/include/linux/mtd/
H A Ddoc2000.h17 #if 0
21 #define DoC_Sig1 0
24 #define DoC_ChipID 0x1000
25 #define DoC_DOCStatus 0x1001
26 #define DoC_DOCControl 0x1002
27 #define DoC_FloorSelect 0x1003
28 #define DoC_CDSNControl 0x1004
29 #define DoC_CDSNDeviceSelect 0x1005
30 #define DoC_ECCConf 0x1006
31 #define DoC_2k_ECCStatus 0x1007
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/kernel/
H A Dhead_40x.S83 . = 0xc0
105 stw r10,crit_r10@l(0); /* save two registers to work with */\
106 stw r11,crit_r11@l(0); \
131 stw r1,0(r11); \
133 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
165 * 0x0100 - Critical Interrupt Exception
167 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
170 * 0x0200 - Machine Check Exception
172 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
175 * 0x0300 - Data Storage Exception
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dgpucc-msm8998.c36 .halt_reg = 0x1020,
38 .enable_reg = 0x1020,
39 .enable_mask = BIT(0),
54 { 0x0, 1 },
55 { 0x1, 2 },
56 { 0x3, 4 },
57 { 0x7, 8 },
62 .offset = 0x0,
73 .offset = 0x0,
88 { P_XO, 0 },
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-pci-dwc-mshc.c15 #define SDHCI_VENDOR_PTR_R 0xE8
18 #define SDHC_GPIO_OUT 0x34
19 #define SDHC_AT_CTRL_R 0x40
20 #define SDHC_SW_TUNE_EN 0x00000010
23 #define SDHC_MMCM_DIV_REG 0x1020
24 #define DIV_REG_100_MHZ 0x1145
25 #define DIV_REG_200_MHZ 0x1083
26 #define SDHC_MMCM_CLKFBOUT 0x1024
27 #define CLKFBOUT_100_MHZ 0x0000
28 #define CLKFBOUT_200_MHZ 0x0080
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/cpu/quark/
H A DKconfig47 default 0xfff00000
52 The default base address of 0xfff00000 indicates that the binary must
53 be located at offset 0 from the beginning of a 1MB flash device.
71 default 0x80000000
77 default 0xe0000000
81 default 0xfed1c000
87 default 0x1000
94 default 0x1010
101 default 0x1020
107 default 0x1080
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dsprd,sc9863a-clk.yaml82 reg = <0x21500000 0x1000>;
91 reg = <0x20e00000 0x4000>;
94 ranges = <0 0x20e00000 0x4000>;
96 apahb_gate: apahb-gate@0 {
98 reg = <0x0 0x1020>;
/OK3568_Linux_fs/kernel/drivers/gpu/arm/mali400/mali/regs/
H A Dmali_200_regs.h18 MALI200_REG_ADDR_MGMT_VERSION = 0x1000,
19 MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR = 0x1004,
20 MALI200_REG_ADDR_MGMT_STATUS = 0x1008,
21 MALI200_REG_ADDR_MGMT_CTRL_MGMT = 0x100c,
23 MALI200_REG_ADDR_MGMT_INT_RAWSTAT = 0x1020,
24 MALI200_REG_ADDR_MGMT_INT_CLEAR = 0x1024,
25 MALI200_REG_ADDR_MGMT_INT_MASK = 0x1028,
26 MALI200_REG_ADDR_MGMT_INT_STATUS = 0x102c,
28 MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS = 0x1050,
30 MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE = 0x1080,
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/qcom/venus/
H A Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 (VBIF_BASE + 0x208)
12 #define VBIF_AXI_HALT_CTRL1 (VBIF_BASE + 0x20c)
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
19 #define CPU_CS_BASE (CPU_BASE + 0x12000)
20 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE + 0x1c)
24 #define VIDC_CTRL_INIT (CPU_CS_BASE + 0x48)
[all …]
/OK3568_Linux_fs/yocto/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-connectivity/lirc/lirc/
H A Dlircd.conf21 pre_data 0x54
25 MUTE 0x70
26 EXIT 0xA8
27 POWER 0xF0
28 CHANNEL_UP 0x50
29 CHANNEL_DOWN 0xD0
30 VOLUME_UP 0x30
31 VOLUME_DOWN 0xB0
32 OK 0x98
33 FAVORITES 0x04
[all …]
/OK3568_Linux_fs/kernel/include/uapi/linux/
H A Dmedia-bus-format.h16 * These bus formats uniquely identify data formats on the data bus. Format 0
35 #define MEDIA_BUS_FMT_FIXED 0x0001
37 /* RGB - next is 0x1024 */
38 #define MEDIA_BUS_FMT_RGB444_1X12 0x1016
39 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
40 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
41 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
42 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
43 #define MEDIA_BUS_FMT_RGB565_1X16 0x1017
44 #define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
[all …]
/OK3568_Linux_fs/u-boot/include/linux/
H A Dmedia-bus-format.h16 * These bus formats uniquely identify data formats on the data bus. Format 0
35 #define MEDIA_BUS_FMT_FIXED 0x0001
37 /* RGB - next is 0x1024 */
38 #define MEDIA_BUS_FMT_RGB444_1X12 0x1016
39 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
40 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
41 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
42 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
43 #define MEDIA_BUS_FMT_RGB565_1X16 0x1017
44 #define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/mach-common/mach/
H A Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dusb_mac.c11 s8 offset = 0; in mt76x2u_mac_fixup_xtal()
16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal()
17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal()
18 offset = 0; in mt76x2u_mac_fixup_xtal()
19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal()
20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal()
23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal()
25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal()
27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal()
28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal()
[all …]
/OK3568_Linux_fs/kernel/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml66 const: 0
69 "^dai-link@[0-9a-f]$":
187 reg = <0 0x62d87000 0 0x68000>,
188 <0 0x62f00000 0 0x29000>;
191 iommus = <&apps_smmu 0x1020 0>,
192 <&apps_smmu 0x1032 0>;
193 power-domains = <&lpass_hm 0>;
206 interrupts = <0 160 1>,
207 <0 268 1>;
213 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/lima/
H A Dlima_regs.h14 #define LIMA_PMU_POWER_UP 0x00
15 #define LIMA_PMU_POWER_DOWN 0x04
16 #define LIMA_PMU_POWER_GP0_MASK BIT(0)
29 #define LIMA_PMU_STATUS 0x08
30 #define LIMA_PMU_INT_MASK 0x0C
31 #define LIMA_PMU_INT_RAWSTAT 0x10
32 #define LIMA_PMU_INT_CLEAR 0x18
33 #define LIMA_PMU_INT_CMD_MASK BIT(0)
34 #define LIMA_PMU_SW_DELAY 0x1C
37 #define LIMA_L2_CACHE_SIZE 0x0004
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rmobile/include/mach/
H A Dsh73a0.h5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
6 #define MERAM_BASE (0xE5580000)
9 #define GIC_BASE (0xF0000100)
13 #define LIFEC_SEC_SRC (0xE6110008)
16 #define RWDT_BASE (0xE6020000)
19 #define HPB_BASE (0xE6001010)
22 #define HPBSCR_BASE (0xE6001600)
25 #define SBSC1_BASE (0xFE400000)
26 #define SDMRA1A (SBSC1_BASE + 0x100000)
27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
61 reg = <0 0x1100>;
69 reg = <0 0x40353000 0 0x3000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/emxx_udc/
H A Demxx_udc.h21 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */
22 #define INT_VBUS 0 /* IRQ for GPIO_P153 */
48 #define U2F_DISABLE 0
62 #define MAX_TEST_MODE_NUM 0x05
65 /*------- (0x0004) USB Status Register */
75 /*------- (0x0008) USB Address Register */
76 #define USB_ADDR 0x007F0000
79 #define FRAME 0x000007FF
83 /*------- (0x000C) UTMI Characteristic 1 Register */
88 /*------- (0x0010) TEST Control Register */
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]

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