1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ARMADA100CPU_H 10*4882a593Smuzhiyun #define _ARMADA100CPU_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun #include <asm/system.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Main Power Management (MPMU) Registers 17*4882a593Smuzhiyun * Refer Datasheet Appendix A.8 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun struct armd1mpmu_registers { 20*4882a593Smuzhiyun u8 pad0[0x08 - 0x00]; 21*4882a593Smuzhiyun u32 fccr; /*0x0008*/ 22*4882a593Smuzhiyun u32 pocr; /*0x000c*/ 23*4882a593Smuzhiyun u32 posr; /*0x0010*/ 24*4882a593Smuzhiyun u32 succr; /*0x0014*/ 25*4882a593Smuzhiyun u8 pad1[0x030 - 0x014 - 4]; 26*4882a593Smuzhiyun u32 gpcr; /*0x0030*/ 27*4882a593Smuzhiyun u8 pad2[0x200 - 0x030 - 4]; 28*4882a593Smuzhiyun u32 wdtpcr; /*0x0200*/ 29*4882a593Smuzhiyun u8 pad3[0x1000 - 0x200 - 4]; 30*4882a593Smuzhiyun u32 apcr; /*0x1000*/ 31*4882a593Smuzhiyun u32 apsr; /*0x1004*/ 32*4882a593Smuzhiyun u8 pad4[0x1020 - 0x1004 - 4]; 33*4882a593Smuzhiyun u32 aprr; /*0x1020*/ 34*4882a593Smuzhiyun u32 acgr; /*0x1024*/ 35*4882a593Smuzhiyun u32 arsr; /*0x1028*/ 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Application Subsystem Power Management 40*4882a593Smuzhiyun * Refer Datasheet Appendix A.9 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun struct armd1apmu_registers { 43*4882a593Smuzhiyun u32 pcr; /* 0x000 */ 44*4882a593Smuzhiyun u32 ccr; /* 0x004 */ 45*4882a593Smuzhiyun u32 pad1; 46*4882a593Smuzhiyun u32 ccsr; /* 0x00C */ 47*4882a593Smuzhiyun u32 fc_timer; /* 0x010 */ 48*4882a593Smuzhiyun u32 pad2; 49*4882a593Smuzhiyun u32 ideal_cfg; /* 0x018 */ 50*4882a593Smuzhiyun u8 pad3[0x04C - 0x018 - 4]; 51*4882a593Smuzhiyun u32 lcdcrc; /* 0x04C */ 52*4882a593Smuzhiyun u32 cciccrc; /* 0x050 */ 53*4882a593Smuzhiyun u32 sd1crc; /* 0x054 */ 54*4882a593Smuzhiyun u32 sd2crc; /* 0x058 */ 55*4882a593Smuzhiyun u32 usbcrc; /* 0x05C */ 56*4882a593Smuzhiyun u32 nfccrc; /* 0x060 */ 57*4882a593Smuzhiyun u32 dmacrc; /* 0x064 */ 58*4882a593Smuzhiyun u32 pad4; 59*4882a593Smuzhiyun u32 buscrc; /* 0x06C */ 60*4882a593Smuzhiyun u8 pad5[0x07C - 0x06C - 4]; 61*4882a593Smuzhiyun u32 wake_clr; /* 0x07C */ 62*4882a593Smuzhiyun u8 pad6[0x090 - 0x07C - 4]; 63*4882a593Smuzhiyun u32 core_status; /* 0x090 */ 64*4882a593Smuzhiyun u32 rfsc; /* 0x094 */ 65*4882a593Smuzhiyun u32 imr; /* 0x098 */ 66*4882a593Smuzhiyun u32 irwc; /* 0x09C */ 67*4882a593Smuzhiyun u32 isr; /* 0x0A0 */ 68*4882a593Smuzhiyun u8 pad7[0x0B0 - 0x0A0 - 4]; 69*4882a593Smuzhiyun u32 mhst; /* 0x0B0 */ 70*4882a593Smuzhiyun u32 msr; /* 0x0B4 */ 71*4882a593Smuzhiyun u8 pad8[0x0C0 - 0x0B4 - 4]; 72*4882a593Smuzhiyun u32 msst; /* 0x0C0 */ 73*4882a593Smuzhiyun u32 pllss; /* 0x0C4 */ 74*4882a593Smuzhiyun u32 smb; /* 0x0C8 */ 75*4882a593Smuzhiyun u32 gccrc; /* 0x0CC */ 76*4882a593Smuzhiyun u8 pad9[0x0D4 - 0x0CC - 4]; 77*4882a593Smuzhiyun u32 smccrc; /* 0x0D4 */ 78*4882a593Smuzhiyun u32 pad10; 79*4882a593Smuzhiyun u32 xdcrc; /* 0x0DC */ 80*4882a593Smuzhiyun u32 sd3crc; /* 0x0E0 */ 81*4882a593Smuzhiyun u32 sd4crc; /* 0x0E4 */ 82*4882a593Smuzhiyun u8 pad11[0x0F0 - 0x0E4 - 4]; 83*4882a593Smuzhiyun u32 cfcrc; /* 0x0F0 */ 84*4882a593Smuzhiyun u32 mspcrc; /* 0x0F4 */ 85*4882a593Smuzhiyun u32 cmucrc; /* 0x0F8 */ 86*4882a593Smuzhiyun u32 fecrc; /* 0x0FC */ 87*4882a593Smuzhiyun u32 pciecrc; /* 0x100 */ 88*4882a593Smuzhiyun u32 epdcrc; /* 0x104 */ 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * APB1 Clock Reset/Control Registers 93*4882a593Smuzhiyun * Refer Datasheet Appendix A.10 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun struct armd1apb1_registers { 96*4882a593Smuzhiyun u32 uart1; /*0x000*/ 97*4882a593Smuzhiyun u32 uart2; /*0x004*/ 98*4882a593Smuzhiyun u32 gpio; /*0x008*/ 99*4882a593Smuzhiyun u32 pwm1; /*0x00c*/ 100*4882a593Smuzhiyun u32 pwm2; /*0x010*/ 101*4882a593Smuzhiyun u32 pwm3; /*0x014*/ 102*4882a593Smuzhiyun u32 pwm4; /*0x018*/ 103*4882a593Smuzhiyun u8 pad0[0x028 - 0x018 - 4]; 104*4882a593Smuzhiyun u32 rtc; /*0x028*/ 105*4882a593Smuzhiyun u32 twsi0; /*0x02c*/ 106*4882a593Smuzhiyun u32 kpc; /*0x030*/ 107*4882a593Smuzhiyun u32 timers; /*0x034*/ 108*4882a593Smuzhiyun u8 pad1[0x03c - 0x034 - 4]; 109*4882a593Smuzhiyun u32 aib; /*0x03c*/ 110*4882a593Smuzhiyun u32 sw_jtag; /*0x040*/ 111*4882a593Smuzhiyun u32 timer1; /*0x044*/ 112*4882a593Smuzhiyun u32 onewire; /*0x048*/ 113*4882a593Smuzhiyun u8 pad2[0x050 - 0x048 - 4]; 114*4882a593Smuzhiyun u32 asfar; /*0x050 AIB Secure First Access Reg*/ 115*4882a593Smuzhiyun u32 assar; /*0x054 AIB Secure Second Access Reg*/ 116*4882a593Smuzhiyun u8 pad3[0x06c - 0x054 - 4]; 117*4882a593Smuzhiyun u32 twsi1; /*0x06c*/ 118*4882a593Smuzhiyun u32 uart3; /*0x070*/ 119*4882a593Smuzhiyun u8 pad4[0x07c - 0x070 - 4]; 120*4882a593Smuzhiyun u32 timer2; /*0x07C*/ 121*4882a593Smuzhiyun u8 pad5[0x084 - 0x07c - 4]; 122*4882a593Smuzhiyun u32 ac97; /*0x084*/ 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* 126*4882a593Smuzhiyun * APB2 Clock Reset/Control Registers 127*4882a593Smuzhiyun * Refer Datasheet Appendix A.11 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun struct armd1apb2_registers { 130*4882a593Smuzhiyun u32 pad1[0x01C - 0x000]; 131*4882a593Smuzhiyun u32 ssp1_clkrst; /* 0x01C */ 132*4882a593Smuzhiyun u32 ssp2_clkrst; /* 0x020 */ 133*4882a593Smuzhiyun u32 pad2[0x04C - 0x020 - 4]; 134*4882a593Smuzhiyun u32 ssp3_clkrst; /* 0x04C */ 135*4882a593Smuzhiyun u32 pad3[0x058 - 0x04C - 4]; 136*4882a593Smuzhiyun u32 ssp4_clkrst; /* 0x058 */ 137*4882a593Smuzhiyun u32 ssp5_clkrst; /* 0x05C */ 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* 141*4882a593Smuzhiyun * CPU Interface Registers 142*4882a593Smuzhiyun * Refer Datasheet Appendix A.2 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun struct armd1cpu_registers { 145*4882a593Smuzhiyun u32 chip_id; /* Chip Id Reg */ 146*4882a593Smuzhiyun u32 pad; 147*4882a593Smuzhiyun u32 cpu_conf; /* CPU Conf Reg */ 148*4882a593Smuzhiyun u32 pad1; 149*4882a593Smuzhiyun u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ 150*4882a593Smuzhiyun u32 pad2; 151*4882a593Smuzhiyun u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ 152*4882a593Smuzhiyun u32 mcb_conf; /* MCB Conf Reg */ 153*4882a593Smuzhiyun u32 sys_boot_ctl; /* Sytem Boot Control */ 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* 157*4882a593Smuzhiyun * Functions 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun u32 armd1_sdram_base(int); 160*4882a593Smuzhiyun u32 armd1_sdram_size(int); 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #endif /* _ARMADA100CPU_H */ 163