1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __MACH_URQUELL_H 3*4882a593Smuzhiyun #define __MACH_URQUELL_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * ------ 0x00000000 ------------------------------------ 7*4882a593Smuzhiyun * CS0 | (SW1,SW47) EEPROM, SRAM, NOR FLASH 8*4882a593Smuzhiyun * -----+ 0x04000000 ------------------------------------ 9*4882a593Smuzhiyun * CS1 | (SW47) SRAM, SRAM-LAN-PCMCIA, NOR FLASH 10*4882a593Smuzhiyun * -----+ 0x08000000 ------------------------------------ 11*4882a593Smuzhiyun * CS2 | DDR3 12*4882a593Smuzhiyun * CS3 | 13*4882a593Smuzhiyun * -----+ 0x10000000 ------------------------------------ 14*4882a593Smuzhiyun * CS4 | PCIe 15*4882a593Smuzhiyun * -----+ 0x14000000 ------------------------------------ 16*4882a593Smuzhiyun * CS5 | (SW47) LRAM/URAM, SRAM-LAN-PCMCIA 17*4882a593Smuzhiyun * -----+ 0x18000000 ------------------------------------ 18*4882a593Smuzhiyun * CS6 | ATA, NAND FLASH 19*4882a593Smuzhiyun * -----+ 0x1c000000 ------------------------------------ 20*4882a593Smuzhiyun * CS7 | SH7786 register 21*4882a593Smuzhiyun * -----+------------------------------------------------ 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define NOR_FLASH_ADDR 0x00000000 25*4882a593Smuzhiyun #define NOR_FLASH_SIZE 0x04000000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CS1_BASE 0x05000000 28*4882a593Smuzhiyun #define CS5_BASE 0x15000000 29*4882a593Smuzhiyun #define FPGA_BASE CS1_BASE 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS) 32*4882a593Smuzhiyun #define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define SRSTR_OFS 0x0000 /* System reset register */ 35*4882a593Smuzhiyun #define BDMR_OFS 0x0010 /* Board operating mode resister */ 36*4882a593Smuzhiyun #define IRL0SR_OFS 0x0020 /* IRL0 Status register */ 37*4882a593Smuzhiyun #define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */ 38*4882a593Smuzhiyun #define IRL1SR_OFS 0x0040 /* IRL1 Status register */ 39*4882a593Smuzhiyun #define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */ 40*4882a593Smuzhiyun #define IRL2SR_OFS 0x0060 /* IRL2 Status register */ 41*4882a593Smuzhiyun #define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */ 42*4882a593Smuzhiyun #define IRL3SR_OFS 0x0080 /* IRL3 Status register */ 43*4882a593Smuzhiyun #define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */ 44*4882a593Smuzhiyun #define SOFTINTR_OFS 0x0120 /* Softwear Interrupt register */ 45*4882a593Smuzhiyun #define SLEDR_OFS 0x0130 /* LED control resister */ 46*4882a593Smuzhiyun #define MAPSCIFSWR_OFS 0x0140 /* Map/SCIF Switch register */ 47*4882a593Smuzhiyun #define FPVERR_OFS 0x0150 /* FPGA Version register */ 48*4882a593Smuzhiyun #define FPDATER_OFS 0x0160 /* FPGA Date register */ 49*4882a593Smuzhiyun #define FPYEARR_OFS 0x0170 /* FPGA Year register */ 50*4882a593Smuzhiyun #define TCLKCR_OFS 0x0180 /* TCLK Control register */ 51*4882a593Smuzhiyun #define DIPSWMR_OFS 0x1000 /* DIPSW monitor register */ 52*4882a593Smuzhiyun #define FPODR_OFS 0x1010 /* Output port data register */ 53*4882a593Smuzhiyun #define ATACNR_OFS 0x1020 /* ATA-CN Control/status register */ 54*4882a593Smuzhiyun #define FPINDR_OFS 0x1030 /* Input port data register */ 55*4882a593Smuzhiyun #define MDSWMR_OFS 0x1040 /* MODE SW monitor register */ 56*4882a593Smuzhiyun #define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */ 57*4882a593Smuzhiyun #define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */ 58*4882a593Smuzhiyun #define PCIESLOTSR_OFS 0x1070 /* PCIexpress Slot status register */ 59*4882a593Smuzhiyun #define ETHERPORTSR_OFS 0x1080 /* EtherPhy Port status register */ 60*4882a593Smuzhiyun #define LATCHCR_OFS 0x3000 /* Latch control register */ 61*4882a593Smuzhiyun #define LATCUAR_OFS 0x3010 /* Latch upper address register */ 62*4882a593Smuzhiyun #define LATCLAR_OFS 0x3012 /* Latch lower address register */ 63*4882a593Smuzhiyun #define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */ 64*4882a593Smuzhiyun #define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define CHARLED_OFS 0x2000 /* Character LED */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* __MACH_URQUELL_H */ 69*4882a593Smuzhiyun 70