xref: /OK3568_Linux_fs/u-boot/include/linux/mtd/doc2000.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Linux driver for Disk-On-Chip devices
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright © 1999 Machine Vision Holdings, Inc.
5*4882a593Smuzhiyun  * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
6*4882a593Smuzhiyun  * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com>
7*4882a593Smuzhiyun  * Copyright © 2002-2003 SnapGear Inc
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #ifndef __MTD_DOC2000_H__
14*4882a593Smuzhiyun #define __MTD_DOC2000_H__
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
17*4882a593Smuzhiyun #if 0
18*4882a593Smuzhiyun #include <linux/mutex.h>
19*4882a593Smuzhiyun #endif
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define DoC_Sig1 0
22*4882a593Smuzhiyun #define DoC_Sig2 1
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define DoC_ChipID		0x1000
25*4882a593Smuzhiyun #define DoC_DOCStatus		0x1001
26*4882a593Smuzhiyun #define DoC_DOCControl		0x1002
27*4882a593Smuzhiyun #define DoC_FloorSelect		0x1003
28*4882a593Smuzhiyun #define DoC_CDSNControl		0x1004
29*4882a593Smuzhiyun #define DoC_CDSNDeviceSelect	0x1005
30*4882a593Smuzhiyun #define DoC_ECCConf		0x1006
31*4882a593Smuzhiyun #define DoC_2k_ECCStatus	0x1007
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define DoC_CDSNSlowIO		0x100d
34*4882a593Smuzhiyun #define DoC_ECCSyndrome0	0x1010
35*4882a593Smuzhiyun #define DoC_ECCSyndrome1	0x1011
36*4882a593Smuzhiyun #define DoC_ECCSyndrome2	0x1012
37*4882a593Smuzhiyun #define DoC_ECCSyndrome3	0x1013
38*4882a593Smuzhiyun #define DoC_ECCSyndrome4	0x1014
39*4882a593Smuzhiyun #define DoC_ECCSyndrome5	0x1015
40*4882a593Smuzhiyun #define DoC_AliasResolution	0x101b
41*4882a593Smuzhiyun #define DoC_ConfigInput		0x101c
42*4882a593Smuzhiyun #define DoC_ReadPipeInit	0x101d
43*4882a593Smuzhiyun #define DoC_WritePipeTerm	0x101e
44*4882a593Smuzhiyun #define DoC_LastDataRead	0x101f
45*4882a593Smuzhiyun #define DoC_NOP			0x1020
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define DoC_Mil_CDSN_IO		0x0800
48*4882a593Smuzhiyun #define DoC_2k_CDSN_IO		0x1800
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define DoC_Mplus_NOP			0x1002
51*4882a593Smuzhiyun #define DoC_Mplus_AliasResolution	0x1004
52*4882a593Smuzhiyun #define DoC_Mplus_DOCControl		0x1006
53*4882a593Smuzhiyun #define DoC_Mplus_AccessStatus		0x1008
54*4882a593Smuzhiyun #define DoC_Mplus_DeviceSelect		0x1008
55*4882a593Smuzhiyun #define DoC_Mplus_Configuration		0x100a
56*4882a593Smuzhiyun #define DoC_Mplus_OutputControl		0x100c
57*4882a593Smuzhiyun #define DoC_Mplus_FlashControl		0x1020
58*4882a593Smuzhiyun #define DoC_Mplus_FlashSelect 		0x1022
59*4882a593Smuzhiyun #define DoC_Mplus_FlashCmd		0x1024
60*4882a593Smuzhiyun #define DoC_Mplus_FlashAddress		0x1026
61*4882a593Smuzhiyun #define DoC_Mplus_FlashData0		0x1028
62*4882a593Smuzhiyun #define DoC_Mplus_FlashData1		0x1029
63*4882a593Smuzhiyun #define DoC_Mplus_ReadPipeInit		0x102a
64*4882a593Smuzhiyun #define DoC_Mplus_LastDataRead		0x102c
65*4882a593Smuzhiyun #define DoC_Mplus_LastDataRead1		0x102d
66*4882a593Smuzhiyun #define DoC_Mplus_WritePipeTerm 	0x102e
67*4882a593Smuzhiyun #define DoC_Mplus_ECCSyndrome0		0x1040
68*4882a593Smuzhiyun #define DoC_Mplus_ECCSyndrome1		0x1041
69*4882a593Smuzhiyun #define DoC_Mplus_ECCSyndrome2		0x1042
70*4882a593Smuzhiyun #define DoC_Mplus_ECCSyndrome3		0x1043
71*4882a593Smuzhiyun #define DoC_Mplus_ECCSyndrome4		0x1044
72*4882a593Smuzhiyun #define DoC_Mplus_ECCSyndrome5		0x1045
73*4882a593Smuzhiyun #define DoC_Mplus_ECCConf 		0x1046
74*4882a593Smuzhiyun #define DoC_Mplus_Toggle		0x1046
75*4882a593Smuzhiyun #define DoC_Mplus_DownloadStatus	0x1074
76*4882a593Smuzhiyun #define DoC_Mplus_CtrlConfirm		0x1076
77*4882a593Smuzhiyun #define DoC_Mplus_Power			0x1fff
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /* How to access the device?
80*4882a593Smuzhiyun  * On ARM, it'll be mmap'd directly with 32-bit wide accesses.
81*4882a593Smuzhiyun  * On PPC, it's mmap'd and 16-bit wide.
82*4882a593Smuzhiyun  * Others use readb/writeb
83*4882a593Smuzhiyun  */
84*4882a593Smuzhiyun #if defined(__arm__)
85*4882a593Smuzhiyun #define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2))))
86*4882a593Smuzhiyun #define WriteDOC_(d, adr, reg)  do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0)
87*4882a593Smuzhiyun #define DOC_IOREMAP_LEN 0x8000
88*4882a593Smuzhiyun #elif defined(__ppc__)
89*4882a593Smuzhiyun #define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1))))
90*4882a593Smuzhiyun #define WriteDOC_(d, adr, reg)  do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0)
91*4882a593Smuzhiyun #define DOC_IOREMAP_LEN 0x4000
92*4882a593Smuzhiyun #else
93*4882a593Smuzhiyun #define ReadDOC_(adr, reg)      readb((void __iomem *)(adr) + (reg))
94*4882a593Smuzhiyun #define WriteDOC_(d, adr, reg)  writeb(d, (void __iomem *)(adr) + (reg))
95*4882a593Smuzhiyun #define DOC_IOREMAP_LEN 0x2000
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #if defined(__i386__) || defined(__x86_64__)
100*4882a593Smuzhiyun #define USE_MEMCPY
101*4882a593Smuzhiyun #endif
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* These are provided to directly use the DoC_xxx defines */
104*4882a593Smuzhiyun #define ReadDOC(adr, reg)      ReadDOC_(adr,DoC_##reg)
105*4882a593Smuzhiyun #define WriteDOC(d, adr, reg)  WriteDOC_(d,adr,DoC_##reg)
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #define DOC_MODE_RESET		0
108*4882a593Smuzhiyun #define DOC_MODE_NORMAL		1
109*4882a593Smuzhiyun #define DOC_MODE_RESERVED1	2
110*4882a593Smuzhiyun #define DOC_MODE_RESERVED2	3
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #define DOC_MODE_CLR_ERR	0x80
113*4882a593Smuzhiyun #define	DOC_MODE_RST_LAT	0x10
114*4882a593Smuzhiyun #define	DOC_MODE_BDECT		0x08
115*4882a593Smuzhiyun #define DOC_MODE_MDWREN	0x04
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define DOC_ChipID_Doc2k	0x20
118*4882a593Smuzhiyun #define DOC_ChipID_Doc2kTSOP	0x21	/* internal number for MTD */
119*4882a593Smuzhiyun #define DOC_ChipID_DocMil	0x30
120*4882a593Smuzhiyun #define DOC_ChipID_DocMilPlus32	0x40
121*4882a593Smuzhiyun #define DOC_ChipID_DocMilPlus16	0x41
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun #define CDSN_CTRL_FR_B		0x80
124*4882a593Smuzhiyun #define CDSN_CTRL_FR_B0		0x40
125*4882a593Smuzhiyun #define CDSN_CTRL_FR_B1		0x80
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define CDSN_CTRL_ECC_IO	0x20
128*4882a593Smuzhiyun #define CDSN_CTRL_FLASH_IO	0x10
129*4882a593Smuzhiyun #define CDSN_CTRL_WP		0x08
130*4882a593Smuzhiyun #define CDSN_CTRL_ALE		0x04
131*4882a593Smuzhiyun #define CDSN_CTRL_CLE		0x02
132*4882a593Smuzhiyun #define CDSN_CTRL_CE		0x01
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun #define DOC_ECC_RESET		0
135*4882a593Smuzhiyun #define DOC_ECC_ERROR		0x80
136*4882a593Smuzhiyun #define DOC_ECC_RW		0x20
137*4882a593Smuzhiyun #define DOC_ECC__EN		0x08
138*4882a593Smuzhiyun #define DOC_TOGGLE_BIT		0x04
139*4882a593Smuzhiyun #define DOC_ECC_RESV		0x02
140*4882a593Smuzhiyun #define DOC_ECC_IGNORE		0x01
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #define DOC_FLASH_CE		0x80
143*4882a593Smuzhiyun #define DOC_FLASH_WP		0x40
144*4882a593Smuzhiyun #define DOC_FLASH_BANK		0x02
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /* We have to also set the reserved bit 1 for enable */
147*4882a593Smuzhiyun #define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
148*4882a593Smuzhiyun #define DOC_ECC_DIS (DOC_ECC_RESV)
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun struct Nand {
151*4882a593Smuzhiyun 	char floor, chip;
152*4882a593Smuzhiyun 	unsigned long curadr;
153*4882a593Smuzhiyun 	unsigned char curmode;
154*4882a593Smuzhiyun 	/* Also some erase/write/pipeline info when we get that far */
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun #define MAX_FLOORS 4
158*4882a593Smuzhiyun #define MAX_CHIPS 4
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun #define MAX_FLOORS_MIL 1
161*4882a593Smuzhiyun #define MAX_CHIPS_MIL 1
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun #define MAX_FLOORS_MPLUS 2
164*4882a593Smuzhiyun #define MAX_CHIPS_MPLUS 1
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #define ADDR_COLUMN 1
167*4882a593Smuzhiyun #define ADDR_PAGE 2
168*4882a593Smuzhiyun #define ADDR_COLUMN_PAGE 3
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun struct DiskOnChip {
171*4882a593Smuzhiyun 	unsigned long physadr;
172*4882a593Smuzhiyun 	void __iomem *virtadr;
173*4882a593Smuzhiyun 	unsigned long totlen;
174*4882a593Smuzhiyun 	unsigned char ChipID; /* Type of DiskOnChip */
175*4882a593Smuzhiyun 	int ioreg;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	unsigned long mfr; /* Flash IDs - only one type of flash per device */
178*4882a593Smuzhiyun 	unsigned long id;
179*4882a593Smuzhiyun 	int chipshift;
180*4882a593Smuzhiyun 	char page256;
181*4882a593Smuzhiyun 	char pageadrlen;
182*4882a593Smuzhiyun 	char interleave; /* Internal interleaving - Millennium Plus style */
183*4882a593Smuzhiyun 	unsigned long erasesize;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	int curfloor;
186*4882a593Smuzhiyun 	int curchip;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	int numchips;
189*4882a593Smuzhiyun 	struct Nand *chips;
190*4882a593Smuzhiyun 	struct mtd_info *nextdoc;
191*4882a593Smuzhiyun /* XXX U-BOOT XXX */
192*4882a593Smuzhiyun #if 0
193*4882a593Smuzhiyun 	struct mutex lock;
194*4882a593Smuzhiyun #endif
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun /* XXX U-BOOT XXX */
200*4882a593Smuzhiyun #if 1
201*4882a593Smuzhiyun /*
202*4882a593Smuzhiyun  * NAND Flash Manufacturer ID Codes
203*4882a593Smuzhiyun  */
204*4882a593Smuzhiyun #define NAND_MFR_TOSHIBA   0x98
205*4882a593Smuzhiyun #define NAND_MFR_SAMSUNG   0xec
206*4882a593Smuzhiyun #endif
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun #endif /* __MTD_DOC2000_H__ */
209